Name Implemented tests Planned tests Implementation progress Passing runs Total runs Pass Rate
bus_monitor 1 1100% 1 1100%
bus_rx_flow 2 2100% 2 2100%
bus_timers 1 1100% 1 1100%
bus_tx 5 5100% 19 19100%
bus_tx_flow 5 5100% 9 9100%
ccc 1 1100% 1 1100%
descriptor_rx 1 1100% 1 1100%
descriptor_tx 1 1100% 1 1100%
drivers 0 10.0% 0 0 --%
edge_detector 6 6100% 6 6100%
i3c_bus_monitor 2 2100% 2 2100%
pec 1 1100% 1 1100%
target_axi_filtering 19 19100% 19 19100%
tti_queues 13 13100% 13 13100%
width_converter_8toN 2 2100% 2 2100%
width_converter_Nto8 2 2100% 2 2100%

Progress of stages

Stage Implemented tests Planned tests Implementation progress Passing runs Total runs Pass Rate
N.A. 62 6398.4% 80 80100%
Testplan simulation results
Name Implemented tests Planned tests Implementation progress Passing runs Total runs Pass Rate
Target 10 10 100% 10 10100%
Data over-/underflow handling 6 6 100% 6 6100%
CCC handling 21 21 100% 26 26100%
CSR access check 6 6 100% 6 6100%
Target error detection 6 6 100% 6 6100%
Enter and exit HDR mode 4 4 100% 4 4100%
Target interrupts 4 4 100% 8 8100%
Recovery mode tests 17 17 100% 17 17100%
Recovery bypass 10 1190.9% 10 10100%
target_peripheral_reset 2 2 100% 2 2100%

Progress of stages

Stage Implemented tests Planned tests Implementation progress Passing runs Total runs Pass Rate
N.A. 86 8798.9% 95 95100%