| ccc_getstatus | ccc_getstatus | 8.774 | 93477.200 | 1 | 1 | 100% |
| ccc_setdasa | ccc_setdasa | 2.705 | 25030.000 | 1 | 1 | 100% |
| ccc_setdasa_nack | ccc_setdasa_nack | 1.526 | 12781.560 | 1 | 1 | 100% |
| ccc_setnewda | ccc_setnewda | 1.219 | 6732.000 | 1 | 1 | 100% |
| ccc_rstdaa | ccc_rstdaa | 0.867 | 2156.000 | 1 | 1 | 100% |
| ccc_getbcr | ccc_getbcr | 1.228 | 6831.240 | 1 | 1 | 100% |
| ccc_getdcr | ccc_getdcr | 1.203 | 6801.240 | 1 | 1 | 100% |
| ccc_getmwl | ccc_getmwl | 1.313 | 8225.400 | 1 | 1 | 100% |
| ccc_getmrl | ccc_getmrl | 1.431 | 9665.560 | 1 | 1 | 100% |
| ccc_setaasa | ccc_setaasa | 0.722 | 2062.000 | 1 | 1 | 100% |
| ccc_setaasa_ignore | ccc_setaasa_ignore | 0.673 | 2020.000 | 1 | 1 | 100% |
| ccc_setaasa_single | ccc_setaasa_single | 0.640 | 1992.000 | 2 | 2 | 100% |
| ccc_getpid | ccc_getpid | 1.882 | 14032.040 | 1 | 1 | 100% |
| ccc_enec_disec_direct | ccc_enec_disec_direct | 3.895 | 35353.040 | 1 | 1 | 100% |
| ccc_enec_disec_bcast | ccc_enec_disec_bcast | 0.952 | 5090.000 | 1 | 1 | 100% |
| ccc_setmwl_direct | ccc_setmwl_direct | 5.745 | 58693.400 | 1 | 1 | 100% |
| ccc_setmrl_direct | ccc_setmrl_direct | 6.814 | 69521.560 | 1 | 1 | 100% |
| ccc_setmwl_bcast | ccc_setmwl_bcast | 0.863 | 3504.000 | 1 | 1 | 100% |
| ccc_setmrl_bcast | ccc_setmrl_bcast | 0.916 | 4232.000 | 1 | 1 | 100% |
| ccc_rstact | ccc_rstact | 1.449 | 8153.000 | 6 | 6 | 100% |
| ccc_direct_multiple_wr | ccc_direct_multiple_wr | 1.457 | 11071.900 | 1 | 1 | 100% |
| ccc_direct_multiple_rd | ccc_direct_multiple_rd | 1.880 | 15040.910 | 1 | 1 | 100% |
| ccc_entdaa | ccc_entdaa | 2.505 | 21785.240 | 1 | 1 | 100% |
| ccc_entdaa_arb_lost | ccc_entdaa_arb_lost | 2.280 | 19433.120 | 1 | 1 | 100% |
| ccc_entdaa_early_stop | ccc_entdaa_early_stop | 1.649 | 11961.120 | 1 | 1 | 100% |
| ccc_entdaa_te3_te4 | ccc_entdaa_te3_te4 | 3.599 | 32796.000 | 1 | 1 | 100% |
| ccc_enthdr_all_codes | ccc_enthdr_all_codes | 3.982 | 40799.320 | 1 | 1 | 100% |
| ccc_error_det_enable | ccc_error_det_enable | 1.320 | 6901.120 | 1 | 1 | 100% |
| ccc_getcaps | ccc_getcaps | 2.953 | 28036.360 | 1 | 1 | 100% |
| ccc_setdasa_padding_err | ccc_setdasa_padding_err | 2.186 | 16333.120 | 1 | 1 | 100% |
| | ccc_setdasa_padding_err_det_disabled | 1.666 | 13051.120 | 1 | 1 | 100% |
| ccc_te2_parity | ccc_te2_parity | 2.559 | 20212.000 | 1 | 1 | 100% |
| ccc_te5_wrong_direction | ccc_te5_wrong_direction | 2.079 | 17678.400 | 1 | 1 | 100% |
| ccc_unknown_broadcast | ccc_unknown_broadcast | 1.315 | 9685.960 | 1 | 1 | 100% |
| ccc_unsupported_direct_nack | ccc_unsupported_direct_nack | 2.737 | 25693.240 | 1 | 1 | 100% |
| ccc_vendor_codes | ccc_vendor_codes | 3.265 | 31710.620 | 1 | 1 | 100% |
| ccc_abort_bcast_stop | ccc_abort_bcast_stop | 1.578 | 11456.000 | 1 | 1 | 100% |
| ccc_abort_get_sr | ccc_abort_get_sr | 4.965 | 51980.360 | 1 | 1 | 100% |
| ccc_addr_lifecycle | ccc_addr_lifecycle | 1.796 | 14542.000 | 1 | 1 | 100% |
| ccc_back_to_back | ccc_back_to_back | 6.800 | 74325.800 | 1 | 1 | 100% |
| ccc_chain_bcast | ccc_chain_bcast | 1.127 | 7179.040 | 1 | 1 | 100% |
| ccc_chain_direct | ccc_chain_direct | 1.138 | 6610.660 | 1 | 1 | 100% |
| ccc_random_interleave | ccc_random_interleave | 7.207 | 78644.040 | 1 | 1 | 100% |
| ccc_rstact_arm_clear_on_start | ccc_rstact_arm_clear_on_start | 1.483 | 9878.000 | 1 | 1 | 100% |
| ccc_rstact_escalation_clear | ccc_rstact_escalation_clear | 2.202 | 17184.000 | 1 | 1 | 100% |
| ccc_rstact_read_action | ccc_rstact_read_action | 3.836 | 36325.360 | 1 | 1 | 100% |
| ccc_rstact_unsupported_db | ccc_rstact_unsupported_db | 3.261 | 32003.400 | 1 | 1 | 100% |
| ccc_rstact_vt_detect | ccc_rstact_vt_detect | 19.243 | 220429.500 | 1 | 1 | 100% |
| ccc_rstact_vt_detect_no_reset_arm | ccc_rstact_vt_detect_no_reset_arm | 1.088 | 5368.000 | 1 | 1 | 100% |
| ccc_setmwl_sr_abort_during_data | ccc_setmwl_sr_abort_during_data | 2.071 | 15129.120 | 1 | 1 | 100% |
| ccc_getstatus_abort_then_chain_setmwl | ccc_getstatus_abort_then_chain_setmwl | 1.934 | 13714.000 | 1 | 1 | 100% |
| ccc_getstatus_sr_abort_clears_protocol_err | ccc_getstatus_sr_abort_clears_protocol_err | 1.631 | 10016.000 | 1 | 1 | 100% |
| ccc_getstatus_sr_abort_done_assert | ccc_getstatus_sr_abort_done_assert | 1.312 | 9740.140 | 1 | 1 | 100% |
| ccc_entdaa_virtual_only | ccc_entdaa_virtual_only | 1.688 | 12003.120 | 1 | 1 | 100% |
| ccc_entdaa_main_only | ccc_entdaa_main_only | 1.706 | 12001.120 | 1 | 1 | 100% |
| ccc_entdaa_both_addressed | ccc_entdaa_both_addressed | 1.543 | 9341.240 | 1 | 1 | 100% |
| ccc_te0_reserved_addr_direct | ccc_te0_reserved_addr_direct | 1.397 | 6647.120 | 1 | 1 | 100% |
| ccc_direct_chain_7e_termination | ccc_direct_chain_7e_termination | 1.526 | 9961.120 | 1 | 1 | 100% |
| ccc_all_det_en_toggle | ccc_all_det_en_toggle | 3.471 | 21305.120 | 1 | 1 | 100% |
| ccc_te2_direct_def_byte_tbit | ccc_te2_direct_def_byte_tbit | 1.271 | 6791.120 | 1 | 1 | 100% |
| ccc_direct_extra_data_before_addr | ccc_direct_extra_data_before_addr | 1.267 | 7298.000 | 1 | 1 | 100% |
| ccc_te2_data_byte_direct_set | ccc_te2_data_byte_direct_set | 1.271 | 6891.120 | 1 | 1 | 100% |
| ccc_entdaa_te3_det_en_toggle | ccc_entdaa_te3_det_en_toggle | 2.433 | 18864.000 | 1 | 1 | 100% |
| ccc_entdaa_te4_det_en_disabled | ccc_entdaa_te4_det_en_disabled | 1.203 | 8658.000 | 1 | 1 | 100% |
| ccc_stop_mid_transfer | ccc_stop_mid_transfer | 2.048 | 14961.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_waitstart | ccc_entdaa_stop_in_waitstart | 2.446 | 20321.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_sendidbit | ccc_entdaa_stop_in_sendidbit | 2.581 | 21779.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_receiveaddr | ccc_entdaa_stop_in_receiveaddr | 2.966 | 26579.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_ackrsvdbyte | ccc_entdaa_stop_in_ackrsvdbyte | 2.527 | 21139.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_sendnack | ccc_entdaa_stop_in_sendnack | 2.518 | 21139.120 | 1 | 1 | 100% |
| ccc_stop_during_target_read | ccc_stop_during_target_read | 3.116 | 25475.120 | 1 | 1 | 100% |
| ccc_csr_concurrent_stress | ccc_csr_concurrent_stress | 25.760 | 188107.280 | 1 | 1 | 100% |
| entdaa | | | | 0 | 0 | --% |
| entdaa_parity_errors | | | | 0 | 0 | --% |
| | TOTAL | | | 78 | 78 | 100% |