| ccc_getstatus | ccc_getstatus | 5.632 | 85733.200 | 1 | 1 | 100% |
| ccc_setdasa | ccc_setdasa | 2.077 | 28104.000 | 1 | 1 | 100% |
| ccc_setdasa_nack | ccc_setdasa_nack | 1.075 | 12781.560 | 1 | 1 | 100% |
| ccc_setnewda | ccc_setnewda | 0.882 | 6732.000 | 1 | 1 | 100% |
| ccc_rstdaa | ccc_rstdaa | 0.633 | 2156.000 | 1 | 1 | 100% |
| ccc_getbcr | ccc_getbcr | 0.904 | 6831.240 | 1 | 1 | 100% |
| ccc_getdcr | ccc_getdcr | 0.915 | 6829.240 | 1 | 1 | 100% |
| ccc_getmwl | ccc_getmwl | 0.946 | 8225.400 | 1 | 1 | 100% |
| ccc_getmrl | ccc_getmrl | 1.023 | 9665.560 | 1 | 1 | 100% |
| ccc_setaasa | ccc_setaasa | 0.538 | 2062.000 | 1 | 1 | 100% |
| ccc_setaasa_ignore | ccc_setaasa_ignore | 0.498 | 2020.000 | 1 | 1 | 100% |
| ccc_setaasa_single | ccc_setaasa_single | 0.482 | 1992.000 | 2 | 2 | 100% |
| ccc_getpid | ccc_getpid | 1.351 | 14032.040 | 1 | 1 | 100% |
| ccc_enec_disec_direct | ccc_enec_disec_direct | 2.744 | 35353.040 | 1 | 1 | 100% |
| ccc_enec_disec_bcast | ccc_enec_disec_bcast | 0.718 | 5090.000 | 1 | 1 | 100% |
| ccc_setmwl_direct | ccc_setmwl_direct | 4.042 | 58693.400 | 1 | 1 | 100% |
| ccc_setmrl_direct | ccc_setmrl_direct | 4.680 | 69521.560 | 1 | 1 | 100% |
| ccc_setmwl_bcast | ccc_setmwl_bcast | 0.635 | 3504.000 | 1 | 1 | 100% |
| ccc_setmrl_bcast | ccc_setmrl_bcast | 0.678 | 4232.000 | 1 | 1 | 100% |
| ccc_rstact | ccc_rstact | 1.065 | 8153.000 | 6 | 6 | 100% |
| ccc_direct_multiple_wr | ccc_direct_multiple_wr | 1.076 | 11071.900 | 1 | 1 | 100% |
| ccc_direct_multiple_rd | ccc_direct_multiple_rd | 1.386 | 15042.510 | 1 | 1 | 100% |
| ccc_entdaa | ccc_entdaa | 1.752 | 21785.240 | 1 | 1 | 100% |
| ccc_entdaa_arb_lost | ccc_entdaa_arb_lost | 1.604 | 19433.120 | 1 | 1 | 100% |
| ccc_entdaa_early_stop | ccc_entdaa_early_stop | 1.197 | 11961.120 | 1 | 1 | 100% |
| ccc_entdaa_te3_te4 | ccc_entdaa_te3_te4 | 2.509 | 32796.000 | 1 | 1 | 100% |
| ccc_enthdr_all_codes | ccc_enthdr_all_codes | 2.828 | 40799.320 | 1 | 1 | 100% |
| ccc_error_det_enable | ccc_error_det_enable | 0.987 | 6901.120 | 1 | 1 | 100% |
| ccc_getcaps | ccc_getcaps | 2.109 | 28036.360 | 1 | 1 | 100% |
| ccc_setdasa_padding_err | ccc_setdasa_padding_err | 1.566 | 16333.120 | 1 | 1 | 100% |
| | ccc_setdasa_padding_err_det_disabled | 1.207 | 13051.120 | 1 | 1 | 100% |
| ccc_te2_parity | ccc_te2_parity | 1.831 | 20212.000 | 1 | 1 | 100% |
| ccc_te5_wrong_direction | ccc_te5_wrong_direction | 1.506 | 17681.600 | 1 | 1 | 100% |
| ccc_unknown_broadcast | ccc_unknown_broadcast | 0.972 | 9685.960 | 1 | 1 | 100% |
| ccc_unsupported_direct_nack | ccc_unsupported_direct_nack | 1.981 | 25699.640 | 1 | 1 | 100% |
| ccc_vendor_codes | ccc_vendor_codes | 2.287 | 31710.620 | 1 | 1 | 100% |
| ccc_abort_bcast_stop | ccc_abort_bcast_stop | 1.123 | 11456.000 | 1 | 1 | 100% |
| ccc_abort_get_sr | ccc_abort_get_sr | 3.515 | 51978.360 | 1 | 1 | 100% |
| ccc_addr_lifecycle | ccc_addr_lifecycle | 1.313 | 14542.000 | 1 | 1 | 100% |
| ccc_back_to_back | ccc_back_to_back | 4.811 | 74325.800 | 1 | 1 | 100% |
| ccc_chain_bcast | ccc_chain_bcast | 0.837 | 7179.040 | 1 | 1 | 100% |
| ccc_chain_direct | ccc_chain_direct | 0.859 | 6610.660 | 1 | 1 | 100% |
| ccc_random_interleave | ccc_random_interleave | 5.327 | 83684.600 | 1 | 1 | 100% |
| ccc_rstact_arm_clear_on_start | ccc_rstact_arm_clear_on_start | 1.091 | 9878.000 | 1 | 1 | 100% |
| ccc_rstact_escalation_clear | ccc_rstact_escalation_clear | 1.599 | 17184.000 | 1 | 1 | 100% |
| ccc_rstact_read_action | ccc_rstact_read_action | 2.761 | 36325.360 | 1 | 1 | 100% |
| ccc_rstact_unsupported_db | ccc_rstact_unsupported_db | 2.343 | 32003.400 | 1 | 1 | 100% |
| ccc_rstact_vt_detect | ccc_rstact_vt_detect | 13.389 | 219611.880 | 1 | 1 | 100% |
| ccc_rstact_vt_detect_no_reset_arm | ccc_rstact_vt_detect_no_reset_arm | 0.830 | 5368.000 | 1 | 1 | 100% |
| ccc_setmwl_sr_abort_during_data | ccc_setmwl_sr_abort_during_data | 1.437 | 15129.120 | 1 | 1 | 100% |
| ccc_getstatus_abort_then_chain_setmwl | ccc_getstatus_abort_then_chain_setmwl | 1.371 | 13714.000 | 1 | 1 | 100% |
| ccc_getstatus_sr_abort_clears_protocol_err | ccc_getstatus_sr_abort_clears_protocol_err | 1.173 | 10016.000 | 1 | 1 | 100% |
| ccc_getstatus_sr_abort_done_assert | ccc_getstatus_sr_abort_done_assert | 0.908 | 9740.140 | 1 | 1 | 100% |
| ccc_entdaa_virtual_only | ccc_entdaa_virtual_only | 1.241 | 12003.120 | 1 | 1 | 100% |
| ccc_entdaa_main_only | ccc_entdaa_main_only | 1.231 | 12001.120 | 1 | 1 | 100% |
| ccc_entdaa_both_addressed | ccc_entdaa_both_addressed | 1.099 | 9341.240 | 1 | 1 | 100% |
| ccc_te0_reserved_addr_direct | ccc_te0_reserved_addr_direct | 1.005 | 6647.120 | 1 | 1 | 100% |
| ccc_direct_chain_7e_termination | ccc_direct_chain_7e_termination | 1.073 | 9961.120 | 1 | 1 | 100% |
| ccc_all_det_en_toggle | ccc_all_det_en_toggle | 2.472 | 21305.120 | 1 | 1 | 100% |
| ccc_te2_direct_def_byte_tbit | ccc_te2_direct_def_byte_tbit | 0.912 | 6791.120 | 1 | 1 | 100% |
| ccc_direct_extra_data_before_addr | ccc_direct_extra_data_before_addr | 0.906 | 7298.000 | 1 | 1 | 100% |
| ccc_te2_data_byte_direct_set | ccc_te2_data_byte_direct_set | 0.920 | 6891.120 | 1 | 1 | 100% |
| ccc_entdaa_te3_det_en_toggle | ccc_entdaa_te3_det_en_toggle | 1.702 | 18864.000 | 1 | 1 | 100% |
| ccc_entdaa_te4_det_en_disabled | ccc_entdaa_te4_det_en_disabled | 0.861 | 8658.000 | 1 | 1 | 100% |
| ccc_stop_mid_transfer | ccc_stop_mid_transfer | 1.451 | 14961.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_waitstart | ccc_entdaa_stop_in_waitstart | 1.698 | 20321.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_sendidbit | ccc_entdaa_stop_in_sendidbit | 1.794 | 21779.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_receiveaddr | ccc_entdaa_stop_in_receiveaddr | 2.084 | 26579.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_ackrsvdbyte | ccc_entdaa_stop_in_ackrsvdbyte | 1.742 | 21139.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_sendnack | ccc_entdaa_stop_in_sendnack | 1.767 | 21139.120 | 1 | 1 | 100% |
| ccc_stop_during_target_read | ccc_stop_during_target_read | 2.176 | 25475.120 | 1 | 1 | 100% |
| ccc_csr_concurrent_stress | ccc_csr_concurrent_stress | 19.643 | 193831.280 | 1 | 1 | 100% |
| entdaa | | | | 0 | 0 | --% |
| entdaa_parity_errors | | | | 0 | 0 | --% |
| | TOTAL | | | 78 | 78 | 100% |