| ccc_getstatus | ccc_getstatus | 7.363 | 112839.200 | 1 | 1 | 100% |
| ccc_setdasa | ccc_setdasa | 1.886 | 25106.000 | 1 | 1 | 100% |
| ccc_setdasa_nack | ccc_setdasa_nack | 1.076 | 12781.560 | 1 | 1 | 100% |
| ccc_setnewda | ccc_setnewda | 0.870 | 6732.000 | 1 | 1 | 100% |
| ccc_rstdaa | ccc_rstdaa | 0.623 | 2156.000 | 1 | 1 | 100% |
| ccc_getbcr | ccc_getbcr | 0.865 | 6803.240 | 1 | 1 | 100% |
| ccc_getdcr | ccc_getdcr | 0.907 | 6829.240 | 1 | 1 | 100% |
| ccc_getmwl | ccc_getmwl | 0.934 | 8225.400 | 1 | 1 | 100% |
| ccc_getmrl | ccc_getmrl | 1.031 | 9665.560 | 1 | 1 | 100% |
| ccc_setaasa | ccc_setaasa | 0.528 | 2062.000 | 1 | 1 | 100% |
| ccc_setaasa_ignore | ccc_setaasa_ignore | 0.510 | 2020.000 | 1 | 1 | 100% |
| ccc_setaasa_single | ccc_setaasa_single | 0.476 | 1992.000 | 2 | 2 | 100% |
| ccc_getpid | ccc_getpid | 1.354 | 14060.040 | 1 | 1 | 100% |
| ccc_enec_disec_direct | ccc_enec_disec_direct | 2.762 | 35353.040 | 1 | 1 | 100% |
| ccc_enec_disec_bcast | ccc_enec_disec_bcast | 0.697 | 5090.000 | 1 | 1 | 100% |
| ccc_setmwl_direct | ccc_setmwl_direct | 4.059 | 58693.400 | 1 | 1 | 100% |
| ccc_setmrl_direct | ccc_setmrl_direct | 4.709 | 69521.560 | 1 | 1 | 100% |
| ccc_setmwl_bcast | ccc_setmwl_bcast | 0.625 | 3504.000 | 1 | 1 | 100% |
| ccc_setmrl_bcast | ccc_setmrl_bcast | 0.658 | 4232.000 | 1 | 1 | 100% |
| ccc_rstact | ccc_rstact | 1.045 | 8153.000 | 6 | 6 | 100% |
| ccc_direct_multiple_wr | ccc_direct_multiple_wr | 1.061 | 11071.900 | 1 | 1 | 100% |
| ccc_direct_multiple_rd | ccc_direct_multiple_rd | 1.368 | 15040.910 | 1 | 1 | 100% |
| ccc_entdaa | ccc_entdaa | 1.749 | 21785.240 | 1 | 1 | 100% |
| ccc_entdaa_arb_lost | ccc_entdaa_arb_lost | 1.592 | 19433.120 | 1 | 1 | 100% |
| ccc_entdaa_early_stop | ccc_entdaa_early_stop | 1.174 | 11961.120 | 1 | 1 | 100% |
| ccc_entdaa_te3_te4 | ccc_entdaa_te3_te4 | 2.514 | 32796.000 | 1 | 1 | 100% |
| ccc_enthdr_all_codes | ccc_enthdr_all_codes | 2.819 | 40799.320 | 1 | 1 | 100% |
| ccc_error_det_enable | ccc_error_det_enable | 0.945 | 6901.120 | 1 | 1 | 100% |
| ccc_getcaps | ccc_getcaps | 2.102 | 28036.360 | 1 | 1 | 100% |
| ccc_setdasa_padding_err | ccc_setdasa_padding_err | 1.534 | 16333.120 | 1 | 1 | 100% |
| | ccc_setdasa_padding_err_det_disabled | 1.160 | 13051.120 | 1 | 1 | 100% |
| ccc_te2_parity | ccc_te2_parity | 1.792 | 20212.000 | 1 | 1 | 100% |
| ccc_te5_wrong_direction | ccc_te5_wrong_direction | 1.470 | 17678.400 | 1 | 1 | 100% |
| ccc_unknown_broadcast | ccc_unknown_broadcast | 0.968 | 9685.960 | 1 | 1 | 100% |
| ccc_unsupported_direct_nack | ccc_unsupported_direct_nack | 1.974 | 25693.240 | 1 | 1 | 100% |
| ccc_vendor_codes | ccc_vendor_codes | 2.296 | 31710.620 | 1 | 1 | 100% |
| ccc_abort_bcast_stop | ccc_abort_bcast_stop | 1.110 | 11456.000 | 1 | 1 | 100% |
| ccc_abort_get_sr | ccc_abort_get_sr | 3.509 | 51980.360 | 1 | 1 | 100% |
| ccc_addr_lifecycle | ccc_addr_lifecycle | 1.306 | 14542.000 | 1 | 1 | 100% |
| ccc_back_to_back | ccc_back_to_back | 4.769 | 74325.800 | 1 | 1 | 100% |
| ccc_chain_bcast | ccc_chain_bcast | 0.821 | 7179.040 | 1 | 1 | 100% |
| ccc_chain_direct | ccc_chain_direct | 0.836 | 6610.660 | 1 | 1 | 100% |
| ccc_random_interleave | ccc_random_interleave | 5.198 | 81524.520 | 1 | 1 | 100% |
| ccc_rstact_arm_clear_on_start | ccc_rstact_arm_clear_on_start | 1.081 | 9878.000 | 1 | 1 | 100% |
| ccc_rstact_escalation_clear | ccc_rstact_escalation_clear | 1.589 | 17184.000 | 1 | 1 | 100% |
| ccc_rstact_read_action | ccc_rstact_read_action | 2.763 | 36325.360 | 1 | 1 | 100% |
| ccc_rstact_unsupported_db | ccc_rstact_unsupported_db | 2.354 | 32003.400 | 1 | 1 | 100% |
| ccc_rstact_vt_detect | ccc_rstact_vt_detect | 13.576 | 221247.120 | 1 | 1 | 100% |
| ccc_rstact_vt_detect_no_reset_arm | ccc_rstact_vt_detect_no_reset_arm | 0.826 | 5368.000 | 1 | 1 | 100% |
| ccc_setmwl_sr_abort_during_data | ccc_setmwl_sr_abort_during_data | 1.473 | 15129.120 | 1 | 1 | 100% |
| ccc_getstatus_abort_then_chain_setmwl | ccc_getstatus_abort_then_chain_setmwl | 1.377 | 13714.000 | 1 | 1 | 100% |
| ccc_getstatus_sr_abort_clears_protocol_err | ccc_getstatus_sr_abort_clears_protocol_err | 1.180 | 10016.000 | 1 | 1 | 100% |
| ccc_getstatus_sr_abort_done_assert | ccc_getstatus_sr_abort_done_assert | 0.938 | 9740.140 | 1 | 1 | 100% |
| ccc_entdaa_virtual_only | ccc_entdaa_virtual_only | 1.231 | 12003.120 | 1 | 1 | 100% |
| ccc_entdaa_main_only | ccc_entdaa_main_only | 1.207 | 12001.120 | 1 | 1 | 100% |
| ccc_entdaa_both_addressed | ccc_entdaa_both_addressed | 1.084 | 9341.240 | 1 | 1 | 100% |
| ccc_te0_reserved_addr_direct | ccc_te0_reserved_addr_direct | 0.999 | 6647.120 | 1 | 1 | 100% |
| ccc_direct_chain_7e_termination | ccc_direct_chain_7e_termination | 1.073 | 9961.120 | 1 | 1 | 100% |
| ccc_all_det_en_toggle | ccc_all_det_en_toggle | 2.520 | 21305.120 | 1 | 1 | 100% |
| ccc_te2_direct_def_byte_tbit | ccc_te2_direct_def_byte_tbit | 0.930 | 6791.120 | 1 | 1 | 100% |
| ccc_direct_extra_data_before_addr | ccc_direct_extra_data_before_addr | 0.921 | 7298.000 | 1 | 1 | 100% |
| ccc_te2_data_byte_direct_set | ccc_te2_data_byte_direct_set | 0.932 | 6891.120 | 1 | 1 | 100% |
| ccc_entdaa_te3_det_en_toggle | ccc_entdaa_te3_det_en_toggle | 1.717 | 18864.000 | 1 | 1 | 100% |
| ccc_entdaa_te4_det_en_disabled | ccc_entdaa_te4_det_en_disabled | 0.860 | 8658.000 | 1 | 1 | 100% |
| ccc_stop_mid_transfer | ccc_stop_mid_transfer | 1.462 | 14961.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_waitstart | ccc_entdaa_stop_in_waitstart | 1.723 | 20321.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_sendidbit | ccc_entdaa_stop_in_sendidbit | 1.802 | 21779.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_receiveaddr | ccc_entdaa_stop_in_receiveaddr | 2.073 | 26579.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_ackrsvdbyte | ccc_entdaa_stop_in_ackrsvdbyte | 1.795 | 21139.120 | 1 | 1 | 100% |
| ccc_entdaa_stop_in_sendnack | ccc_entdaa_stop_in_sendnack | 1.782 | 21139.120 | 1 | 1 | 100% |
| ccc_stop_during_target_read | ccc_stop_during_target_read | 2.190 | 25475.120 | 1 | 1 | 100% |
| ccc_csr_concurrent_stress | ccc_csr_concurrent_stress | 19.816 | 188497.280 | 1 | 1 | 100% |
| entdaa | | | | 0 | 0 | --% |
| entdaa_parity_errors | | | | 0 | 0 | --% |
| | TOTAL | | | 78 | 78 | 100% |