| axi_filtering_disabled | read_hci_version_csr_id_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_off | 0.041 | 304.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_off | 0.101 | 856.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_off | 0.026 | 308.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_off | 0.025 | 290.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_off | 0.059 | 746.000 | 1 | 1 | 100% |
| axi_filtering_priv | read_hci_version_csr_id_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_on_priv | 0.045 | 274.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_priv | 0.094 | 802.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_on_priv | 0.042 | 536.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_on_priv | 0.041 | 518.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_on_priv | 0.054 | 674.000 | 1 | 1 | 100% |
| axi_filtering_non_priv | read_hci_version_csr_id_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_on_non_priv | 0.063 | 466.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_non_priv | 0.076 | 614.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_on_non_priv | 0.038 | 472.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_on_non_priv | 0.033 | 402.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_on_non_priv | 0.029 | 330.000 | 1 | 1 | 100% |
| axi_filtering_mixed_priv | collision_with_write_id_filter_on_mixed | 0.108 | 826.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_mixed | 0.121 | 994.000 | 1 | 1 | 100% |
| | collision_with_write_mixed_priv | 0.149 | 1156.000 | 1 | 1 | 100% |
| | collision_with_read_mixed_priv | 0.059 | 660.000 | 1 | 1 | 100% |
| bus_stress | collision_with_read | 0.176 | 1216.000 | 1 | 1 | 100% |
| | collision_with_write | 0.080 | 464.000 | 1 | 1 | 100% |
| | write_read_burst | 0.070 | 752.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write | 0.099 | 1106.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read | 0.071 | 758.000 | 1 | 1 | 100% |
| priv_id | priv_id_variation | 0.035 | 302.000 | 1 | 1 | 100% |
| | randomized_id_configuration_swap | | | 0 | 0 | --% |
| | swap_priv_ids_mid_read | | | 0 | 0 | --% |
| | swap_priv_ids_mid_write | | | 0 | 0 | --% |
| | toggle_filtering_mid_read | | | 0 | 0 | --% |
| | toggle_filtering_mid_write | | | 0 | 0 | --% |
| | TOTAL | | | 25 | 43 | 58.1% |