| axi_filtering_disabled | read_hci_version_csr_id_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_off | 0.106 | 720.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_off | 0.083 | 676.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_off | 0.039 | 440.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_off | 0.034 | 374.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_off | 0.116 | 1514.000 | 1 | 1 | 100% |
| axi_filtering_priv | read_hci_version_csr_id_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_on_priv | 0.108 | 802.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_priv | 0.062 | 478.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_on_priv | 0.029 | 308.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_on_priv | 0.035 | 386.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_on_priv | 0.050 | 602.000 | 1 | 1 | 100% |
| axi_filtering_non_priv | read_hci_version_csr_id_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_on_non_priv | 0.065 | 430.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_non_priv | 0.121 | 866.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_on_non_priv | 0.038 | 440.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_on_non_priv | 0.030 | 346.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_on_non_priv | 0.080 | 1034.000 | 1 | 1 | 100% |
| axi_filtering_mixed_priv | collision_with_write_id_filter_on_mixed | 0.078 | 538.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_mixed | 0.059 | 442.000 | 1 | 1 | 100% |
| | collision_with_write_mixed_priv | 0.135 | 1088.000 | 1 | 1 | 100% |
| | collision_with_read_mixed_priv | 0.086 | 854.000 | 1 | 1 | 100% |
| bus_stress | collision_with_read | 0.089 | 1144.000 | 1 | 1 | 100% |
| | collision_with_write | 0.057 | 656.000 | 1 | 1 | 100% |
| | write_read_burst | 0.026 | 500.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write | 0.024 | 410.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read | 0.041 | 842.000 | 1 | 1 | 100% |
| priv_id | priv_id_variation | 0.041 | 302.000 | 1 | 1 | 100% |
| | randomized_id_configuration_swap | | | 0 | 0 | --% |
| | swap_priv_ids_mid_read | | | 0 | 0 | --% |
| | swap_priv_ids_mid_write | | | 0 | 0 | --% |
| | toggle_filtering_mid_read | | | 0 | 0 | --% |
| | toggle_filtering_mid_write | | | 0 | 0 | --% |
| | TOTAL | | | 25 | 43 | 58.1% |