| axi_filtering_disabled | read_hci_version_csr_id_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_off | 0.060 | 448.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_off | 0.115 | 964.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_off | 0.064 | 824.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_off | 0.064 | 818.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_off | 0.041 | 482.000 | 1 | 1 | 100% |
| axi_filtering_priv | read_hci_version_csr_id_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_on_priv | 0.098 | 770.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_priv | 0.064 | 532.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_on_priv | 0.059 | 764.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_on_priv | 0.036 | 434.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_on_priv | 0.108 | 1394.000 | 1 | 1 | 100% |
| axi_filtering_non_priv | read_hci_version_csr_id_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_on_non_priv | 0.029 | 214.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_non_priv | 0.042 | 320.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_on_non_priv | 0.020 | 216.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_on_non_priv | 0.019 | 194.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_on_non_priv | 0.025 | 266.000 | 1 | 1 | 100% |
| axi_filtering_mixed_priv | collision_with_write_id_filter_on_mixed | 0.094 | 706.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_mixed | 0.137 | 876.000 | 1 | 1 | 100% |
| | collision_with_write_mixed_priv | 0.143 | 1204.000 | 1 | 1 | 100% |
| | collision_with_read_mixed_priv | 0.135 | 1142.000 | 1 | 1 | 100% |
| bus_stress | collision_with_read | 0.102 | 1000.000 | 1 | 1 | 100% |
| | collision_with_write | 0.076 | 672.000 | 1 | 1 | 100% |
| | write_read_burst | 0.033 | 488.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write | 0.050 | 746.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read | 0.040 | 602.000 | 1 | 1 | 100% |
| priv_id | priv_id_variation | 0.035 | 302.000 | 1 | 1 | 100% |
| | randomized_id_configuration_swap | | | 0 | 0 | --% |
| | swap_priv_ids_mid_read | | | 0 | 0 | --% |
| | swap_priv_ids_mid_write | | | 0 | 0 | --% |
| | toggle_filtering_mid_read | | | 0 | 0 | --% |
| | toggle_filtering_mid_write | | | 0 | 0 | --% |
| | TOTAL | | | 25 | 43 | 58.1% |