| axi_filtering_disabled | read_hci_version_csr_id_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_off | 0.094 | 576.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_off | 0.052 | 424.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_off | 0.042 | 476.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_off | 0.023 | 230.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_off | 0.113 | 1346.000 | 1 | 1 | 100% |
| axi_filtering_priv | read_hci_version_csr_id_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_on_priv | 0.063 | 482.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_priv | 0.117 | 946.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_on_priv | 0.050 | 584.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_on_priv | 0.066 | 782.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_on_priv | 0.123 | 1322.000 | 1 | 1 | 100% |
| axi_filtering_non_priv | read_hci_version_csr_id_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | collision_with_write_id_filter_on_non_priv | 0.077 | 538.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_non_priv | 0.085 | 642.000 | 1 | 1 | 100% |
| | write_read_burst_id_filter_on_non_priv | 0.037 | 416.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read_id_filter_on_non_priv | 0.033 | 354.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write_id_filter_on_non_priv | 0.044 | 474.000 | 1 | 1 | 100% |
| axi_filtering_mixed_priv | collision_with_write_id_filter_on_mixed | 0.126 | 922.000 | 1 | 1 | 100% |
| | collision_with_read_id_filter_on_mixed | 0.132 | 1034.000 | 1 | 1 | 100% |
| | collision_with_write_mixed_priv | 0.123 | 1032.000 | 1 | 1 | 100% |
| | collision_with_read_mixed_priv | 0.087 | 818.000 | 1 | 1 | 100% |
| bus_stress | collision_with_read | 0.153 | 1144.000 | 1 | 1 | 100% |
| | collision_with_write | 0.088 | 592.000 | 1 | 1 | 100% |
| | write_read_burst | 0.062 | 680.000 | 1 | 1 | 100% |
| | read_burst_collision_with_write | 0.083 | 914.000 | 1 | 1 | 100% |
| | write_burst_collision_with_read | 0.062 | 674.000 | 1 | 1 | 100% |
| priv_id | priv_id_variation | 0.043 | 302.000 | 1 | 1 | 100% |
| | randomized_id_configuration_swap | | | 0 | 0 | --% |
| | swap_priv_ids_mid_read | | | 0 | 0 | --% |
| | swap_priv_ids_mid_write | | | 0 | 0 | --% |
| | toggle_filtering_mid_read | | | 0 | 0 | --% |
| | toggle_filtering_mid_write | | | 0 | 0 | --% |
| | TOTAL | | | 25 | 43 | 58.1% |