| clear_on_nonempty_resp_queue | clear_on_nonempty_resp_queue | 0 | 0 | 0 | 1 | 0.0% |
| clear_on_nonempty_cmd_queue | clear_on_nonempty_cmd_queue | 0 | 0 | 0 | 1 | 0.0% |
| clear_on_nonempty_rx_queue | clear_on_nonempty_rx_queue | 0 | 0 | 0 | 1 | 0.0% |
| clear_on_nonempty_tx_queue | clear_on_nonempty_tx_queue | 0 | 0 | 0 | 1 | 0.0% |
| clear_on_nonempty_ibi_queue | clear_on_nonempty_ibi_queue | 0 | 0 | 0 | 1 | 0.0% |
| cmd_capacity_status | cmd_capacity_status | 0 | 0 | 0 | 1 | 0.0% |
| resp_capacity_status | resp_capacity_status | 0 | 0 | 0 | 1 | 0.0% |
| rx_capacity_status | rx_capacity_status | 0 | 0 | 0 | 1 | 0.0% |
| tx_capacity_status | tx_capacity_status | 0 | 0 | 0 | 1 | 0.0% |
| ibi_capacity_status | ibi_capacity_status | 0 | 0 | 0 | 1 | 0.0% |
| cmd_setup_threshold | cmd_setup_threshold | 0 | 0 | 0 | 1 | 0.0% |
| resp_setup_threshold | resp_setup_threshold | 0 | 0 | 0 | 1 | 0.0% |
| rx_setup_threshold | rx_setup_threshold | 0 | 0 | 0 | 1 | 0.0% |
| tx_setup_threshold | tx_setup_threshold | 0 | 0 | 0 | 1 | 0.0% |
| ibi_setup_threshold | ibi_setup_threshold | 0 | 0 | 0 | 1 | 0.0% |
| resp_should_raise_thld_trig | resp_should_raise_thld_trig | 0 | 0 | 0 | 1 | 0.0% |
| rx_should_raise_thld_trig | rx_should_raise_thld_trig | 0 | 0 | 0 | 1 | 0.0% |
| ibi_should_raise_thld_trig | ibi_should_raise_thld_trig | 0 | 0 | 0 | 1 | 0.0% |
| cmd_should_raise_thld_trig | cmd_should_raise_thld_trig | 0 | 0 | 0 | 1 | 0.0% |
| tx_should_raise_thld_trig | tx_should_raise_thld_trig | 0 | 0 | 0 | 1 | 0.0% |
| | TOTAL | | | 0 | 20 | 0.0% |