| clear_on_nonempty_resp_queue |
clear_on_nonempty_resp_queue |
0.03117 |
76.01000 |
2 |
2 |
100.00 % |
| clear_on_nonempty_cmd_queue |
clear_on_nonempty_cmd_queue |
0.06137 |
247.01000 |
2 |
2 |
100.00 % |
| clear_on_nonempty_rx_queue |
clear_on_nonempty_rx_queue |
0.02150 |
78.01000 |
2 |
2 |
100.00 % |
| clear_on_nonempty_tx_queue |
clear_on_nonempty_tx_queue |
0.03950 |
159.01000 |
2 |
2 |
100.00 % |
| clear_on_nonempty_ibi_queue |
clear_on_nonempty_ibi_queue |
0.02149 |
78.01000 |
2 |
2 |
100.00 % |
| cmd_capacity_status |
cmd_capacity_status |
0.01814 |
32.01000 |
2 |
2 |
100.00 % |
| resp_capacity_status |
resp_capacity_status |
0.00939 |
34.01000 |
2 |
2 |
100.00 % |
| rx_capacity_status |
rx_capacity_status |
0.00931 |
34.01000 |
2 |
2 |
100.00 % |
| tx_capacity_status |
tx_capacity_status |
0.00909 |
34.01000 |
2 |
2 |
100.00 % |
| ibi_capacity_status |
ibi_capacity_status |
0.00921 |
34.01000 |
2 |
2 |
100.00 % |
| cmd_setup_threshold |
cmd_setup_threshold |
0.02780 |
67.01000 |
2 |
2 |
100.00 % |
| resp_setup_threshold |
resp_setup_threshold |
0.02629 |
74.01000 |
2 |
2 |
100.00 % |
| rx_setup_threshold |
rx_setup_threshold |
0.02439 |
94.01000 |
2 |
2 |
100.00 % |
| tx_setup_threshold |
tx_setup_threshold |
0.02504 |
94.01000 |
2 |
2 |
100.00 % |
| ibi_setup_threshold |
ibi_setup_threshold |
0.02178 |
64.01000 |
2 |
2 |
100.00 % |
| resp_should_raise_thld_trig |
resp_should_raise_thld_trig |
0.03438 |
118.01000 |
2 |
2 |
100.00 % |
| rx_should_raise_thld_trig |
rx_should_raise_thld_trig |
0.07085 |
251.01000 |
2 |
2 |
100.00 % |
| ibi_should_raise_thld_trig |
ibi_should_raise_thld_trig |
0.02380 |
86.01000 |
2 |
2 |
100.00 % |
| cmd_should_raise_thld_trig |
cmd_should_raise_thld_trig |
0.19496 |
753.01000 |
2 |
2 |
100.00 % |
| tx_should_raise_thld_trig |
tx_should_raise_thld_trig |
0.32851 |
1342.01000 |
2 |
2 |
100.00 % |
|
TOTAL |
|
|
40 |
40 |
100.00 % |