| clear_on_nonempty_resp_queue |
clear_on_nonempty_resp_queue |
0.03071 |
76.01000 |
2 |
2 |
100.00 % |
| clear_on_nonempty_cmd_queue |
clear_on_nonempty_cmd_queue |
0.06099 |
247.01000 |
2 |
2 |
100.00 % |
| clear_on_nonempty_rx_queue |
clear_on_nonempty_rx_queue |
0.02139 |
78.01000 |
2 |
2 |
100.00 % |
| clear_on_nonempty_tx_queue |
clear_on_nonempty_tx_queue |
0.03932 |
159.01000 |
2 |
2 |
100.00 % |
| clear_on_nonempty_ibi_queue |
clear_on_nonempty_ibi_queue |
0.02140 |
78.01000 |
2 |
2 |
100.00 % |
| cmd_capacity_status |
cmd_capacity_status |
0.01839 |
32.01000 |
2 |
2 |
100.00 % |
| resp_capacity_status |
resp_capacity_status |
0.00937 |
34.01000 |
2 |
2 |
100.00 % |
| rx_capacity_status |
rx_capacity_status |
0.00911 |
34.01000 |
2 |
2 |
100.00 % |
| tx_capacity_status |
tx_capacity_status |
0.00902 |
34.01000 |
2 |
2 |
100.00 % |
| ibi_capacity_status |
ibi_capacity_status |
0.00915 |
34.01000 |
2 |
2 |
100.00 % |
| cmd_setup_threshold |
cmd_setup_threshold |
0.02713 |
67.01000 |
2 |
2 |
100.00 % |
| resp_setup_threshold |
resp_setup_threshold |
0.02337 |
74.01000 |
2 |
2 |
100.00 % |
| rx_setup_threshold |
rx_setup_threshold |
0.02372 |
94.01000 |
2 |
2 |
100.00 % |
| tx_setup_threshold |
tx_setup_threshold |
0.02429 |
94.01000 |
2 |
2 |
100.00 % |
| ibi_setup_threshold |
ibi_setup_threshold |
0.02190 |
64.01000 |
2 |
2 |
100.00 % |
| resp_should_raise_thld_trig |
resp_should_raise_thld_trig |
0.04561 |
159.01000 |
2 |
2 |
100.00 % |
| rx_should_raise_thld_trig |
rx_should_raise_thld_trig |
0.21884 |
883.01000 |
2 |
2 |
100.00 % |
| ibi_should_raise_thld_trig |
ibi_should_raise_thld_trig |
0.03984 |
135.01000 |
2 |
2 |
100.00 % |
| cmd_should_raise_thld_trig |
cmd_should_raise_thld_trig |
0.20048 |
823.01000 |
2 |
2 |
100.00 % |
| tx_should_raise_thld_trig |
tx_should_raise_thld_trig |
0.29050 |
1198.01000 |
2 |
2 |
100.00 % |
|
TOTAL |
|
|
40 |
40 |
100.00 % |