| clear_on_nonempty_resp_queue | clear_on_nonempty_resp_queue | 0.021 | 88.000 | 1 | 1 | 100% |
| clear_on_nonempty_cmd_queue | clear_on_nonempty_cmd_queue | 0.050 | 302.000 | 1 | 1 | 100% |
| clear_on_nonempty_rx_queue | clear_on_nonempty_rx_queue | 0.020 | 90.000 | 1 | 1 | 100% |
| clear_on_nonempty_tx_queue | clear_on_nonempty_tx_queue | 0.034 | 192.000 | 1 | 1 | 100% |
| clear_on_nonempty_ibi_queue | clear_on_nonempty_ibi_queue | 0.020 | 90.000 | 1 | 1 | 100% |
| cmd_capacity_status | cmd_capacity_status | 0.013 | 42.000 | 1 | 1 | 100% |
| resp_capacity_status | resp_capacity_status | 0.010 | 44.000 | 1 | 1 | 100% |
| rx_capacity_status | rx_capacity_status | 0.010 | 44.000 | 1 | 1 | 100% |
| tx_capacity_status | tx_capacity_status | 0.010 | 44.000 | 1 | 1 | 100% |
| ibi_capacity_status | ibi_capacity_status | 0.010 | 44.000 | 1 | 1 | 100% |
| cmd_setup_threshold | cmd_setup_threshold | 0.020 | 82.000 | 1 | 1 | 100% |
| resp_setup_threshold | resp_setup_threshold | 0.017 | 90.000 | 1 | 1 | 100% |
| rx_setup_threshold | rx_setup_threshold | 0.019 | 112.000 | 1 | 1 | 100% |
| tx_setup_threshold | tx_setup_threshold | 0.019 | 112.000 | 1 | 1 | 100% |
| ibi_setup_threshold | ibi_setup_threshold | 0.014 | 78.000 | 1 | 1 | 100% |
| resp_should_raise_thld_trig | resp_should_raise_thld_trig | 0.023 | 128.000 | 1 | 1 | 100% |
| rx_should_raise_thld_trig | rx_should_raise_thld_trig | 0.154 | 1056.000 | 1 | 1 | 100% |
| ibi_should_raise_thld_trig | ibi_should_raise_thld_trig | 0.026 | 142.000 | 1 | 1 | 100% |
| cmd_should_raise_thld_trig | cmd_should_raise_thld_trig | 0.177 | 1206.000 | 1 | 1 | 100% |
| tx_should_raise_thld_trig | tx_should_raise_thld_trig | 0.107 | 642.000 | 1 | 1 | 100% |
| | TOTAL | | | 20 | 20 | 100% |