| Test CSR accesses | dat_csr_access | 0 | 0 | 0 | 1 | 0.0% |
| | dct_csr_access | 0 | 0 | 0 | 1 | 0.0% |
| | base_csr_access | 0 | 0 | 0 | 1 | 0.0% |
| | pio_csr_access | 0 | 0 | 0 | 1 | 0.0% |
| | ec_sec_fw_rec_csr_access | 1.103 | 6863.357 | 1 | 1 | 100% |
| | ec_stdby_ctrl_mode_csr_access | 0.436 | 2951.949 | 1 | 1 | 100% |
| | ec_tti_csr_access | 1.411 | 9072.063 | 1 | 1 | 100% |
| | ec_soc_mgmt_csr_access | 1.617 | 9836.327 | 1 | 1 | 100% |
| | ec_contrl_config_csr_access | 0.101 | 644.144 | 1 | 1 | 100% |
| | ec_csr_access | 0.051 | 373.874 | 1 | 1 | 100% |
| AXI burst read | basic_burst_read | 1.780 | 17309.292 | 1 | 1 | 100% |
| AXI burst write | basic_burst_write | 14.661 | 125005.881 | 1 | 1 | 100% |
| AXI stall accesses | write_stall | 0.086 | 749.249 | 1 | 1 | 100% |
| | read_stall | 0.044 | 483.483 | 1 | 1 | 100% |
| | write_b_channel_skid_full | 0.027 | 240.240 | 1 | 1 | 100% |
| | read_r_channel_skid_full | 0.014 | 123.123 | 1 | 1 | 100% |
| Standby Controller CSR Hardware Lock | ec_stdby_csr_hw_lock | | | 0 | 0 | --% |
| | TOTAL | | | 12 | 16 | 75.0% |