| Test CSR accesses | dat_csr_access | 0 | 0 | 0 | 1 | 0.0% |
| | dct_csr_access | 0 | 0 | 0 | 1 | 0.0% |
| | base_csr_access | 0 | 0 | 0 | 1 | 0.0% |
| | pio_csr_access | 0 | 0 | 0 | 1 | 0.0% |
| | ec_sec_fw_rec_csr_access | 0.818 | 6863.357 | 1 | 1 | 100% |
| | ec_stdby_ctrl_mode_csr_access | 0.388 | 2951.949 | 1 | 1 | 100% |
| | ec_tti_csr_access | 1.170 | 9072.063 | 1 | 1 | 100% |
| | ec_soc_mgmt_csr_access | 1.231 | 9836.327 | 1 | 1 | 100% |
| | ec_contrl_config_csr_access | 0.072 | 644.144 | 1 | 1 | 100% |
| | ec_csr_access | 0.040 | 373.874 | 1 | 1 | 100% |
| AXI burst read | basic_burst_read | 1.277 | 17309.292 | 1 | 1 | 100% |
| AXI burst write | basic_burst_write | 12.170 | 131492.361 | 1 | 1 | 100% |
| AXI stall accesses | write_stall | 0.061 | 626.126 | 1 | 1 | 100% |
| | read_stall | 0.034 | 477.477 | 1 | 1 | 100% |
| | write_b_channel_skid_full | 0.021 | 240.240 | 1 | 1 | 100% |
| | read_r_channel_skid_full | 0.011 | 123.123 | 1 | 1 | 100% |
| Standby Controller CSR Hardware Lock | ec_stdby_csr_hw_lock | | | 0 | 0 | --% |
| | TOTAL | | | 12 | 16 | 75.0% |