Design verification¶
This chapter presents the available models and tools which are used for I3C verification. The core is verified with the Cocotb + unit tests and the UVM test suite.
There are also non-public tests which utilize Avery I3C VIP framework. The tests include: private_read, private_write and recovery and verify operation of target mode private reads and writes and the secure firmware recovery flow respectively.
This section contains testplans for the verification.
Definitions:
testplan- an organized collection of testpointstestpoint- an actionable item, which can be turned into a test:name- typically related to the tested featuredesc- detailed description; should contain description of the feature, configuration mode, stimuli, expected behavior.stage- can be used to assign testpoints to milestones.tests- names of implemented tests, which cover the testpoint. Relation test-testpoint can be many to many.tags- additional tags that can be used to group testpoints
Full overview of tests can be found in Testplan summary.
Testplans for individual blocks¶
bus_monitor¶
Testpoints¶
bus_monitor¶
Test: bus_monitor
Tests operation of the bus_monitor module along with its sub-modules. Performs a number of I3C transactions between a simulated controller and a simulated target. Counts start, repeated start and stop events reported by bus_monitor. Verifies that the counts match what’s expected.
bus_rx_flow¶
Testpoints¶
multiple_bit_reads¶
Test: multiple_bit_reads
Drives SCL line with a steady clock, issues multiple bit read requests, verifies that the module returns correct data sampled from the SDA line.
multiple_byte_reads¶
Test: multiple_byte_reads
Drives SCL line with a steady clock, issues multiple byte read requests, verifies that the module returns correct data sampled from the SDA line.
bus_timers¶
Testpoints¶
get_status¶
Test: bus_timers
Tests the bus_timers module responsible for tracking bus free, idle and available states. Triggers the module and verifies if the signals corresponding to bus states get asserted after the required time period.
bus_tx¶
Testpoints¶
bit_tx_negedge¶
Test: bit_tx_negedge
Requests the bus_tx module to drive SDA right after SCL falling edge. Checks if the requested bit value is driven correctly
bit_tx_pre_posedge¶
Test: bit_tx_pre_posedge
Requests the bus_tx module to drive SDA just before SCL rising edge. Checks if the requested bit value is driven correctly
bit_tx_high_level¶
Test: bit_tx_high_level
Requests the bus_tx module to drive SDA just before SCL falling edge. Checks if the requested bit value is driven correctly
bit_tx_low_level¶
Test: bit_tx_low_level
Requests the bus_tx module to drive SDA when SCL in in stable low state. Checks if the requested bit value is driven correctly
byte_tx¶
Test: byte_tx
Drives controls of the bus_tx module in a sequence which sends a data byte plus T bit to the I3C bus. For each bit sent checks if SDA is driven correctly and bus timings are met.
bus_tx_flow¶
Testpoints¶
bit_tx_negedge¶
Test: bit_tx_negedge
Requests the bus_tx_flow module to drive SDA right after SCL falling edge. Checks if the requested bit value is driven correctly
bit_tx_pre_posedge¶
Test: bit_tx_pre_posedge
Requests the bus_tx_flow module to drive SDA just before SCL rising edge. Checks if the requested bit value is driven correctly
bit_tx_high_level¶
Test: bit_tx_high_level
Requests the bus_tx_flow module to drive SDA just before SCL falling edge. Checks if the requested bit value is driven correctly
bit_tx_low_level¶
Test: bit_tx_low_level
Requests the bus_tx_flow module to drive SDA when SCL in in stable low state. Checks if the requested bit value is driven correctly
byte_tx¶
Test: byte_tx
Requests the bus_tx_flow module to transmitt a data byte along with T-bit. While the transmission is in progress samples SDA on rising edges of SCL. Once the transmission finishes compares sampled data with what was requested to be sent.
ccc¶
Testpoints¶
ccc¶
Test: ccc
Instucts the ccc module to begin servicing GETSTATUS CCC. Feeds data bytes and bits to the module via its bus_tx/bus_rx interfaces to mimick actual I3C transaction. Checks if data bytes received correspond to correct GETSTATUS CCC response.
csr_sw_access¶
Testpoints¶
read_hci_version_csr¶
Test: read_hci_version_csr
Reads the HCI version CSR and verifies its content
read_pio_section_offset¶
Test: read_pio_section_offset
Reads the PIO_SECTION_OFFSET CSR and verifies its content
write_to_controller_device_addr¶
Test: write_to_controller_device_addr
Writes to the CONTROLLER_DEVICE_ADDR CSR and verifies if the write was successful
write_should_not_affect_ro_csr¶
Test: write_should_not_affect_ro_csr
Writes to the HC_CAPABILITIES CSR which is read-only for software Verifies that the write did not succeed.
sequence_csr_read¶
Test: sequence_csr_read
Performs a sequence of CSR reads. Verifies that each one succeeds
sequence_csr_write¶
Test: sequence_csr_write
Performs a sequence of CSR writes. Verifies that each one succeeds
descriptor_rx¶
Testpoints¶
descriptor_rx¶
Test: descriptor_rx
Tests the descriptor_rx module responsible for generating TTI RX descriptors. The test sends N bytes to the module and verifies that it emits a valid descriptor with data length set to N.
descriptor_tx¶
Testpoints¶
descriptor_tx¶
Test: descriptor_tx
Tests the descriptor_tx module responsible for processing TTI TX descriptors and controlling TTI data flow during I3C private reads. Sends a descriptor to the module followed with the right amount of data. Verifies that the module accepted the descriptor and allowed the right amount of data bytes to pass through it.
drivers¶
Testpoints¶
test_drivers¶
Test: drivers
Tests the I3C PHY module. Loops through all possible states of SDA/SCL for OD and PP mode. Checks if driven data matches the bus state.
edge_detector¶
Testpoints¶
pretrigger_with_delay¶
Test: pretrigger_with_delay
Triggers the edge_detector module before an edge on a bus line, emits the edge and counts clock cycles it takes the detector to report the presence of the edge. Verifies that the count is equal to the programmed delay.
posttrigger_with_delay¶
Test: posttrigger_with_delay
Emits an edge on the bus, triggers the edge_detector module after the edge when the bus line is high. Counts clock cycles it takes the detector to report the edge event. The output detect signal is asserted only if the bus line signal is stable for the programmed delay time since the assertion of the trigger signal. Verifies that the number of counted cycles is equal the programmed delay.
trigger_with_delay¶
Test: trigger_with_delay
Triggers the edge detector and emits a rising edge on a bus line simultaneously. Counts clock cycles it takes the detector to report the presence of the edge. Verifies that the count is equal to the programmed delay.
pretrigger_no_delay¶
Test: pretrigger_no_delay
Triggers the edge_detector module before an edge on a bus line, emits the edge and counts clock cycles it takes the detector to report the presence of the edge. Verifies that the count is zero as the configured delay is also set to 0.
posttrigger_no_delay¶
Test: posttrigger_no_delay
Triggers the edge_detector module when a bus line is high which is after an edge. Counts clock cycles it takes the detector to report the presence of the edge. Verifies that the count is zero as the configured delay is also set to 0.
trigger_no_delay¶
Test: trigger_no_delay
Triggers the edge detector and emits a rising edge on a bus line simultaneously. Counts clock cycles it takes the detector to report the presence of the edge. Verifies that the count is zero as the configured delay is also set to 0.
flow_standby_i3c¶
Testpoints¶
rx¶
Test: rx
Tests basic operation of the flow_standby_i3c module. The test instantiates two tasks serving as BFMs for RX and TX queues. Then it simulates bus start condition followed by data reception ended by bus stop condition.
hci_queues¶
Testpoints¶
clear_on_nonempty_resp_queue¶
Test: clear_on_nonempty_resp_queue
Writes to the HCI queue RESET_CONTROL CSR bit which causes HCI command response queue to be cleared. Then, polls the CSR until the bit gets cleared by the hardware. To check if the queue has been cleared puts a descriptor to the queue and reads it back. It should be the same descriptor.
clear_on_nonempty_cmd_queue¶
Test: clear_on_nonempty_cmd_queue
Puts a command descriptor to the HCI command queue. Writes to the RESET_CONTROL CSR to the bit responsible for clearing the queue, polls the CSR until the bit gets cleared by hardware. Verifies that the queue got cleared by pushing and retrieving another descriptor from the queue.
clear_on_nonempty_rx_queue¶
Test: clear_on_nonempty_rx_queue
Puts 10 data words to the HCI RX data queue. Writes to the RESET_CONTROL CSR to the bit responsible for clearing the queue, polls the CSR until the bit gets cleared by hardware. Puts and gets another data word from the queue to check if it was cleared
clear_on_nonempty_tx_queue¶
Test: clear_on_nonempty_tx_queue
Puts 10 data words to the HCI TX data queue. Writes to the RESET_CONTROL CSR to the bit responsible for clearing the queue, polls the CSR until the bit gets cleared by hardware. Puts and gets another data word from the queue to check if it was cleared
clear_on_nonempty_ibi_queue¶
Test: clear_on_nonempty_ibi_queue
Puts 10 data words to the HCI IBI queue. Writes to the RESET_CONTROL CSR to the bit responsible for clearing the queue, polls the CSR until the bit gets cleared by hardware. Puts and gets another data word from the queue to check if it was cleared
cmd_capacity_status¶
Test: cmd_capacity_status
Resets the HCI command queue and verifies that it is empty afterwards
resp_capacity_status¶
Test: resp_capacity_status
Resets the HCI response queue and verifies that it is empty afterwards
rx_capacity_status¶
Test: rx_capacity_status
Resets the HCI RX queue and verifies that it is empty afterwards
tx_capacity_status¶
Test: tx_capacity_status
Resets the HCI TX queue and verifies that it is empty afterwards
ibi_capacity_status¶
Test: ibi_capacity_status
Resets the HCI IBI queue and verifies that it is empty afterwards
cmd_setup_threshold¶
Test: cmd_setup_threshold
Writes the threshold to appropriate register for the HCI command queue (QUEUE_THLD_CTRL or DATA_BUFFER_THLD_CTRL). Verifies that an appropriate value has been written to the CSR. Verifies the threshold signal assumes the correct value.
resp_setup_threshold¶
Test: resp_setup_threshold
Writes the threshold to appropriate register for the HCI response queue (QUEUE_THLD_CTRL or DATA_BUFFER_THLD_CTRL). Verifies that an appropriate value has been written to the CSR. Verifies the threshold signal assumes the correct value.
rx_setup_threshold¶
Test: rx_setup_threshold
Writes the threshold to appropriate register for the HCI data RX queue (QUEUE_THLD_CTRL or DATA_BUFFER_THLD_CTRL). Verifies that an appropriate value has been written to the CSR. Verifies the threshold signal assumes the correct value.
tx_setup_threshold¶
Test: tx_setup_threshold
Writes the threshold to appropriate register for the HCI data TX queue (QUEUE_THLD_CTRL or DATA_BUFFER_THLD_CTRL). Verifies that an appropriate value has been written to the CSR. Verifies the threshold signal assumes the correct value.
ibi_setup_threshold¶
Test: ibi_setup_threshold
Writes the threshold to appropriate register for the HCI IBI queue (QUEUE_THLD_CTRL or DATA_BUFFER_THLD_CTRL). Verifies that an appropriate value has been written to the CSR. Verifies the threshold signal assumes the correct value.
resp_should_raise_thld_trig¶
Test: resp_should_raise_thld_trig
Sets up a ready threshold of the read queue and checks whether the trigger signal is properly asserted at different levels of the queue fill.
rx_should_raise_thld_trig¶
Test: rx_should_raise_thld_trig
Sets up a ready and start thresholds of the read queue and checks whether the trigger signals are properly asserted at different levels of the queue fill.
ibi_should_raise_thld_trig¶
Test: ibi_should_raise_thld_trig
Sets up a ready threshold of the read queue and checks whether the trigger signal is properly asserted at different levels of the queue fill.
cmd_should_raise_thld_trig¶
Test: cmd_should_raise_thld_trig
Sets up a ready threshold of the write queue and checks whether the trigger is properly asserted at different levels of the queue fill.
tx_should_raise_thld_trig¶
Test: tx_should_raise_thld_trig
Sets up a ready and start threshold of the write queue and checks whether the trigger is properly asserted at different levels of the queue fill.
i3c_bus_monitor¶
Testpoints¶
bus_monitor_hdr_exit¶
Test: bus_monitor_hdr_exit
Verifies that the i3c_bus_monitor module correctly detects HDR exit pattern. Sends the HDR exit pattern and verifies that the module does not react - initially the bus is in SDR mode. Instructs the module that the bus has entered HDR mode, issues the HDR exit pattern and counts the number of times the module reported HDR exit. Checks if it reported exactly one HDR exit event.
target_reset_detection¶
Test: target_reset_detection
Issues a target reset patterin to the I3C bus, verifies that the i3c_bus_monitor correctly report it detected.
pec¶
Testpoints¶
pec¶
Test: pec
Pushes random bytes through the recovery_pec module, compares its computed checksum with its correspondent computed in software.
tti_queues¶
Testpoints¶
tti_tx_capacity_status¶
Test: tti_tx_capacity_status
Resets the TTI TX queue and verifies that it is empty afterwards
tti_tx_desc_capacity_status¶
Test: tti_tx_desc_capacity_status
Resets the TTI TX descriptor queue and verifies that it is empty afterwards
tti_rx_capacity_status¶
Test: tti_rx_capacity_status
Resets the TTI RX queue and verifies that it is empty afterwards
tti_rx_desc_capacity_status¶
Test: tti_rx_desc_capacity_status
Resets the TTI RX descriptor queue and verifies that it is empty afterwards
tti_tx_setup_threshold¶
Test: tti_tx_setup_threshold
Writes the threshold to appropriate register for the TTI data TX queue (QUEUE_THLD_CTRL or DATA_BUFFER_THLD_CTRL). Verifies that an appropriate value has been written to the CSR. Verifies the threshold signal assumes the correct value.
tti_tx_desc_setup_threshold¶
Test: tti_tx_desc_setup_threshold
Writes the threshold to appropriate register for the TTI descriptor TX queue (QUEUE_THLD_CTRL or DATA_BUFFER_THLD_CTRL). Verifies that an appropriate value has been written to the CSR. Verifies the threshold signal assumes the correct value.
tti_rx_setup_threshold¶
Test: tti_rx_setup_threshold
Writes the threshold to appropriate register for the TTI data RX queue (QUEUE_THLD_CTRL or DATA_BUFFER_THLD_CTRL). Verifies that an appropriate value has been written to the CSR. Verifies the threshold signal assumes the correct value.
tti_rx_desc_setup_threshold¶
Test: tti_rx_desc_setup_threshold
Writes the threshold to appropriate register for the TTI descriptor RX queue (QUEUE_THLD_CTRL or DATA_BUFFER_THLD_CTRL). Verifies that an appropriate value has been written to the CSR. Verifies the threshold signal assumes the correct value.
tti_ibi_setup_threshold¶
Test: tti_ibi_setup_threshold
Writes the threshold to appropriate register for the TTI IBI queue (QUEUE_THLD_CTRL or DATA_BUFFER_THLD_CTRL). Verifies that an appropriate value has been written to the CSR. Verifies the threshold signal assumes the correct value.
tti_ibi_should_raise_thld_trig¶
Test: tti_ibi_should_raise_thld_trig
Sets up a ready threshold of the TTI queue and checks whether the trigger signal is properly asserted at different levels of the queue fill.
tti_rx_desc_should_raise_thld_trig¶
Test: tti_rx_desc_should_raise_thld_trig
Sets up a ready threshold of the read queue and checks whether the trigger signal is properly asserted at different levels of the queue fill.
rx_should_raise_thld_trig¶
Test: rx_should_raise_thld_trig
Sets up a ready and start thresholds of the read queue and checks whether the trigger signals are properly asserted at different levels of the queue fill.
tx_desc_should_raise_thld_trig¶
Test: tti_tx_desc_should_raise_thld_trig
Sets up a ready and start threshold of the write queue and checks whether the trigger is properly asserted at different levels of the queue fill.
tx_should_raise_thld_trig¶
Test: tx_should_raise_thld_trig
Sets up a ready and start threshold of the write queue and checks whether the trigger is properly asserted at different levels of the queue fill.
ibi_should_raise_thld_trig¶
Test: ibi_should_raise_thld_trig
Sets up a ready and start threshold of the write queue and checks whether the trigger is properly asserted at different levels of the queue fill.
tti_ibi_capacity_status¶
Test: tti_ibi_capacity_status
Resets the TTI TX IBI queue and verifies that it is empty afterwards
width_converter_8toN¶
Testpoints¶
converter¶
Test: width_converter_8ton_converter
Pushes random byte stream to the converter module. After each byte waits at random. Simultaneously receives N-bit data words and generates pushback (deasserts ready) at random. Verifies if the output data matches the input.
flush¶
Test: width_converter_8ton_flush
Feeds M bytes to the module where M is in [1, 2, 3]. Asserts the sink_flush_i signal, receives the output word and checks if it matches the input data.
width_converter_Nto8¶
Testpoints¶
converter¶
Test: width_converter_nto8_converter
Pushes random N-bit word stream to the converter module. After each word waits at random. Simultaneously receives bytes and generates pushback (deasserts ready) at random. Verifies if the output data matches the input.
flush¶
Test: width_converter_nto8_flush
Feeds an N-bit word to the module. Receives M bytes where M is in [1, 2, 3] and asserts source_flush_i. Verifies that the module ceases to output data as expected.
Testplans for the core¶
Target¶
Testpoints¶
i3c_target_write¶
Test: i3c_target_write
Spawns a TTI agent that reads from TTI descriptor and data queues and stores received data.
While the agent is running the test issues several private writes over I3C. Data sent over I3C is compared with data received by the agent.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
i3c_target_read¶
Test: i3c_target_read
Writes a data chunk and its descriptor to TTI TX queues, issues an I3C private read transfer. Verifies that the data matches. Repeats the two steps N times.
Writes N data chunks and their descriptors to TTI TX queues, issues N private read transfers over I3C. For each one verifies that data matches.
Writes a data chunk and its descriptor to TTI TX queues, issues an I3C private read transfer which is shorter than the length of the chunk. Verifies that the received data matches with the chunk. Repeats the steps N times.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
i3c_target_ibi¶
Test: i3c_target_ibi
Writes an IBI descriptor to the TTI IBI queue. Waits until the controller services the IBI. Checks if the mandatory byte (MDB) matches on both sides.
Reads the LAST_IBI_STATUS fiels of the TTI STATUS CSR. Ensures that it is equal to 0 (no error).
Writes an IBI descriptor followed by N bytes of data to the TTI IBI queue. Waits until the controller services the IBI. Checks if the mandatory byte (MDB) and data matches on both sides.
Repeats the LAST_IBI_STATUS check
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
i3c_target_ibi_retry¶
Test: i3c_target_ibi_retry
Disables ACK-ing IBIs in the I3C controller model, issues an ibi from the target by writing to TTI IBI queue. Waits for a fixed time period - sufficiently long for the target to retry sending the IBI, reads LAST_IBI_STATUS from the TTI STATUS CSR, check if it is set to 3 (IBI retry).
Re-enables ACK-ing of IBIs in the controller model, waits for the model to service the IBI, compares the IBI mandatory byte (MDB) with the one written to the TTI queue. Reads LAST_IBI_STATUS from the TTI STATUS CSR, check if it is set to 0 (no error).
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
i3c_target_ibi_data¶
Test: i3c_target_ibi_data
Sets a limit on how many IBI data bytes may be accepted in the controller model. Issues an IBI with more data bytes by writing to the TTI IBI queue, checks if the IBI gets serivced correctly, compares data.
Issues another IBI with data payload within the set limit, checks if it gets serviced correctly, compares data.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
i3c_target_writes_and_reads¶
Test: i3c_target_writes_and_reads
Writes a randomized data chunk to the TTI TX data queue, writes a corresponding descriptor to the TTI TX descriptor queue.
Issues private write transfers to the target with randomized payloads, waits until a TTI interrupt is set by polling TTI INTERRUPT_STATUS CSR. Reads received data from TTI RX queues, compares it with what has been sent.
Does a private read transfer, compares if the received data equals the data written to TTI TX queue in the beginning of the test.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
CCC handling¶
Testpoints¶
ccc_getstatus¶
Test: ccc_getstatus
The test reads PENDING_INTERRUPT field from the TTI INTERRUPT status CSR. Next, it issues the GETSTATUS directed CCC to the target. Finally it compares the interrupt status returned by the CCC with the one read from the register.
ccc_setdasa¶
Test: ccc_setdasa
The test sets dynamic address and virtual dynamic address by sending SETDASA CCC. Then it verifies that correct addresses have been set by reading STBY_CR_DEVICE_ADDR CSR.
ccc_rstdaa¶
Test: ccc_rstdaa
Sets dynamic address via STBY_CR_DEVICE_ADDR CSR, then sends RSTDAA CCC and verifies that the address got cleared.
ccc_getbcr¶
Test: ccc_getbcr
Reads BCR register content by sending GETBCR CCC and examining returned data.
ccc_getdcr¶
Test: ccc_getdcr
Reads DCR register content by sending GETDCR CCC and examining returned data.
ccc_getmwl¶
Test: ccc_getmwl
Reads MWL register content by sending GETMWL CCC and examining returned data.
ccc_getmrl¶
Test: ccc_getmrl
Reads MRL register content by sending GETMWL CCC and examining returned data.
ccc_setaasa¶
Test: ccc_setaasa
Issues the broadcast SETAASA CCC and checks if the target uses its static address as dynamic by examining STBY_CR_DEVICE_ADDR CSR.
ccc_getpid¶
Test: ccc_getpid
Sends the CCC to the target and examines if the returned PID matches the expected.
ccc_enec_disec_direct¶
Test: ccc_enec_disec_direct
Sends DISEC CCC to the target and verifies that events are disabled. Then, sends ENEC CCC to the target and checks that events are enabled.
ccc_enec_disec_bcast¶
Test: ccc_enec_disec_bcast
Sends boradcast DISEC CCC and verifies that events are disabled. Then, sends broadcast ENEC CCC and checks that events are enabled.
ccc_setmwl_direct¶
Test: ccc_setmwl_direct
Sends directed SETMWL CCC to the target and verifies that the register got correctly set. The check is performed by examining relevant wires in the target DUT
ccc_setmrl_direct¶
Test: ccc_setmrl_direct
Sends directed SETMRL CCC to the target and verifies that the register got correctly set. The check is performed by examining relevant wires in the target DUT
ccc_setmwl_bcast¶
Test: ccc_setmwl_bcast
Sends broadcast SETMWL CCC and verifies that the register got correctly set. The check is performed by examining relevant wires in the target DUT
ccc_setmrl_bcast¶
Test: ccc_setmrl_bcast
Sends SETMRL CCC and verifies that the register got correctly set. The check is performed by examining relevant wires in the target DUT
ccc_rstact_direct¶
Test: ccc_rstact_direct
Sends directed RSTACT CCC to the target followed by reset pattern and checks if reset action was stored correctly. The check is done by examining DUT wires. Then, triggers target reset and verifies that the peripheral_reset_o signal gets asserted.
ccc_rstact_bcast¶
Test: ccc_rstact_bcast
Sends directed RSTACT CCC to the target followed by reset pattern and checks if reset action was stored correctly. The check is done by examining DUT wires. Then, triggers target reset and verifies that the escalated_reset_o signal gets asserted.
ccc_direct_multiple_wr¶
Test: ccc_direct_multiple_wr
Sends a sequence of multiple directed SETMWL CCCs. The first and the last have non-matching address. The two middle ones set MWL to different values. Verify that the target responded to correct addresses and executed both CCCs.
ccc_direct_multiple_rd¶
Test: ccc_direct_multiple_rd
Sends SETMWL CCC. Then sends multiple directed GETMWL CCCs to thee different addresses. Only the one for the target should be ACK-ed with the correct MWL content.
Enter and exit HDR mode¶
Testpoints¶
Enter and exit HDR mode¶
Test: enter_exit_hdr_mode
Issues ENTHDR0 CCC to the target, verifies that the target FSM is in IdleHDR state. Issues HDR exit pattern, verifies that the target FSM is back in Idle state.
target_interrupts¶
Testpoints¶
rx_desc_stat¶
Test: rx_desc_stat
Enables RX_DESC_STAT TTI interrupt, checks if the irq_o signal is deasserted, sends a private write over I3C to the target and waits for irq_o assertion. Once the interrupt is asserted reads a RX descriptor from the TTI RX descriptor queue, ensures that irq_o gets deasserted after the read.
tx_desc_stat¶
Test: tx_desc_stat
Enables TX_DESC_STAT TTI interrupt, checks if the irq_o signal is deasserted, writes data to TTI TX data queue followed by writing a descriptor to TTI TX descriptor queue, sends a private read over I3C and waits for irq_o assertion. Once the interrupt is asserted clears it by writing 1 to the TX_DESC_STAT fiels of TTI INTERRUPT_STATUS csr and ensures that irq_o signal gets deasserted.
ibi_done¶
Test: ibi_done
Enables IBI_DONE_EN TTI interrupt, checks if the irq_o signal is deasserted, and the status bit in TTI INTERRUPT_STATUS CSR cleared. Issues and IBI, waits for it to be serviced by the controller. Checks if the status bit is set in INTERRUPT_STATUS CSR and the irq_o signal asserted. Reads LAST_IBI_STATUS field from the TTI STATUS CSR, ensures that irq_o gets deasserted and status bit gets cleared afterwards.
interrupt_force¶
Test: interrupt_force
The test is run for each TTI interrupt:
TX_DESC_STAT_EN
RX_DESC_STAT_EN
RX_DESC_THLD_STAT_EN
RX_DATA_THLD_STAT_EN
IBI_DONE_EN
Ensures that irq_o is deasserted. Disables the interrupt in TTI INTERRUPT_ENABLE CSR, forces the interrupt by writing 1 to the corresponding field in TTI INTERRUPT_FORCE CSR, ensures that the irq_o does not get asserted.
Enables the interrupt in TTI INTERRUPT_ENABLE CSR, forces the interrupt by writing 1 to the corresponding field in TTI INTERRUPT_FORCE CSR, ensures that the irq_o does get asserted.
Clears the interrupt by writing 1 to its corresponding field in TTI INTERRUPT_STATUS CSR, ensures that irq_o gets deasserted and the status bit cleared.
Recovery mode tests¶
Testpoints¶
virtual_write¶
Test: virtual_write
Tests CSR write(s) through recovery protocol using the virtual target address. In the beginning sets the TTI and recovery addresses via two SETDASA CCCs.
Performs a write to DEVICE_RESET register via the recovery protocol targeting the virtual address. Reads the CSR content back through AHB/AXI, checks if the transfer was successful and the content read back matches. Then reads again the DEVICE_RESET register, this time via the recovery protocol. Check if the content matches.
Reads PENDING_INTERRUPT field from INTERRUPT_STATUS CSR via the GET_STATUS CCC command issued to the TTI I3C address. Verifies that the content read back matches what is set in the CSR.
Writes to the INDIRECT_FIFO_CTRL register using recovery protocol, reads content of the register via AHB/AXI and verifies that their content matches.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
virtual_write_alternating¶
Test: virtual_write_alternating
Sets the TTI and recovery addresses via two SETDASA CCCs.
Writes to DEVICE_RESET via recovery protocol targeting the virtual device address. Reads the register content through AHB/AXI and check if it matches with what has been written.
Sends a private write transfer to the TTI address. Reads the data back from TTI TX data queue and check that it matches.
Disables the recovery mode by writing 0x2 to DEVICE_STATUS register and repeats the previous steps to test whether the I3C core responds both to TTI and virtual addresses.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
write¶
Test: write
Sets the TTI and recovery addresses via two SETDASA CCCs.
Performs a write to DEVICE_RESET register via the recovery protocol targeting the virtual address. Reads the CSR content back through AHB/AXI, checks if the transfer was successful and the content read back matches. Then reads again the DEVICE_RESET register, this time via the recovery protocol. Check if the content matches.
Writes to the INDIRECT_FIFO_CTRL register using recovery protocol, reads content of the register via AHB/AXI and verifies that their content matches.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
indirect_fifo_write¶
Test: indirect_fifo_write
Sets the TTI and recovery addresses via two SETDASA CCCs.
Retrieves indirect FIFO status and pointers by reading INDIRECT_FIFO_STATUS CSR over AHB/AXI bus. Writes data to the indirect FIFO through the recovery interface and retrieves status and pointers again. Reads the data from the FIFO back through AHB/AXI bus, retrieves FIFO pointers. Lastly clears the indirect FIFO by writing to INDIRECT_FIFO_CTRL through the recovery interface and obtains the pointers again.
After each FIFO status and pointer retrieval checks if both match the expected behavior.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
write_pec¶
Test: write_pec
Sets the TTI and recovery addresses via two SETDASA CCCs.
Writes some data to DEVICE_RESET register using the recovery interface. Then, repeats the write with different data but deliberately corrupts the recovery packet’s checksum (PEC). Finally, reads the content of DEVICE_RESET CSR over AHB/AXI and ensures that it matches with what was written in the first transfer.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
read¶
Test: read
Sets the TTI and recovery addresses via two SETDASA CCCs.
Writes random data to the PROT_CAP recovery CSR via AHB/AXI. Disables the recovery mode, writes some data to TTI TX queues via AHB/AXI, enables the recovery mode and reads PROT_CAP using the recovery protocol. Checks if the content matches what was written in the beginning of the test.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
read_short¶
Test: read_short
Sets the TTI and recovery addresses via two SETDASA CCCs.
Writes random data to the PROT_CAP recovery CSR via AHB/AXI. Disables the recovery mode, writes some data to TTI TX queues via AHB/AXI, enables the recovery mode and reads PROT_CAP using the recovery protocol. The I3C read transfer is deliberately shorter - the recovery read is terminated by the I3C controller. Checks if the content read back matches what was written in the beginning of the test.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
read_long¶
Test: read_long
Sets the TTI and recovery addresses via two SETDASA CCCs.
Writes random data to the PROT_CAP recovery CSR via AHB/AXI. Disables the recovery mode, writes some data to TTI TX queues via AHB/AXI, enables the recovery mode and reads PROT_CAP using the recovery protocol. The I3C read transfer is deliberately longer - the recovery read is terminated by the I3C target. Checks if the content read back matches what was written in the beginning of the test.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
virtual_read¶
Test: virtual_read
Sets the TTI and recovery addresses via two SETDASA CCCs. Disables the recovery mode.
Issues a series of recovery read commands to all CSRs mentioned in the spec. The series is repeated twice - for recovery mode enabled and disabled. Each transfer is checked if the response is ACK or NACK and in case of ACK if PEC checksum is correct.
Checks if CSRs that sould be available anytime (i.e. when the recovery mode is off) are always accessible, checks if other CSRs are accessible only in the recovery mode.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
virtual_read_alternating¶
Test: virtual_read_alternating
Alternates between recovery mode reads and TTI reads. Initially sets the TTI and recovery addresses via two SETDASA CCCs.
Writes random data to the PROT_CAP register over AHB/AXI, reads the register through the recovery protocol and check if the content matches.
Writes data and its descriptor to TTI TX queues, issues a private I3C read, verifies that the data read back matches.
Disables the recovery mode and repeats the recovery and TTI reads to ensure that both TTI and recovery transfers are possible regardless of the recovery mode setting.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
payload_available¶
Test: payload_available
Sets the TTI and recovery addresses via two SETDASA CCCs.
Ensures that initially the recovery_payload_available_o signal is deasserted. Then writes data to the indirect FIFO via the recovery interface and checks if the signal gets asserted.
Reads from INDIRECT_FIFO_DATA CSR over AHB/AXI and checks if the read causes the signal to be deasserted again.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
image_activated¶
Test: image_activated
Sets the TTI and recovery addresses via two SETDASA CCCs.
Ensures that initially the image_activated_o signal is deasserted. Writes 0xF to the 3rd byte of the RECOVERY_CTRL register using the recovery interface. Checks if the signal gets asserted. Then writes 0xFF to the same byte of the register and checks if the signal gets deasserted.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
recovery_flow¶
Test: recovery_flow
The test exercises firmware image transfer flow using the recovery protocol. It consists of two agents running concurrently.
The AHB/AXI agent is responsible for recovery operation from the system bus side. It mimicks operation of the recovery handling firmware.
The BFM agent issues I3C transactions and is responsible for pushing a firmware image to the target.
The test runs at core clock of 100 and 200 MHz. The slowest clock that does not result in a tSCO violation is 166 MHz. The I3C bus clock is set to 12.5 MHz
target_peripheral_reset¶
Testpoints¶
target_peripheral_reset¶
Test: target_peripheral_reset
Issues I3C target reset pattern and verifies successful peripheral reset
target_escalated_reset¶
Test: target_escalated_reset
Issues I3C target reset patterns and verifies successful reset escalation