Introduction¶

This document summarizes the current state of the I3C core developed by Antmicro for Caliptra within CHIPS Alliance.

The implementation follows the Errata 01 for MIPI I3C Basic Specification Version 1.1.1 dated 11.03.2022.

Documentation structure¶

This documentation comprises the following chapters:

• I3C core overview - summarizes the main notions of the project

• I3C Common Command Codes (CCC) - provides an overview of the CCCs implemented by the core

• Physical Layer - provides a description of the I3C PHY Layer logic

• Design verification - describes verification tooling and testplans

• Specification for I3C Vendor-Specific Extended Capabilities - provides a description of Target Transaction Interface

• i3c_recovery_flow - describes the I3C-based Recovery mode workflow

• AXI Transaction ID Filtering - provides information about the AXI transactions filtering feature

• AXI driven Caliptra recovery flow - describes the alternative, optional, recovery flow where the recovery data is transferred to the core over the AXI bus

• Register descriptions - provides auto-generated register descriptions