Register descriptions¶

This chapter provides auto-generated register descriptions for the core.

I3CCSR address map¶

Absolute Address: 0x0
Base Offset: 0x0
Size: 0x1000

Offset	Identifier	Name
0x000	I3CBase	I3C Capability and Operational Registers
0x080	PIOControl	Programmable I/O
0x100	I3C_EC	Extended Capabilities
0x400	DAT	Device Address Table
0x800	DCT	Device Characteristic Table

I3CBase register file¶

Absolute Address: 0x0
Base Offset: 0x0
Size: 0x6C

Offset	Identifier	Name
0x00	HCI_VERSION	HCI Version
0x04	HC_CONTROL	Control
0x08	CONTROLLER_DEVICE_ADDR	Dynamic address
0x0C	HC_CAPABILITIES	Capabilities
0x10	RESET_CONTROL	Reset controls
0x14	PRESENT_STATE	Active controller
0x20	INTR_STATUS	Status
0x24	INTR_STATUS_ENABLE	Enable status reporting
0x28	INTR_SIGNAL_ENABLE	Enable status interrupts
0x2C	INTR_FORCE	Force status and interrupt
0x30	DAT_SECTION_OFFSET	DAT section offset
0x34	DCT_SECTION_OFFSET	DCT section offset
0x38	RING_HEADERS_SECTION_OFFSET	Ring section offset
0x3C	PIO_SECTION_OFFSET	PIO section offset
0x40	EXT_CAPS_SECTION_OFFSET	Extended capabilities section offset
0x4C	INT_CTRL_CMDS_EN	MIPI commands
0x58	IBI_NOTIFY_CTRL	I3C interrupts notification
0x5C	IBI_DATA_ABORT_CTRL	IBI data control
0x60	DEV_CTX_BASE_LO	Device context memory address lower 32 bits
0x64	DEV_CTX_BASE_HI	Device context memory address higher 32 bits
0x68	DEV_CTX_SG	SG control

HCI_VERSION register¶

Absolute Address: 0x0
Base Offset: 0x0
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	VERSION	r	0x120	—

HC_CONTROL register¶

Absolute Address: 0x4
Base Offset: 0x4
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	IBA_INCLUDE	rw	0x0	IBA_INCLUDE
3	AUTOCMD_DATA_RPT	r	0x0	AUTOCMD_DATA_RPT
4	DATA_BYTE_ORDER_MODE	r	0x0	DATA_BYTE_ORDER_MODE
6	MODE_SELECTOR	r	0x1	MODE_SELECTOR
7	I2C_DEV_PRESENT	rw	0x0	I2C_DEV_PRESENT
8	HOT_JOIN_CTRL	rw	0x0	HOT_JOIN_CTRL
12	HALT_ON_CMD_SEQ_TIMEOUT	rw	0x0	HALT_ON_CMD_SEQ_TIMEOUT
29	ABORT	rw	0x0	ABORT
30	RESUME	rw, woclr	0x0	RESUME
31	BUS_ENABLE	rw	0x0	BUS_ENABLE

IBA_INCLUDE field¶

Include I3C Broadcast Address:

0 - skips I3C Broadcast Address for private transfers

1 - includes I3C Broadcast Address for private transfers

AUTOCMD_DATA_RPT field¶

Auto-Command Data Report:

0 - coalesced reporting

1 - separated reporting

DATA_BYTE_ORDER_MODE field¶

Data Byte Ordering Mode:

0 - Little Endian

1 - Big Endian

MODE_SELECTOR field¶

DMA/PIO Mode Selector:

0 - DMA

1 - PIO

I2C_DEV_PRESENT field¶

I2C Device Present on Bus:

0 - pure I3C bus

1 - legacy I2C devices on the bus

HOT_JOIN_CTRL field¶

Hot-Join ACK/NACK Control:

0 - ACK Hot-Join request

1 - NACK Hot-Join request and send Broadcast CCC to disable Hot-Join

HALT_ON_CMD_SEQ_TIMEOUT field¶

Halt on Command Sequence Timeout when set to 1

ABORT field¶

Host Controller Abort when set to 1

RESUME field¶

Host Controller Resume:

0 - Controller is running

1 - Controller is suspended

Write 1 to resume Controller operations.

BUS_ENABLE field¶

Host Controller Bus Enable

CONTROLLER_DEVICE_ADDR register¶

Absolute Address: 0x8
Base Offset: 0x8
Size: 0x4

Bits	Identifier	Access	Reset	Name
22:16	DYNAMIC_ADDR	rw	0x0	DYNAMIC_ADDR
31	DYNAMIC_ADDR_VALID	rw	0x0	DYNAMIC_ADDR_VALID

DYNAMIC_ADDR field¶

Device Dynamic Address

DYNAMIC_ADDR_VALID field¶

Dynamic Address is Valid:

0 - dynamic address is invalid

1 - dynamic address is valid

HC_CAPABILITIES register¶

Absolute Address: 0xC
Base Offset: 0xC
Size: 0x4

Bits	Identifier	Access	Reset	Name
2	COMBO_COMMAND	r	0x0	COMBO_COMMAND
3	AUTO_COMMAND	r	0x0	AUTO_COMMAND
5	STANDBY_CR_CAP	r	0x0	STANDBY_CR_CAP
6	HDR_DDR_EN	r	0x0	HDR_DDR_EN
7	HDR_TS_EN	r	0x0	HDR_TS_EN
10	CMD_CCC_DEFBYTE	r	0x1	CMD_CCC_DEFBYTE
11	IBI_DATA_ABORT_EN	r	0x0	IBI_DATA_ABORT_EN
12	IBI_CREDIT_COUNT_EN	r	0x0	IBI_CREDIT_COUNT_EN
13	SCHEDULED_COMMANDS_EN	r	0x0	SCHEDULED_COMMANDS_EN
21:20	CMD_SIZE	r	0x0	CMD_SIZE
28	SG_CAPABILITY_CR_EN	r	0x0	SG_CAPABILITY_CR_EN
29	SG_CAPABILITY_IBI_EN	r	0x0	SG_CAPABILITY_IBI_EN
30	SG_CAPABILITY_DC_EN	r	0x0	SG_CAPABILITY_DC_EN

COMBO_COMMAND field¶

Controller combined command:

0 - not supported

1 - supported

AUTO_COMMAND field¶

Automatic read command on IBI:

0 - not supported

1 - supported

STANDBY_CR_CAP field¶

Switching from active to standby mode:

0 - not supported, this controller is always active on I3C

1- supported, this controller can hand off I3C to secondary controller

HDR_DDR_EN field¶

HDR-DDR transfers:

0 - not supported

1 - supported

HDR_TS_EN field¶

HDR-Ternary transfers:

0 - not supported

1 - supported

CMD_CCC_DEFBYTE field¶

CCC with defining byte:

0 - not supported

1 - supported

IBI_DATA_ABORT_EN field¶

Controller IBI data abort:

0 - not supported

1 - supported

IBI_CREDIT_COUNT_EN field¶

Controller IBI credit count:

0 - not supported

1 - supported

SCHEDULED_COMMANDS_EN field¶

Controller command scheduling:

0 - not supported

1 - supported

CMD_SIZE field¶

Size and structure of the Command Descriptor:

2'b0: 2 DWORDs,

all other reserved.

SG_CAPABILITY_CR_EN field¶

DMA only: Command and Response rings memory:

0 - must be physically continuous

1 - controller supports scatter-gather

SG_CAPABILITY_IBI_EN field¶

DMA only: IBI status and IBI Data rings memory:

0 - must be physically continuous

1 - controller supports scatter-gather

SG_CAPABILITY_DC_EN field¶

Device context memory:

0 - must be physically continuous

1 - controller supports scatter-gather

RESET_CONTROL register¶

Absolute Address: 0x10
Base Offset: 0x10
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	SOFT_RST	rw	0x0	SOFT_RST
1	CMD_QUEUE_RST	rw	0x0	CMD_QUEUE_RST
2	RESP_QUEUE_RST	rw	0x0	RESP_QUEUE_RST
3	TX_FIFO_RST	rw	0x0	TX_FIFO_RST
4	RX_FIFO_RST	rw	0x0	RX_FIFO_RST
5	IBI_QUEUE_RST	rw	0x0	IBI_QUEUE_RST

SOFT_RST field¶

Reset controller from software.

CMD_QUEUE_RST field¶

Clear command queue from software. Valid only in PIO mode.

RESP_QUEUE_RST field¶

Clear response queue from software. Valid only in PIO mode.

TX_FIFO_RST field¶

Clear TX FIFO from software. Valid only in PIO mode.

RX_FIFO_RST field¶

Clear RX FIFO from software. Valid only in PIO mode.

IBI_QUEUE_RST field¶

Clear IBI queue from software. Valid only in PIO mode.

PRESENT_STATE register¶

Absolute Address: 0x14
Base Offset: 0x14
Size: 0x4

Bits	Identifier	Access	Reset	Name
2	AC_CURRENT_OWN	r	0x0	AC_CURRENT_OWN

AC_CURRENT_OWN field¶

Controller I3C state:

0 - not bus owner

1 - bus owner

INTR_STATUS register¶

Absolute Address: 0x20
Base Offset: 0x20
Size: 0x4

Bits	Identifier	Access	Reset	Name
10	HC_INTERNAL_ERR_STAT	rw, woclr	0x0	HC_INTERNAL_ERR_STAT
11	HC_SEQ_CANCEL_STAT	rw, woclr	0x0	HC_SEQ_CANCEL_STAT
12	HC_WARN_CMD_SEQ_STALL_STAT	rw, woclr	0x0	HC_WARN_CMD_SEQ_STALL_STAT
13	HC_ERR_CMD_SEQ_TIMEOUT_STAT	rw, woclr	0x0	HC_ERR_CMD_SEQ_TIMEOUT_STAT
14	SCHED_CMD_MISSED_TICK_STAT	rw, woclr	0x0	SCHED_CMD_MISSED_TICK_STAT

HC_INTERNAL_ERR_STAT field¶

Controller internal unrecoverable error.

HC_SEQ_CANCEL_STAT field¶

Controller had to cancel command sequence.

HC_WARN_CMD_SEQ_STALL_STAT field¶

Clock stalled due to lack of commands.

HC_ERR_CMD_SEQ_TIMEOUT_STAT field¶

Command timeout after prolonged stall.

SCHED_CMD_MISSED_TICK_STAT field¶

Scheduled commands could be executed due to controller being busy.

INTR_STATUS_ENABLE register¶

Absolute Address: 0x24
Base Offset: 0x24
Size: 0x4

Bits	Identifier	Access	Reset	Name
10	HC_INTERNAL_ERR_STAT_EN	rw	0x0	HC_INTERNAL_ERR_STAT_EN
11	HC_SEQ_CANCEL_STAT_EN	rw	0x0	HC_SEQ_CANCEL_STAT_EN
12	HC_WARN_CMD_SEQ_STALL_STAT_EN	rw	0x0	HC_WARN_CMD_SEQ_STALL_STAT_EN
13	HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN	rw	0x0	HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN
14	SCHED_CMD_MISSED_TICK_STAT_EN	rw	0x0	SCHED_CMD_MISSED_TICK_STAT_EN

HC_INTERNAL_ERR_STAT_EN field¶

Enable HC_INTERNAL_ERR_STAT monitoring.

HC_SEQ_CANCEL_STAT_EN field¶

Enable HC_SEQ_CANCEL_STAT monitoring.

HC_WARN_CMD_SEQ_STALL_STAT_EN field¶

Enable HC_WARN_CMD_SEQ_STALL_STAT monitoring.

HC_ERR_CMD_SEQ_TIMEOUT_STAT_EN field¶

Enable HC_ERR_CMD_SEQ_TIMEOUT_STAT monitoring.

SCHED_CMD_MISSED_TICK_STAT_EN field¶

Enable SCHED_CMD_MISSED_TICK_STAT monitoring.

INTR_SIGNAL_ENABLE register¶

Absolute Address: 0x28
Base Offset: 0x28
Size: 0x4

Bits	Identifier	Access	Reset	Name
10	HC_INTERNAL_ERR_SIGNAL_EN	rw	0x0	HC_INTERNAL_ERR_SIGNAL_EN
11	HC_SEQ_CANCEL_SIGNAL_EN	rw	0x0	HC_SEQ_CANCEL_SIGNAL_EN
12	HC_WARN_CMD_SEQ_STALL_SIGNAL_EN	rw	0x0	HC_WARN_CMD_SEQ_STALL_SIGNAL_EN
13	HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN	rw	0x0	HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN
14	SCHED_CMD_MISSED_TICK_SIGNAL_EN	rw	0x0	SCHED_CMD_MISSED_TICK_SIGNAL_EN

HC_INTERNAL_ERR_SIGNAL_EN field¶

Enable HC_INTERNAL_ERR_STAT interrupt.

HC_SEQ_CANCEL_SIGNAL_EN field¶

Enable HC_SEQ_CANCEL_STAT interrupt.

HC_WARN_CMD_SEQ_STALL_SIGNAL_EN field¶

Enable HC_WARN_CMD_SEQ_STALL_STAT interrupt.

HC_ERR_CMD_SEQ_TIMEOUT_SIGNAL_EN field¶

Enable HC_ERR_CMD_SEQ_TIMEOUT_STAT interrupt.

SCHED_CMD_MISSED_TICK_SIGNAL_EN field¶

Enable SCHED_CMD_MISSED_TICK_STAT interrupt.

INTR_FORCE register¶

Absolute Address: 0x2C
Base Offset: 0x2C
Size: 0x4

Bits	Identifier	Access	Reset	Name
10	HC_INTERNAL_ERR_FORCE	w	0x0	HC_INTERNAL_ERR_FORCE
11	HC_SEQ_CANCEL_FORCE	w	0x0	HC_SEQ_CANCEL_FORCE
12	HC_WARN_CMD_SEQ_STALL_FORCE	w	0x0	HC_WARN_CMD_SEQ_STALL_FORCE
13	HC_ERR_CMD_SEQ_TIMEOUT_FORCE	w	0x0	HC_ERR_CMD_SEQ_TIMEOUT_FORCE
14	SCHED_CMD_MISSED_TICK_FORCE	w	0x0	SCHED_CMD_MISSED_TICK_FORCE

HC_INTERNAL_ERR_FORCE field¶

Force HC_INTERNAL_ERR_STAT interrupt.

HC_SEQ_CANCEL_FORCE field¶

Force HC_SEQ_CANCEL_STAT interrupt.

HC_WARN_CMD_SEQ_STALL_FORCE field¶

Force HC_WARN_CMD_SEQ_STALL_STAT interrupt.

HC_ERR_CMD_SEQ_TIMEOUT_FORCE field¶

Force HC_ERR_CMD_SEQ_TIMEOUT_STAT interrupt.

SCHED_CMD_MISSED_TICK_FORCE field¶

Force SCHED_CMD_MISSED_TICK_STAT interrupt.

DAT_SECTION_OFFSET register¶

Absolute Address: 0x30
Base Offset: 0x30
Size: 0x4

Bits	Identifier	Access	Reset	Name
11:0	TABLE_OFFSET	r	0x400	TABLE_OFFSET
18:12	TABLE_SIZE	r	0x7F	TABLE_SIZE
31:28	ENTRY_SIZE	r	0x0	ENTRY_SIZE

TABLE_OFFSET field¶

DAT entry offset in respect to BASE address.

TABLE_SIZE field¶

Max number of DAT entries.

ENTRY_SIZE field¶

Individual DAT entry size. 0 - 2 DWRODs, 1:15 - reserved.

DCT_SECTION_OFFSET register¶

Absolute Address: 0x34
Base Offset: 0x34
Size: 0x4

Bits	Identifier	Access	Reset	Name
11:0	TABLE_OFFSET	r	0x800	TABLE_OFFSET
18:12	TABLE_SIZE	r	0x7F	TABLE_SIZE
23:19	TABLE_INDEX	rw	0x0	TABLE_INDEX
31:28	ENTRY_SIZE	r	0x0	ENTRY_SIZE

TABLE_OFFSET field¶

DCT entry offset in respect to BASE address.

TABLE_SIZE field¶

Max number of DCT entries.

TABLE_INDEX field¶

Index to DCT used during ENTDAA.

ENTRY_SIZE field¶

Individual DCT entry size.

0 - 4 DWORDs,

1:15 - Reserved.

RING_HEADERS_SECTION_OFFSET register¶

Absolute Address: 0x38
Base Offset: 0x38
Size: 0x4

Bits	Identifier	Access	Reset	Name
15:0	SECTION_OFFSET	r	0x0	SECTION_OFFSET

SECTION_OFFSET field¶

DMA ring headers section offset. Invalid if 0.

PIO_SECTION_OFFSET register¶

Absolute Address: 0x3C
Base Offset: 0x3C
Size: 0x4

Bits	Identifier	Access	Reset	Name
15:0	SECTION_OFFSET	r	0x80	SECTION_OFFSET

SECTION_OFFSET field¶

PIO section offset. Invalid if 0.

EXT_CAPS_SECTION_OFFSET register¶

Absolute Address: 0x40
Base Offset: 0x40
Size: 0x4

Bits	Identifier	Access	Reset	Name
15:0	SECTION_OFFSET	r	0x100	SECTION_OFFSET

SECTION_OFFSET field¶

Extended Capabilities section offset. Invalid if 0.

INT_CTRL_CMDS_EN register¶

Absolute Address: 0x4C
Base Offset: 0x4C
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	ICC_SUPPORT	r	0x1	ICC_SUPPORT
15:1	MIPI_CMDS_SUPPORTED	r	0x35	MIPI_CMDS_SUPPORTED

ICC_SUPPORT field¶

Internal Control Commands:

1 - some or all internals commands sub-commands are supported,

0 - illegal.

MIPI_CMDS_SUPPORTED field¶

Bitmask of supported MIPI commands.

IBI_NOTIFY_CTRL register¶

Absolute Address: 0x58
Base Offset: 0x58
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	NOTIFY_HJ_REJECTED	rw	0x0	NOTIFY_HJ_REJECTED
1	NOTIFY_CRR_REJECTED	rw	0x0	NOTIFY_CRR_REJECTED
3	NOTIFY_IBI_REJECTED	rw	0x0	NOTIFY_IBI_REJECTED

NOTIFY_HJ_REJECTED field¶

Notify about rejected hot-join:

0 - do not enqueue rejected HJ,

1 = enqueue rejected HJ on IBI queue/ring.

NOTIFY_CRR_REJECTED field¶

Notify about rejected controller role request:

0 - do not enqueue rejected CRR,

1 = enqueue rejected CRR on IBI queue/ring.

NOTIFY_IBI_REJECTED field¶

Notify about rejected IBI:

0 - do not enqueue rejected IBI,

1 = enqueue rejected IBI on IBI queue/ring.

IBI_DATA_ABORT_CTRL register¶

Absolute Address: 0x5C
Base Offset: 0x5C
Size: 0x4

Bits	Identifier	Access	Reset	Name
15:8	MATCH_IBI_ID	rw	0x0	MATCH_IBI_ID
17:16	AFTER_N_CHUNKS	rw	0x0	AFTER_N_CHUNKS
20:18	MATCH_STATUS_TYPE	rw	0x0	MATCH_STATUS_TYPE
31	IBI_DATA_ABORT_MON	rw	0x0	IBI_DATA_ABORT_MON

MATCH_IBI_ID field¶

IBI target address:

[15:9] - device address,

[8] - must always be set to 1'b1

AFTER_N_CHUNKS field¶

Number of data chunks to be allowed before forced termination:

0 - immediate,

1:3 - delay by 1-3 data chunks.

MATCH_STATUS_TYPE field¶

Define which IBI should be aborted:

3'b000 - Regular IBI,

3'b100 - Autocmd IBI,

other values - not supported.

IBI_DATA_ABORT_MON field¶

Enable/disable IBI monitoring logic.

DEV_CTX_BASE_LO register¶

Absolute Address: 0x60
Base Offset: 0x60
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	BASE_LO	rw	0x0	—

DEV_CTX_BASE_HI register¶

Absolute Address: 0x64
Base Offset: 0x64
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	BASE_HI	rw	0x0	—

DEV_CTX_SG register¶

Absolute Address: 0x68
Base Offset: 0x68
Size: 0x4

Bits	Identifier	Access	Reset	Name
15:0	LIST_SIZE	r	0x0	LIST_SIZE
31	BLP	r	0x0	BLP

LIST_SIZE field¶

Number of SG entries.

BLP field¶

Buffer vs list pointer in device context:

0 - continuous physical memory region,

1 - pointer to SG descriptor list.

PIOControl register file¶

Absolute Address: 0x80
Base Offset: 0x80
Size: 0x34

Offset	Identifier	Name
0x00	COMMAND_PORT	Command issue port
0x04	RESPONSE_PORT	Command response port
0x08	TX_DATA_PORT	Transferred data access port
0x08	RX_DATA_PORT	Received data access port
0x0C	IBI_PORT	IBI descriptor access port
0x10	QUEUE_THLD_CTRL	The Queue Threshold Control register for the Command Queue, the Response Queue, and the IBI Queue
0x14	DATA_BUFFER_THLD_CTRL	RX/TX queue threshold control
0x18	QUEUE_SIZE	Queue sizes
0x1C	ALT_QUEUE_SIZE	Alternate queue sizes
0x20	PIO_INTR_STATUS	PIO interrupt status
0x24	PIO_INTR_STATUS_ENABLE	—
0x28	PIO_INTR_SIGNAL_ENABLE	Interrupt Signal Enable
0x2C	PIO_INTR_FORCE	PIO force interrupt status
0x30	PIO_CONTROL	PIO control

COMMAND_PORT register¶

Absolute Address: 0x80
Base Offset: 0x0
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	COMMAND_DATA	w	—	COMMAND_QUEUE_PORT

RESPONSE_PORT register¶

Absolute Address: 0x84
Base Offset: 0x4
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	RESPONSE_DATA	r	—	RESPONSE_QUEUE_PORT

TX_DATA_PORT register¶

Absolute Address: 0x88
Base Offset: 0x8
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	TX_DATA	w	—	TX_DATA

RX_DATA_PORT register¶

Absolute Address: 0x88
Base Offset: 0x8
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	RX_DATA	r	—	RX_DATA

IBI_PORT register¶

Absolute Address: 0x8C
Base Offset: 0xC
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	IBI_DATA	r	—	IBI_DATA

IBI_DATA field¶

Data Read from IBI Data Buffer.

The IBI Port is mapped to the IBI Data Queue. IBI Data is always aligned to a 4-byte boundary and then put into the IBI Queue. If the incoming data is not aligned to a 4-byte boundary, then there will be extra (unused) bytes at the end of the transferred IBI data. This can be determined from the value of field DATA_LENGTH in the IBI Status Descriptor.

QUEUE_THLD_CTRL register¶

Absolute Address: 0x90
Base Offset: 0x10
Size: 0x4

Bits	Identifier	Access	Reset	Name
7:0	CMD_EMPTY_BUF_THLD	rw	0x1	CMD_EMPTY_BUF_THLD
15:8	RESP_BUF_THLD	rw	0x1	RESP_BUF_THLD
23:16	IBI_DATA_SEGMENT_SIZE	rw	0x1	IBI_DATA_SEGMENT_SIZE
31:24	IBI_STATUS_THLD	rw	0x1	IBI_STATUS_THLD

CMD_EMPTY_BUF_THLD field¶

Triggers CMD_QUEUE_READY_STAT interrupt when CMD queue has N or more free entries. Accepted values are 1:255

RESP_BUF_THLD field¶

Triggers RESP_READY_STAT interrupt when RESP queue has N or more entries. Accepted values are 1:255

IBI_DATA_SEGMENT_SIZE field¶

IBI Queue data segment size. Valida values are 1:63

IBI_STATUS_THLD field¶

Triggers IBI_STATUS_THLD_STAT interrupt when IBI queue has N or more entries. Accepted values are 1:255

DATA_BUFFER_THLD_CTRL register¶

Absolute Address: 0x94
Base Offset: 0x14
Size: 0x4

Bits	Identifier	Access	Reset	Name
2:0	TX_BUF_THLD	rw	0x1	TX_BUF_THLD
10:8	RX_BUF_THLD	rw	0x1	RX_BUF_THLD
18:16	TX_START_THLD	rw	0x1	TX_START_THLD
26:24	RX_START_THLD	rw	0x1	RX_START_THLD

TX_BUF_THLD field¶

Trigger TX_THLD_STAT interrupt when TX queue has 2^(N+1) or more free entries

RX_BUF_THLD field¶

Trigger RX_THLD_STAT interrupt when RX queue has 2^(N+1) or more entries

TX_START_THLD field¶

Postpone write command until TX queue has 2^(N+1) entries

RX_START_THLD field¶

Postpone read command until RX queue has 2^(N+1) free entries

QUEUE_SIZE register¶

Absolute Address: 0x98
Base Offset: 0x18
Size: 0x4

Bits	Identifier	Access	Reset	Name
7:0	CR_QUEUE_SIZE	r	0x40	CR_QUEUE_SIZE
15:8	IBI_STATUS_SIZE	r	0x40	IBI_STATUS_SIZE
23:16	RX_DATA_BUFFER_SIZE	r	0x5	RX_DATA_BUFFER_SIZE
31:24	TX_DATA_BUFFER_SIZE	r	0x5	TX_DATA_BUFFER_SIZE

CR_QUEUE_SIZE field¶

Command/Response queue size is equal to N

IBI_STATUS_SIZE field¶

IBI Queue size is equal to N

RX_DATA_BUFFER_SIZE field¶

RX queue size is equal to 2^(N+1), where N is this field value

TX_DATA_BUFFER_SIZE field¶

TX queue size is equal to 2^(N+1), where N is this field value

ALT_QUEUE_SIZE register¶

Absolute Address: 0x9C
Base Offset: 0x1C
Size: 0x4

Bits	Identifier	Access	Reset	Name
7:0	ALT_RESP_QUEUE_SIZE	r	0x40	ALT_RESP_QUEUE_SIZE
24	ALT_RESP_QUEUE_EN	r	0x0	ALT_RESP_QUEUE_EN
28	EXT_IBI_QUEUE_EN	r	0x0	EXT_IBI_QUEUE_EN

ALT_RESP_QUEUE_SIZE field¶

Valid only if ALT_RESP_QUEUE_EN is set. Contains response queue size

ALT_RESP_QUEUE_EN field¶

If set, response and command queues are not equal lengths, then ALT_RESP_QUEUE_SIZE contains response queue size

EXT_IBI_QUEUE_EN field¶

1 indicates that IBI queue size is equal to 8*IBI_STATUS_SIZE

PIO_INTR_STATUS register¶

Absolute Address: 0xA0
Base Offset: 0x20
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	TX_THLD_STAT	r	0x0	TX_THLD_STAT
1	RX_THLD_STAT	r	0x0	RX_THLD_STAT
2	IBI_STATUS_THLD_STAT	r	0x0	IBI_STATUS_THLD_STAT
3	CMD_QUEUE_READY_STAT	r	0x0	CMD_QUEUE_READY_STAT
4	RESP_READY_STAT	r	0x0	RESP_READY_STAT
5	TRANSFER_ABORT_STAT	rw, woclr	0x0	TRANSFER_ABORT_STAT
9	TRANSFER_ERR_STAT	rw, woclr	0x0	TRANSFER_ERR_STAT

TX_THLD_STAT field¶

TX queue fulfils TX_BUF_THLD

RX_THLD_STAT field¶

RX queue fulfils RX_BUF_THLD

IBI_STATUS_THLD_STAT field¶

IBI queue fulfils IBI_STATUS_THLD

CMD_QUEUE_READY_STAT field¶

Command queue fulfils CMD_EMPTY_BUF_THLD

RESP_READY_STAT field¶

Response queue fulfils RESP_BUF_THLD

TRANSFER_ABORT_STAT field¶

Transfer aborted

TRANSFER_ERR_STAT field¶

Transfer error

PIO_INTR_STATUS_ENABLE register¶

Absolute Address: 0xA4
Base Offset: 0x24
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	TX_THLD_STAT_EN	rw	0x0	TX_THLD_STAT_EN
1	RX_THLD_STAT_EN	rw	0x0	RX_THLD_STAT_EN
2	IBI_STATUS_THLD_STAT_EN	rw	0x0	IBI_STATUS_THLD_STAT_EN
3	CMD_QUEUE_READY_STAT_EN	rw	0x0	CMD_QUEUE_READY_STAT_EN
4	RESP_READY_STAT_EN	rw	0x0	RESP_READY_STAT_EN
5	TRANSFER_ABORT_STAT_EN	rw	0x0	TRANSFER_ABORT_STAT_EN
9	TRANSFER_ERR_STAT_EN	rw	0x0	TRANSFER_ERR_STAT_EN

TX_THLD_STAT_EN field¶

Enable TX queue monitoring

RX_THLD_STAT_EN field¶

Enable RX queue monitoring

IBI_STATUS_THLD_STAT_EN field¶

Enable IBI queue monitoring

CMD_QUEUE_READY_STAT_EN field¶

Enable command queue monitoring

RESP_READY_STAT_EN field¶

Enable response queue monitoring

TRANSFER_ABORT_STAT_EN field¶

Enable transfer abort monitoring

TRANSFER_ERR_STAT_EN field¶

Enable transfer error monitoring

PIO_INTR_SIGNAL_ENABLE register¶

Absolute Address: 0xA8
Base Offset: 0x28
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	TX_THLD_SIGNAL_EN	rw	0x0	TX_THLD_SIGNAL_EN
1	RX_THLD_SIGNAL_EN	rw	0x0	RX_THLD_SIGNAL_EN
2	IBI_STATUS_THLD_SIGNAL_EN	rw	0x0	IBI_STATUS_THLD_SIGNAL_EN
3	CMD_QUEUE_READY_SIGNAL_EN	rw	0x0	CMD_QUEUE_READY_SIGNAL_EN
4	RESP_READY_SIGNAL_EN	rw	0x0	RESP_READY_SIGNAL_EN
5	TRANSFER_ABORT_SIGNAL_EN	rw	0x0	TRANSFER_ABORT_SIGNAL_EN
9	TRANSFER_ERR_SIGNAL_EN	rw	0x0	TRANSFER_ERR_SIGNAL_EN

TX_THLD_SIGNAL_EN field¶

Enable TX queue interrupt

RX_THLD_SIGNAL_EN field¶

Enable RX queue interrupt

IBI_STATUS_THLD_SIGNAL_EN field¶

Enable IBI queue interrupt

CMD_QUEUE_READY_SIGNAL_EN field¶

Enable command queue interrupt

RESP_READY_SIGNAL_EN field¶

Enable response ready interrupt

TRANSFER_ABORT_SIGNAL_EN field¶

Enable transfer abort interrupt

TRANSFER_ERR_SIGNAL_EN field¶

Enable transfer error interrupt

PIO_INTR_FORCE register¶

Absolute Address: 0xAC
Base Offset: 0x2C
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	TX_THLD_FORCE	w	0x0	TX_THLD_FORCE
1	RX_THLD_FORCE	w	0x0	RX_THLD_FORCE
2	IBI_THLD_FORCE	w	0x0	IBI_THLD_FORCE
3	CMD_QUEUE_READY_FORCE	w	0x0	CMD_QUEUE_READY_FORCE
4	RESP_READY_FORCE	w	0x0	RESP_READY_FORCE
5	TRANSFER_ABORT_FORCE	w	0x0	TRANSFER_ABORT_FORCE
9	TRANSFER_ERR_FORCE	w	0x0	TRANSFER_ERR_FORCE

TX_THLD_FORCE field¶

Force TX queue interrupt

RX_THLD_FORCE field¶

Force RX queue interrupt

IBI_THLD_FORCE field¶

Force IBI queue interrupt

CMD_QUEUE_READY_FORCE field¶

Force command queue interrupt

RESP_READY_FORCE field¶

Force response queue interrupt

TRANSFER_ABORT_FORCE field¶

Force transfer aborted

TRANSFER_ERR_FORCE field¶

Force transfer error

PIO_CONTROL register¶

Absolute Address: 0xB0
Base Offset: 0x30
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	ENABLE	rw	0x1	ENABLE
1	RS	rw	0x0	RS
2	ABORT	rw	0x0	ABORT

ENABLE field¶

Enables PIO queues. When disabled, SW may not read from/write to PIO queues. 1 - PIO queue enable request, 0 - PIO queue disable request

RS field¶

Run/Stop execution of enqueued commands. When set to 0, it holds execution of enqueued commands and runs current command to completion. 1 - PIO Queue start request, 0 - PIO Queue stop request.

ABORT field¶

Stop current command descriptor execution forcefully and hold remaining commands. 1 - Request PIO Abort, 0 - Resume PIO execution

I3C_EC register file¶

Absolute Address: 0x100
Base Offset: 0x100
Size: 0x1A4

Offset	Identifier	Name
0x000	StdbyCtrlMode	Standby Controller Mode
0x100	SoCMgmtIf	SoC Management Interface
0x198	CtrlCfg	Controller Config
0x1A0	TERMINATION_EXTCAP_HEADER	—

StdbyCtrlMode register file¶

Absolute Address: 0x100
Base Offset: 0x0
Size: 0x44

Offset	Identifier	Name
0x00	EXTCAP_HEADER	—
0x04	STBY_CR_CONTROL	Standby Controller Control
0x08	STBY_CR_DEVICE_ADDR	Standby Controller Device Address
0x0C	STBY_CR_CAPABILITIES	Standby Controller Capabilities
0x10	STBY_CR_VIRTUAL_DEVICE_CHAR	Standby Controller Virtual Device Characteristics
0x14	STBY_CR_STATUS	Standby Controller Status
0x18	STBY_CR_DEVICE_CHAR	Standby Controller Device Characteristics
0x1C	STBY_CR_DEVICE_PID_LO	Standby Controller Device PID Low
0x20	STBY_CR_INTR_STATUS	Standby Controller Interrupt Status
0x24	STBY_CR_VIRTUAL_DEVICE_PID_LO	Standby Controller Virtual Device PID Low
0x28	STBY_CR_INTR_SIGNAL_ENABLE	Standby Controller Interrupt Signal Enable
0x2C	STBY_CR_INTR_FORCE	Standby Controller Interrupt Force
0x30	STBY_CR_CCC_CONFIG_GETCAPS	Standby Controller CCC Configuration GETCAPS
0x34	STBY_CR_CCC_CONFIG_RSTACT_PARAMS	Standby Controller CCC Configuration RSTACT
0x38	STBY_CR_VIRT_DEVICE_ADDR	Standby Virtual Controller Device Address
0x3C	STBY_CR_MWL	Standby Controller Maximum Write Length (read-only)
0x40	STBY_CR_MRL	Standby Controller Maximum Read Length and IBI Payload Size (read-only)

EXTCAP_HEADER register¶

Absolute Address: 0x100
Base Offset: 0x0
Size: 0x4

Bits	Identifier	Access	Reset	Name
7:0	CAP_ID	r	0x12	CAP_ID
23:8	CAP_LENGTH	r	0x20	CAP_LENGTH

CAP_ID field¶

Extended Capability ID

CAP_LENGTH field¶

Capability Structure Length in DWORDs

STBY_CR_CONTROL register¶

Absolute Address: 0x104
Base Offset: 0x4
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	PENDING_RX_NACK	rw	0x0	Pending RX NACK
1	HANDOFF_DELAY_NACK	rw	0x0	Handoff Delay NACK
2	ACR_FSM_OP_SELECT	rw	0x0	Active Controller Select
3	PRIME_ACCEPT_GETACCCR	rw	0x0	Prime to Accept Controller Role
4	HANDOFF_DEEP_SLEEP	rw, wset	0x0	Handoff Deep Sleep
5	CR_REQUEST_SEND	w	0x0	Send Controller Role Request
10:8	BAST_CCC_IBI_RING	rw	0x0	Ring Bundle IBI Selector for Broadcast CCC Capture
12	TARGET_XACT_ENABLE	rw	0x1	Target Transaction Interface Servicing Enable
13	DAA_SETAASA_ENABLE	rw	0x0	Dynamic Address Method Enable SETAASA
14	DAA_SETDASA_ENABLE	rw	0x0	Dynamic Address Method Enable SETDASA
15	DAA_ENTDAA_ENABLE	rw	0x0	Dynamic Address Method Enable ENTDAA
20	RSTACT_DEFBYTE_02	rw	0x0	RSTACT Support DefByte 0x02
31:30	STBY_CR_ENABLE_INIT	rw	0x0	Host Controller Secondary Controller Enable

PENDING_RX_NACK field¶

HANDOFF_DELAY_NACK field¶

ACR_FSM_OP_SELECT field¶

PRIME_ACCEPT_GETACCCR field¶

HANDOFF_DEEP_SLEEP field¶

If this field has a value of 1'b1, then the Secondary Controller Logic shall report a return from Deep Sleep state to the Active Controller. Writing 1'b1 to this bit is sticky. This field shall automatically clear to 1'b0 after accepting the Controller Role and transitioning to Active Controller mode.

CR_REQUEST_SEND field¶

Write of 1'b1 to this field shall instruct the Secondary Controller Logic to attempt to send a Controller Role Request to the I3C Bus.

BAST_CCC_IBI_RING field¶

Indicates which Ring Bundle will be used to capture Broadcast CCC data sent by the Active Controller. The Ring Bundle must be configured and enabled, and its IBI Ring Pair must also be initialized and ready to receive data.

TARGET_XACT_ENABLE field¶

Indicates whether Read-Type/Write-Type transaction servicing is enabled, via an I3C Target Transaction Interface to software (Section 6.17.3).

1'b0: DISABLED: not available

1'b1: ENABLED: available for software

DAA_SETAASA_ENABLE field¶

Indicates SETAASA method is enabled.

1'b0: DISABLED: will not respond

1'b1: ENABLED: will respond

DAA_SETDASA_ENABLE field¶

Indicates SETDASA method is enabled.

1'b0: DISABLED: will not respond

1'b1: ENABLED: will respond

DAA_ENTDAA_ENABLE field¶

Indicates ENTDAA method is enabled.

1'b0: DISABLED: will not respond

1'b1: ENABLED: will respond

RSTACT_DEFBYTE_02 field¶

Controls whether I3C Secondary Controller Logic supports RSTACT CCC with Defining Byte 0x02.

1'b0: NOT_SUPPORTED: Do not ACK Defining Byte 0x02

1'b1: HANDLE_INTR: Support Defining Byte 0x02

STBY_CR_ENABLE_INIT field¶

Enables or disables the Secondary Controller:

2'b00 - DISABLED: Secondary Controller is disabled.

2'b01 - ACM_INIT: Secondary Controller is enabled, but Host Controller initializes in Active Controller mode.

2'b10 - SCM_RUNNING: Secondary Controller operation is enabled, Host Controller initializes in Standby Controller mode.

2'b11 - SCM_HOT_JOIN: Secondary Controller operation is enabled, Host Controller conditionally becomes a Hot-Joining Device to receive its Dynamic Address before operating in Standby Controller mode.

STBY_CR_DEVICE_ADDR register¶

Absolute Address: 0x108
Base Offset: 0x8
Size: 0x4

Bits	Identifier	Access	Reset	Name
6:0	STATIC_ADDR	rw	0x0	Device Static Address
15	STATIC_ADDR_VALID	rw	0x0	Static Address is Valid
22:16	DYNAMIC_ADDR	rw	0x0	Device Dynamic Address
31	DYNAMIC_ADDR_VALID	rw	0x0	Dynamic Address is Valid

STATIC_ADDR field¶

This field contains the Host Controller Device’s Static Address.

STATIC_ADDR_VALID field¶

Indicates whether or not the value in the STATIC_ADDR field is valid.

1'b0: The Static Address field is not valid

1'b1: The Static Address field is valid

DYNAMIC_ADDR field¶

Contains the Host Controller Device’s Dynamic Address.

DYNAMIC_ADDR_VALID field¶

Indicates whether or not the value in the DYNAMIC_ADDR field is valid. 1'b0: DYNAMIC_ADDR field is not valid 1'b1: DYNAMIC_ADDR field is valid

STBY_CR_CAPABILITIES register¶

Absolute Address: 0x10C
Base Offset: 0xC
Size: 0x4

Bits	Identifier	Access	Reset	Name
5	SIMPLE_CRR_SUPPORT	r	0x0	SIMPLE_CRR_SUPPORT
12	TARGET_XACT_SUPPORT	r	0x1	TARGET_XACT_SUPPORT
13	DAA_SETAASA_SUPPORT	r	0x1	DAA_SETAASA_SUPPORT
14	DAA_SETDASA_SUPPORT	r	0x1	DAA_SETDASA_SUPPORT
15	DAA_ENTDAA_SUPPORT	r	0x0	DAA_ENTDAA_SUPPORT

SIMPLE_CRR_SUPPORT field¶

TARGET_XACT_SUPPORT field¶

Defines whether an I3C Target Transaction Interface is supported.

1'b0: DISABLED: Not supported

1'b1: ENABLED: Supported via vendor-defined Extended Capability structure

DAA_SETAASA_SUPPORT field¶

Defines whether Dynamic Address Assignment with SETAASA CCC (using Static Address) is supported.

1'b0: DISABLED: Not supported

1'b1: ENABLED: Supported

DAA_SETDASA_SUPPORT field¶

Defines whether Dynamic Address Assignment with SETDASA CCC (using Static Address) is supported.

1'b0: DISABLED: Not supported

1'b1: ENABLED: Supported

DAA_ENTDAA_SUPPORT field¶

Defines whether Dynamic Address Assignment with ENTDAA CCC is supported.

1'b0: DISABLED: Not supported

1'b1: ENABLED: Supported

STBY_CR_VIRTUAL_DEVICE_CHAR register¶

Absolute Address: 0x110
Base Offset: 0x10
Size: 0x4

Bits	Identifier	Access	Reset	Name
15:1	PID_HI	rw	0x7FFF	PID_HI
23:16	DCR	rw	0xBD	DCR
28:24	BCR_VAR	rw	0x10	BCR_VAR
31:29	BCR_FIXED	rw	0x1	BCR_FIXED

PID_HI field¶

High part of the 48-bit Target Device Provisioned ID.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register STBY_CR_CONTROL is not zero.

DCR field¶

Device Characteristics Register. Value represents an OCP Recovery Device.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register STBY_CR_CONTROL is not zero.

BCR_VAR field¶

Bus Characteristics, Variable Part.

Reset value is set to 5'b10000, because this device:

[bit4] is a Virtual Target
[bit3] is not Offline Capable
[bit2] does not apply due to bit1
[bit1] is not capable of IBI requests
[bit0] has no speed limitation

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register STBY_CR_CONTROL is not zero.

BCR_FIXED field¶

Bus Characteristics, Fixed Part.

Reset value is set to 3'b001, because this device is an I3C Target, which supports extended capabilities.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register STBY_CR_CONTROL is not zero.

STBY_CR_STATUS register¶

Absolute Address: 0x114
Base Offset: 0x14
Size: 0x4

Bits	Identifier	Access	Reset	Name
2	AC_CURRENT_OWN	rw	0x0	AC_CURRENT_OWN
7:5	SIMPLE_CRR_STATUS	rw	0x0	SIMPLE_CRR_STATUS
8	HJ_REQ_STATUS	rw	0x0	HJ_REQ_STATUS

AC_CURRENT_OWN field¶

SIMPLE_CRR_STATUS field¶

HJ_REQ_STATUS field¶

STBY_CR_DEVICE_CHAR register¶

Absolute Address: 0x118
Base Offset: 0x18
Size: 0x4

Bits	Identifier	Access	Reset	Name
15:1	PID_HI	rw	0x7FFF	PID_HI
23:16	DCR	rw	0xBD	DCR
28:24	BCR_VAR	rw	0x16	BCR_VAR
31:29	BCR_FIXED	rw	0x1	BCR_FIXED

PID_HI field¶

High part of the 48-bit Target Device Provisioned ID.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register STBY_CR_CONTROL is not zero.

DCR field¶

Device Characteristics Register. Value represents an OCP Recovery Device.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register STBY_CR_CONTROL is not zero.

BCR_VAR field¶

Bus Characteristics, Variable Part.

Reset value is set to 5'b10110, because this device:

[bit4] exposes a Virtual Target
[bit3] is not Offline Capable
[bit2] (always) uses the MDB in the IBI Payload
[bit1] is capable of IBI requests
[bit0] has no speed limitation

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register STBY_CR_CONTROL is not zero.

BCR_FIXED field¶

Bus Characteristics, Fixed Part.

Reset value is set to 3'b001, because this device is an I3C Target, which supports extended capabilities

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register STBY_CR_CONTROL is not zero.

STBY_CR_DEVICE_PID_LO register¶

Absolute Address: 0x11C
Base Offset: 0x1C
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	PID_LO	rw	0x5A00A5	PID_LO

PID_LO field¶

Low part of the 48-bit Target Device Provisioned ID.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register STBY_CR_CONTROL is not zero.

STBY_CR_INTR_STATUS register¶

Absolute Address: 0x120
Base Offset: 0x20
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	ACR_HANDOFF_OK_REMAIN_STAT	rw	0x0
1	ACR_HANDOFF_OK_PRIMED_STAT	rw	0x0
2	ACR_HANDOFF_ERR_FAIL_STAT	rw	0x0
3	ACR_HANDOFF_ERR_M3_STAT	rw	0x0
10	CRR_RESPONSE_STAT	rw	0x0
11	STBY_CR_DYN_ADDR_STAT	rw	0x0
12	STBY_CR_ACCEPT_NACKED_STAT	rw	0x0
13	STBY_CR_ACCEPT_OK_STAT	rw	0x0
14	STBY_CR_ACCEPT_ERR_STAT	rw	0x0
16	STBY_CR_OP_RSTACT_STAT	rw	0x0	Secondary Controller Operation Reset Action
17	CCC_PARAM_MODIFIED_STAT	rw	0x0
18	CCC_UNHANDLED_NACK_STAT	rw	0x0
19	CCC_FATAL_RSTDAA_ERR_STAT	rw	0x0

ACR_HANDOFF_OK_REMAIN_STAT field¶

ACR_HANDOFF_OK_PRIMED_STAT field¶

ACR_HANDOFF_ERR_FAIL_STAT field¶

ACR_HANDOFF_ERR_M3_STAT field¶

CRR_RESPONSE_STAT field¶

STBY_CR_DYN_ADDR_STAT field¶

STBY_CR_ACCEPT_NACKED_STAT field¶

STBY_CR_ACCEPT_OK_STAT field¶

STBY_CR_ACCEPT_ERR_STAT field¶

STBY_CR_OP_RSTACT_STAT field¶

The Host Controller shall write 1'b1 to this field to indicate that the Secondary Controller received a RSTACT CCC from the Active Controller, followed by the Target Reset Pattern.

CCC_PARAM_MODIFIED_STAT field¶

CCC_UNHANDLED_NACK_STAT field¶

CCC_FATAL_RSTDAA_ERR_STAT field¶

STBY_CR_VIRTUAL_DEVICE_PID_LO register¶

Absolute Address: 0x124
Base Offset: 0x24
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	PID_LO	rw	0x5A10A5	PID_LO

PID_LO field¶

Low part of the 48-bit Target Virtual Device Provisioned ID.

This field is Read-Only while the STBY_CR_ENABLE_INIT field in register STBY_CR_CONTROL is not zero.

STBY_CR_INTR_SIGNAL_ENABLE register¶

Absolute Address: 0x128
Base Offset: 0x28
Size: 0x4

When set to 1'b1, and the corresponding interrupt status field is set in register STBY_CR_INTR_STATUS, the Host Controller shall assert an interrupt to the Host.

Bits	Identifier	Access	Reset
0	ACR_HANDOFF_OK_REMAIN_SIGNAL_EN	rw	0x0
1	ACR_HANDOFF_OK_PRIMED_SIGNAL_EN	rw	0x0
2	ACR_HANDOFF_ERR_FAIL_SIGNAL_EN	rw	0x0
3	ACR_HANDOFF_ERR_M3_SIGNAL_EN	rw	0x0
10	CRR_RESPONSE_SIGNAL_EN	rw	0x0
11	STBY_CR_DYN_ADDR_SIGNAL_EN	rw	0x0
12	STBY_CR_ACCEPT_NACKED_SIGNAL_EN	rw	0x0
13	STBY_CR_ACCEPT_OK_SIGNAL_EN	rw	0x0
14	STBY_CR_ACCEPT_ERR_SIGNAL_EN	rw	0x0
16	STBY_CR_OP_RSTACT_SIGNAL_EN	rw	0x0
17	CCC_PARAM_MODIFIED_SIGNAL_EN	rw	0x0
18	CCC_UNHANDLED_NACK_SIGNAL_EN	rw	0x0
19	CCC_FATAL_RSTDAA_ERR_SIGNAL_EN	rw	0x0

ACR_HANDOFF_OK_REMAIN_SIGNAL_EN field¶

ACR_HANDOFF_OK_PRIMED_SIGNAL_EN field¶

ACR_HANDOFF_ERR_FAIL_SIGNAL_EN field¶

ACR_HANDOFF_ERR_M3_SIGNAL_EN field¶

CRR_RESPONSE_SIGNAL_EN field¶

STBY_CR_DYN_ADDR_SIGNAL_EN field¶

STBY_CR_ACCEPT_NACKED_SIGNAL_EN field¶

STBY_CR_ACCEPT_OK_SIGNAL_EN field¶

STBY_CR_ACCEPT_ERR_SIGNAL_EN field¶

STBY_CR_OP_RSTACT_SIGNAL_EN field¶

CCC_PARAM_MODIFIED_SIGNAL_EN field¶

CCC_UNHANDLED_NACK_SIGNAL_EN field¶

CCC_FATAL_RSTDAA_ERR_SIGNAL_EN field¶

STBY_CR_INTR_FORCE register¶

Absolute Address: 0x12C
Base Offset: 0x2C
Size: 0x4

For software testing, when set to 1'b1, forces the corresponding interrupt to be sent to the Host, if the corresponding fields are set in register STBY_CR_INTR_SIGNAL_ENABLE

Bits	Identifier	Access	Reset
10	CRR_RESPONSE_FORCE	rw	0x0
11	STBY_CR_DYN_ADDR_FORCE	rw	0x0
12	STBY_CR_ACCEPT_NACKED_FORCE	rw	0x0
13	STBY_CR_ACCEPT_OK_FORCE	rw	0x0
14	STBY_CR_ACCEPT_ERR_FORCE	rw	0x0
16	STBY_CR_OP_RSTACT_FORCE	w	0x0
17	CCC_PARAM_MODIFIED_FORCE	rw	0x0
18	CCC_UNHANDLED_NACK_FORCE	rw	0x0
19	CCC_FATAL_RSTDAA_ERR_FORCE	rw	0x0

CRR_RESPONSE_FORCE field¶

STBY_CR_DYN_ADDR_FORCE field¶

STBY_CR_ACCEPT_NACKED_FORCE field¶

STBY_CR_ACCEPT_OK_FORCE field¶

STBY_CR_ACCEPT_ERR_FORCE field¶

STBY_CR_OP_RSTACT_FORCE field¶

CCC_PARAM_MODIFIED_FORCE field¶

CCC_UNHANDLED_NACK_FORCE field¶

CCC_FATAL_RSTDAA_ERR_FORCE field¶

STBY_CR_CCC_CONFIG_GETCAPS register¶

Absolute Address: 0x130
Base Offset: 0x30
Size: 0x4

Bits	Identifier	Access	Reset	Name
2:0	F2_CRCAP1_BUS_CONFIG	rw	0x0
11:8	F2_CRCAP2_DEV_INTERACT	rw	0x0

F2_CRCAP1_BUS_CONFIG field¶

F2_CRCAP2_DEV_INTERACT field¶

STBY_CR_CCC_CONFIG_RSTACT_PARAMS register¶

Absolute Address: 0x134
Base Offset: 0x34
Size: 0x4

Bits	Identifier	Access	Reset	Name
7:0	RST_ACTION	r	0x1	Defining Byte of the RSTACT CCC
15:8	RESET_TIME_PERIPHERAL	rw	0x0	Time to Reset Peripheral
23:16	RESET_TIME_TARGET	rw	0x0	Time to Reset Target
31	RESET_DYNAMIC_ADDR	rw	0x1	Reset Dynamic Address after Target Reset

RST_ACTION field¶

Contains the Defining Byte received with the last Direct SET CCC sent by the Active Controller. If not armed (START or RSTACT with unsupported defining byte) set to spec default 0x1.

RESET_TIME_PERIPHERAL field¶

For Direct GET CCC, this field is returned for Defining Byte 0x81.

RESET_TIME_TARGET field¶

For Direct GET CCC, this field is returned for Defining Byte 0x82.

RESET_DYNAMIC_ADDR field¶

If set to 1'b1, then the Secondary Controller Logic must clear its Dynamic Address in register STBY_CR_DEVICE_ADDR after receiving a Target Reset Pattern that followed a Broadcast or Direct SET RSTACT CCC sent to the Dynamic Address, with Defining Byte 0x01 or 0x02. Requires support for Dynamic Address Assignment with at least one supported method, such as the ENTDAA CCC, with field DAA_ENTDAA_ENABLE set to 1'b1 in register STBY_CR_CONTROL. If field ACR_FSM_OP_SELECT in register STBY_CR_CONTROL is set to 1'b1, then this field shall be cleared (i.e., readiness to accept the Controller Role shall be revoked) with this Target Reset Pattern.

STBY_CR_VIRT_DEVICE_ADDR register¶

Absolute Address: 0x138
Base Offset: 0x38
Size: 0x4

Bits	Identifier	Access	Reset	Name
6:0	VIRT_STATIC_ADDR	rw	0x0	Device Static Address
15	VIRT_STATIC_ADDR_VALID	rw	0x0	Virtual Device Static Address is Valid
22:16	VIRT_DYNAMIC_ADDR	rw	0x0	Virtual Device Dynamic Address
31	VIRT_DYNAMIC_ADDR_VALID	rw	0x0	Virtual Device Dynamic Address is Valid

VIRT_STATIC_ADDR field¶

This field contains the Host Controller Device’s Static Address.

VIRT_STATIC_ADDR_VALID field¶

Indicates whether or not the value in the VIRT_STATIC_ADDR field is valid.

1'b0: The Virtual Device Static Address field is not valid

1'b1: The Virtual Device Static Address field is valid

VIRT_DYNAMIC_ADDR field¶

Contains the Controller Virtual Device’s Dynamic Address.

VIRT_DYNAMIC_ADDR_VALID field¶

Indicates whether or not the value in the VIRT_DYNAMIC_ADDR field is valid. 1'b0: VIRT_DYNAMIC_ADDR field is not valid 1'b1: VIRT_DYNAMIC_ADDR field is valid

STBY_CR_MWL register¶

Absolute Address: 0x13C
Base Offset: 0x3C
Size: 0x4

Bits	Identifier	Access	Reset	Name
15:0	MWL	r	0x100	Maximum Write Length

MWL field¶

This field contains the maximum write length (MWL) (read-only)

STBY_CR_MRL register¶

Absolute Address: 0x140
Base Offset: 0x40
Size: 0x4

Bits	Identifier	Access	Reset	Name
15:0	MRL	r	0x100	Maximum Read Length
23:16	IBIL	r	0x10	IBI Payload Size

MRL field¶

This field contains the maximum read length (MRL) (read-only)

IBIL field¶

This field contains the IBI payload size (IBIL) (read-only)

SoCMgmtIf register file¶

Absolute Address: 0x200
Base Offset: 0x100
Size: 0x94

Offset	Identifier	Name
0x00	EXTCAP_HEADER	—
0x04	SOC_MGMT_CONTROL	SoC Management Control
0x08	SOC_MGMT_STATUS	SoC Management Status
0x0C	REC_INTF_CFG	Configuration of Recovery Interface
0x10	REC_INTF_REG_W1C_ACCESS	Mock hardware register access
0x14	SOC_MGMT_RSVD_2
0x18	SOC_MGMT_RSVD_3
0x1C	SOC_PAD_CONF	I3C Pad Configuration Register
0x20	SOC_PAD_ATTR	I3C Pad Attribute Configuration Register
0x24	SOC_MGMT_FEATURE_2
0x28	SOC_MGMT_FEATURE_3
0x2C	T_R_REG
0x30	T_F_REG
0x34	T_SU_DAT_REG
0x38	T_SU_DAT_I2C_REG
0x3C	T_HD_DAT_REG
0x40	T_HIGH_REG
0x44	T_HIGH_OD_REG
0x48	T_HIGH_INIT_OD_REG
0x4C	T_HIGH_I2C_REG
0x50	T_LOW_REG
0x54	T_LOW_OD_REG
0x58	T_LOW_I2C_REG
0x5C	T_HD_STA_REG
0x60	T_HD_STA_I2C_REG
0x64	T_HD_RSTA_REG
0x68	T_SU_STA_REG
0x6C	T_SU_STA_I2C_REG
0x70	T_SU_STO_REG
0x74	T_SU_STO_I2C_REG
0x78	T_DS_OD_REG
0x7C	T_FREE_REG
0x80	T_FREE_I2C_REG
0x84	T_AVAL_REG
0x88	T_IDLE_REG
0x8C	HDR_TIMEOUT_EN_REG
0x90	T_HDR_TIMEOUT_REG

EXTCAP_HEADER register¶

Absolute Address: 0x200
Base Offset: 0x0
Size: 0x4

Bits	Identifier	Access	Reset	Name
7:0	CAP_ID	r	0xC1	CAP_ID
23:8	CAP_LENGTH	r	0x1A	CAP_LENGTH

CAP_ID field¶

Extended Capability ID

CAP_LENGTH field¶

Capability Structure Length in DWORDs

SOC_MGMT_CONTROL register¶

Absolute Address: 0x204
Base Offset: 0x4
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	PLACEHOLDER	rw	0x0

PLACEHOLDER field¶

SOC_MGMT_STATUS register¶

Absolute Address: 0x208
Base Offset: 0x8
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	PLACEHOLDER	rw	0x0

PLACEHOLDER field¶

REC_INTF_CFG register¶

Absolute Address: 0x20C
Base Offset: 0xC
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	REC_INTF_BYPASS	rw	0x0	Recovery Interface access type
1	REC_PAYLOAD_DONE	rw	0x0	Recovery payload done

REC_INTF_BYPASS field¶

Choose Recovery Interface access type:

0 - I3C Core
1 - direct AXI

REC_PAYLOAD_DONE field¶

Inform Recovery Handler that payload transfer is finished.

REC_INTF_REG_W1C_ACCESS register¶

Absolute Address: 0x210
Base Offset: 0x10
Size: 0x4

Bits	Identifier	Access	Reset	Name
7:0	DEVICE_RESET_CTRL	rw	0x0	HW Device Reset Control
15:8	RECOVERY_CTRL_ACTIVATE_REC_IMG	rw	0x0	HW Activate Recovery Image
23:16	INDIRECT_FIFO_CTRL_RESET	rw	0x0	HW Indirect FIFO Reset Control

DEVICE_RESET_CTRL field¶

Write to 'Reset control - Device Reset Control' register, mocking a hardware access (bypassing 'write 1 to clear' register property).

RECOVERY_CTRL_ACTIVATE_REC_IMG field¶

Write to 'Recovery Control - Activate Recovery Image' register, mocking a hardware access (bypassing 'write 1 to clear' register property).

INDIRECT_FIFO_CTRL_RESET field¶

Write to 'Indirect memory configuration - reset' register, mocking a hardware access (bypassing 'write 1 to clear' register property).

SOC_MGMT_RSVD_2 register¶

Absolute Address: 0x214
Base Offset: 0x14
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	PLACEHOLDER	rw	0x0

PLACEHOLDER field¶

SOC_MGMT_RSVD_3 register¶

Absolute Address: 0x218
Base Offset: 0x18
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	PLACEHOLDER	rw	0x0

PLACEHOLDER field¶

SOC_PAD_CONF register¶

Absolute Address: 0x21C
Base Offset: 0x1C
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	INPUT_ENABLE	rw	0x1	Enable Input
1	SCHMITT_EN	rw	0x0	Schmitt Trigger Enable
2	KEEPER_EN	rw	0x0	High-Keeper Enable
3	PULL_DIR	rw	0x0	Pull Direction
4	PULL_EN	rw	0x0	Pull Enable
5	IO_INVERSION	rw	0x0	IO INVERSION
6	OD_EN	rw	0x0	Open-Drain Enable
7	VIRTUAL_OD_EN	rw	0x0	Virtual Open Drain Enable
31:24	PAD_TYPE	rw	0x1	Pad type

INPUT_ENABLE field¶

Enable input:

0 - enabled

1 - disabled

SCHMITT_EN field¶

Enable the Schmitt Trigger:

0 - disabled

1 - enabled

KEEPER_EN field¶

Enable the High-Keeper:

0 - disabled

1 - enabled

PULL_DIR field¶

Direction of the pull:

0 - Pull down

1 - Pull up

PULL_EN field¶

Enable Pull:

0 - disabled

1 - enabled

IO_INVERSION field¶

Invert I/O signal:

0 - signals pass-through

1 - signals are inverted

OD_EN field¶

Enable Open-Drain:

0 - disabled

1 - enabled

VIRTUAL_OD_EN field¶

Enable virtual open drain:

0 - disabled

1 - enabled

PAD_TYPE field¶

Select pad type

0 - Bidirectional

1 - Open-drain

2 - Input-only

3 - Analog input

SOC_PAD_ATTR register¶

Absolute Address: 0x220
Base Offset: 0x20
Size: 0x4

Bits	Identifier	Access	Reset	Name
15:8	DRIVE_SLEW_RATE	rw	0xF	Driver Slew Rate
31:24	DRIVE_STRENGTH	rw	0xF	Driver Strength

DRIVE_SLEW_RATE field¶

Select driver slew rate

'0 - lowest

'1 - highest

DRIVE_STRENGTH field¶

Select driver strength

'0 - lowest

'1 - highest

SOC_MGMT_FEATURE_2 register¶

Absolute Address: 0x224
Base Offset: 0x24
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	PLACEHOLDER	rw	0x0

PLACEHOLDER field¶

Reserved for: I/O ring and pad configuration

SOC_MGMT_FEATURE_3 register¶

Absolute Address: 0x228
Base Offset: 0x28
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	PLACEHOLDER	rw	0x0

PLACEHOLDER field¶

Reserved for: I/O ring and pad configuration

T_R_REG register¶

Absolute Address: 0x22C
Base Offset: 0x2C
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_R	rw	0x0

T_R field¶

Rise time of both SDA and SCL in clock units

T_F_REG register¶

Absolute Address: 0x230
Base Offset: 0x30
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_F	rw	0x0

T_F field¶

Fall time of both SDA and SCL in clock units

T_SU_DAT_REG register¶

Absolute Address: 0x234
Base Offset: 0x34
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_SU_DAT	rw	0x0

T_SU_DAT field¶

Data setup time in clock units

T_SU_DAT_I2C_REG register¶

Absolute Address: 0x238
Base Offset: 0x38
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_SU_DAT_I2C	rw	0x0

T_SU_DAT_I2C field¶

Data setup time in I2C mode in clock units

T_HD_DAT_REG register¶

Absolute Address: 0x23C
Base Offset: 0x3C
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_HD_DAT	rw	0x0

T_HD_DAT field¶

Data hold time in clock units

T_HIGH_REG register¶

Absolute Address: 0x240
Base Offset: 0x40
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_HIGH	rw	0x0	High period of the SCL in clock units

T_HIGH field¶

T_HIGH_OD_REG register¶

Absolute Address: 0x244
Base Offset: 0x44
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_HIGH_OD	rw	0x0	High period of the SCL in Open-Drain mode in clock units

T_HIGH_OD field¶

T_HIGH_INIT_OD_REG register¶

Absolute Address: 0x248
Base Offset: 0x48
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_HIGH_INIT_OD	rw	0x0	High period of the SCL in Open-Drain mode during bus initialization in clock units

T_HIGH_INIT_OD field¶

T_HIGH_I2C_REG register¶

Absolute Address: 0x24C
Base Offset: 0x4C
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_HIGH_I2C	rw	0x0	High period of the SCL in I2C mode in clock units

T_HIGH_I2C field¶

T_LOW_REG register¶

Absolute Address: 0x250
Base Offset: 0x50
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_LOW	rw	0x0

T_LOW field¶

Low period of the SCL in clock units

T_LOW_OD_REG register¶

Absolute Address: 0x254
Base Offset: 0x54
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_LOW_OD	rw	0x0

T_LOW_OD field¶

Low period of the SCL in Open-Drain mode in clock units

T_LOW_I2C_REG register¶

Absolute Address: 0x258
Base Offset: 0x58
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_LOW_I2C	rw	0x0

T_LOW_I2C field¶

Low period of the SCL in I2C mode in clock units

T_HD_STA_REG register¶

Absolute Address: 0x25C
Base Offset: 0x5C
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_HD_STA	rw	0x0

T_HD_STA field¶

Hold time for START in clock units

T_HD_STA_I2C_REG register¶

Absolute Address: 0x260
Base Offset: 0x60
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_HD_STA_I2C	rw	0x0

T_HD_STA_I2C field¶

Hold time for START in I2C mode in clock units

T_HD_RSTA_REG register¶

Absolute Address: 0x264
Base Offset: 0x64
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_HD_RSTA	rw	0x0

T_HD_RSTA field¶

Hold time for repeated START in clock units

T_SU_STA_REG register¶

Absolute Address: 0x268
Base Offset: 0x68
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_SU_STA	rw	0x0

T_SU_STA field¶

Setup time for repeated START in clock units

T_SU_STA_I2C_REG register¶

Absolute Address: 0x26C
Base Offset: 0x6C
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_SU_STA_I2C	rw	0x0

T_SU_STA_I2C field¶

Setup time for repeated START in I2C mode in clock units

T_SU_STO_REG register¶

Absolute Address: 0x270
Base Offset: 0x70
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_SU_STO	rw	0x0

T_SU_STO field¶

Setup time for STOP in clock units

T_SU_STO_I2C_REG register¶

Absolute Address: 0x274
Base Offset: 0x74
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_SU_STO_I2C	rw	0x0

T_SU_STO_I2C field¶

Setup time for STOP in in I2C mode clock units

T_DS_OD_REG register¶

Absolute Address: 0x278
Base Offset: 0x78
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_DS_OD	rw	0x0

T_DS_OD field¶

Setup time for SDA during START in clock units

T_FREE_REG register¶

Absolute Address: 0x27C
Base Offset: 0x7C
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	T_FREE	rw	0xC

T_FREE field¶

Bus Free Time Between a STOP and a START

T_FREE_I2C_REG register¶

Absolute Address: 0x280
Base Offset: 0x80
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	T_FREE_I2C	rw	0xC

T_FREE_I2C field¶

Bus Free Time Between a STOP and a START in I2C mode

T_AVAL_REG register¶

Absolute Address: 0x284
Base Offset: 0x84
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	T_AVAL	rw	0x12C

T_AVAL field¶

T_IDLE_REG register¶

Absolute Address: 0x288
Base Offset: 0x88
Size: 0x4

Bits	Identifier	Access	Reset	Name
31:0	T_IDLE	rw	0xEA60

T_IDLE field¶

Time in clock cycles from STOP detection until Bus Idle Condition (tIDLE). Configure based on System Clock

HDR_TIMEOUT_EN_REG register¶

Absolute Address: 0x28C
Base Offset: 0x8C
Size: 0x4

Bits	Identifier	Access	Reset	Name
0	HDR_TIMEOUT_EN	rw	0x0

HDR_TIMEOUT_EN field¶

Enable bit for the optional 60us HDR error recovery timer (I3C spec 5.1.10.1.9). When enabled, the Target can recover from TE0/TE1 errors if both SCL and SDA stay High for a period exceeding the configured threshold. Disabled on reset.

T_HDR_TIMEOUT_REG register¶

Absolute Address: 0x290
Base Offset: 0x90
Size: 0x4

Bits	Identifier	Access	Reset	Name
19:0	T_HDR_TIMEOUT	rw	0xEA60

T_HDR_TIMEOUT field¶

Timer threshold in clock cycles for the optional HDR error recovery (I3C spec 5.1.10.1.9). If both SCL and SDA stay High for this many clock cycles during a TE0/TE1 error-induced HDR mode, the Target exits HDR mode and returns to Idle. Configure based on System Clock to achieve 60us.

CtrlCfg register file¶

Absolute Address: 0x298
Base Offset: 0x198
Size: 0x8

Offset	Identifier	Name
0x0	EXTCAP_HEADER	—
0x4	CONTROLLER_CONFIG	Controller Config

EXTCAP_HEADER register¶

Absolute Address: 0x298
Base Offset: 0x0
Size: 0x4

Bits	Identifier	Access	Reset	Name
7:0	CAP_ID	r	0x2	CAP_ID
23:8	CAP_LENGTH	r	0x2	CAP_LENGTH

CAP_ID field¶

Extended Capability ID

CAP_LENGTH field¶

Capability Structure Length in DWORDs

CONTROLLER_CONFIG register¶

Absolute Address: 0x29C
Base Offset: 0x4
Size: 0x4

Bits	Identifier	Access	Reset	Name
5:4	OPERATION_MODE	r	0x1	Operation Mode

OPERATION_MODE field¶

TERMINATION_EXTCAP_HEADER register¶

Absolute Address: 0x2A0
Base Offset: 0x1A0
Size: 0x4

Register after the last EC must advertise ID == 0. Termination register is added to guarantee that the discovery mechanism reaches termination value.

Bits	Identifier	Access	Reset	Name
7:0	CAP_ID	r	0x0	CAP_ID
23:8	CAP_LENGTH	r	0x1	CAP_LENGTH

CAP_ID field¶

Extended Capability ID

CAP_LENGTH field¶

Capability Structure Length in DWORDs

DAT memory¶

Absolute Address: 0x400
Base Offset: 0x400
Size: 0x400

Offset	Identifier	Name
0x0	DAT_MEMORY[128]	—

DAT_MEMORY register¶

Absolute Address: 0x400
Base Offset: 0x0
Size: 0x400
Array Dimensions: [128]
Array Stride: 0x8
Total Size: 0x400

Bits	Identifier	Access	Reset	Name
6:0	STATIC_ADDRESS	rw	—	STATIC_ADDRESS
12	IBI_PAYLOAD	rw	—	IBI_PAYLOAD
13	IBI_REJECT	rw	—	IBI_REJECT
14	CRR_REJECT	rw	—	CRR_REJECT
15	TS	rw	—	TS
23:16	DYNAMIC_ADDRESS	rw	—	DYNAMIC_ADDRESS
28:26	RING_ID	rw	—	RING_ID
30:29	DEV_NACK_RETRY_CNT	rw	—	DEV_NACK_RETRY_CNT
31	DEVICE	rw	—	DEVICE
39:32	AUTOCMD_MASK	rw	—	AUTOCMD_MASK
47:40	AUTOCMD_VALUE	rw	—	AUTOCMD_VALUE
50:48	AUTOCMD_MODE	rw	—	AUTOCMD_MODE
58:51	AUTOCMD_HDR_CODE	rw	—	AUTOCMD_HDR_CODE

STATIC_ADDRESS field¶

I3C/I2C static device address

IBI_PAYLOAD field¶

Device's IBI contains data payload

IBI_REJECT field¶

Reject device's request for IBI

CRR_REJECT field¶

Reject device's request for controller change

TS field¶

Enable/disable IBI timestamp

DYNAMIC_ADDRESS field¶

I3C dynamic address

RING_ID field¶

Send IBI read to ring bundle

DEV_NACK_RETRY_CNT field¶

Number of retries before giving up

DEVICE field¶

Device type: 0 - I3C device, 1 - I2C device.

AUTOCMD_MASK field¶

IBI mask

AUTOCMD_VALUE field¶

IBI value that triggers auto command

AUTOCMD_MODE field¶

Auto command mode and speed

AUTOCMD_HDR_CODE field¶

Device auto command in HDR mode

DCT memory¶

Absolute Address: 0x800
Base Offset: 0x800
Size: 0x800

Offset	Identifier	Name
0x0	DCT_MEMORY[128]	—

DCT_MEMORY register¶

Absolute Address: 0x800
Base Offset: 0x0
Size: 0x800
Array Dimensions: [128]
Array Stride: 0x10
Total Size: 0x800

Bits	Identifier	Access	Reset	Name
31:0	PID_HI	r	—	PID_HI
47:32	PID_LO	r	—	PID_LO
71:64	DCR	r	—	DCR
79:72	BCR	r	—	BCR
103:96	DYNAMIC_ADDRESS	r	—	DYNAMIC_ADDRESS

PID_HI field¶

Device Provisional ID High

PID_LO field¶

Device Provisional ID Low

DCR field¶

Value of the I3C device's Device Characteristics Register

BCR field¶

Value of the I3C device's Bus Characteristics Register

DYNAMIC_ADDRESS field¶

Device I3C Dynamic Address after ENTDAA

Last update: 2026-08-04