| Controller I3C flow | 1 | 3 | 33.3% | 1 | 1 | 100% |
| Controller CCC generation | 11 | 11 | 100% | 11 | 11 | 100% |
| Controller-specific CSR access check | 6 | 7 | 85.7% | 2 | 6 | 33.3% |
| Controller error generation | 8 | 8 | 100% | 8 | 8 | 100% |
| Controller Generate HDR Exit Pattern | 1 | 1 | 100% | 1 | 1 | 100% |
| Controller Hot-Join procedure for a new target | 0 | 1 | 0.0% | 0 | 0 | --% |
| Controller I2C Transaction | 2 | 3 | 66.7% | 2 | 2 | 100% |
| Controller IBI Handling | 3 | 3 | 100% | 3 | 3 | 100% |
| Controller Private Read | 3 | 3 | 100% | 3 | 3 | 100% |
| Controller resets target | 0 | 1 | 0.0% | 0 | 0 | --% |
| Controller Private Write | 7 | 8 | 87.5% | 7 | 7 | 100% |
| Target | 23 | 23 | 100% | 23 | 23 | 100% |
| Data over-/underflow handling | 6 | 6 | 100% | 6 | 6 | 100% |
| Bus timers top-level | 6 | 6 | 100% | 6 | 6 | 100% |
| CCC handling | 72 | 74 | 97.3% | 78 | 78 | 100% |
| CSR access check | 16 | 17 | 94.1% | 12 | 16 | 75.0% |
| Empty queue read handling | 12 | 12 | 100% | 12 | 12 | 100% |
| Enter and exit HDR mode | 12 | 12 | 100% | 12 | 12 | 100% |
| IBI handling | 35 | 38 | 92.1% | 35 | 35 | 100% |
| Target interrupts | 5 | 8 | 62.5% | 9 | 9 | 100% |
| Recovery mode tests | 54 | 54 | 100% | 55 | 55 | 100% |
| Recovery bypass | 12 | 12 | 100% | 12 | 12 | 100% |
| target_peripheral_reset | 16 | 16 | 100% | 16 | 16 | 100% |
| Target error detection | 20 | 20 | 100% | 20 | 20 | 100% |
| tSCO timing verification | 2 | 2 | 100% | 2 | 2 | 100% |