| Name | Implemented tests | Planned tests | Implementation progress | Passing runs | Total runs | Pass Rate |
|---|---|---|---|---|---|---|
| Target | 10 | 10 | 100% | 10 | 10 | 100% |
| Data over-/underflow handling | 0 | 6 | 0.0% | 0 | 0 | --% |
| CCC handling | 21 | 21 | 100% | 26 | 26 | 100% |
| CSR access check | 10 | 10 | 100% | 6 | 10 | 60.0% |
| Target error detection | 6 | 6 | 100% | 6 | 6 | 100% |
| Enter and exit HDR mode | 4 | 4 | 100% | 4 | 4 | 100% |
| Target interrupts | 0 | 4 | 0.0% | 0 | 0 | --% |
| Recovery mode tests | 17 | 17 | 100% | 22 | 22 | 100% |
| Recovery bypass | 10 | 11 | 90.9% | 14 | 14 | 100% |
| target_peripheral_reset | 2 | 2 | 100% | 2 | 2 | 100% |
Progress of stages
| Stage | Implemented tests | Planned tests | Implementation progress | Passing runs | Total runs | Pass Rate |
|---|---|---|---|---|---|---|
| N.A. | 80 | 91 | 87.9% | 90 | 94 | 95.7% |