Error Detection and Recovery¶

This chapter describes the error detection registers, interrupt wiring, error counters, and recovery mechanisms implemented in the I3C core.

For definitions of the Target Error types (TE0-TE5), refer to the I3C Basic specification v1.1.1, Sections 5.1.10.1 through 5.1.10.6.

Error Signal Path¶

Each error is detected in the RTL control logic and routed to the TTI as a single-cycle pulse. The TTI contains per-error interrupt logic and an 8-bit saturating counter. The flow is:

Detection (ctrl/) --> pulse --> TTI interrupt_ctl --> STATUS bit + IRQ
                           \-> TTI counter       --> 8-bit saturating count

Error Detection Sources¶

The following table shows where each error originates in the RTL and what detection enable register bit gates it:

All detection enable bits reset to 1 (enabled). FW may clear individual bits to suppress detection for debug purposes.

Interrupt Registers¶

Each error has a corresponding bit in three TTI registers. All share the same bit positions:

Register behavior:

• TARGET_ERR_INTR_STATUS: Read to see pending errors. Write-1-to-clear.

• TARGET_ERR_INTR_ENABLE: Set bits to allow the corresponding error to propagate to the aggregated irq_o output. The status bit is set regardless of the enable; the enable only gates the IRQ line.

• TARGET_ERR_INTR_FORCE: Set bits to force the corresponding status bit high (for testing). Auto-clears.

All error interrupts are OR’d together with the TTI queue interrupts into a single irq_o output (assign irq_o = |irqs).

Error Counters¶

Each error type has an 8-bit saturating counter. Counters increment on every error pulse (per-byte, not per-transfer) and saturate at 0xFF.

Counters are RW. Write any value to set the counter (write 0 to clear). Counters increment independently of the detection enable and interrupt enable bits – if the error pulse fires, the counter increments.

Error Recovery Mechanisms¶

HDR Exit Pattern Detection¶

Per I3C spec Section 5.2.1.1.1. The implementation uses a shift register that counts SDA falling edges while SCL is held low. After 4 edges, the HDR Exit Pattern is detected and the Target exits HDR mode.

HDR Error Recovery Timeout¶

Per I3C spec Section 5.1.10.1.9. When enabled via HDR_TIMEOUT_EN_REG = 1, the Target counts cycles where both SCL and SDA are stable high while in HDR error mode (entered due to TE0 or TE1). When the count reaches T_HDR_TIMEOUT_REG, the Target exits HDR mode. See Firmware Integration Guide Step 4 for configuration.

Target Reset Pattern Detection¶

The target_reset_detector module monitors the bus for the Target Reset Pattern and asserts target_reset_detect_o when detected.

Protocol Error Reporting (GETSTATUS)¶

TTI.STATUS.PROTOCOL_ERROR (bit 8) is set when any of the following occur:

• TE1 (CCC command parity error)

• TE2 (CCC or Private Write data parity error)

• Framing error (SETDASA/SETNEWDA padding bit)

This bit is readable by the Controller via the GETSTATUS CCC (Format 1). It is sticky and remains set until cleared.

Queue Status Registers¶

For debug and monitoring, the TTI provides real-time queue status: