I3C Common Command Codes (CCC)¶

The I3C core supports all CCCs required by the I3C Basic spec, please see “Table 16 I3C Common Command Codes” for a full reference.

All CCCs are exercised with Cocotb tests.

Broadcast CCCs¶

The following Broadcast CCCs are currently supported by the core (all required Broadcast CCCs as per the errata, and one optional Broadcast CCC):

• ENEC (R) - Enable Events Command

• DISEC (R) - Disable Events Command

• SETMWL (R) - Set Max Write Length

• SETMRL (R) - Set Max Read Length

• SETAASA (O) - Set All Addresses to Static Addresses

• ENTDAA (R) - Enter Dynamic Address Assignment

• RSTDAA (R) - Reset Dynamic Address Assignment

• RSTACT (R) - Target Reset Action

  • Broadcast (Format 1) supports defining bytes 0x0, 0x1 and 0x2

The following Broadcast CCCs are recognized but not actively handled (the core ACKs or NACKs as appropriate per the specification):

• ENTAS0-ENTAS3 - Enter Activity State (acknowledged, no behavioral change)

• ENTHDR0-ENTHDR7 - Enter HDR Mode (triggers HDR mode entry; HDR data transfer is not supported)

• ENDXFER - Data Transfer Ending Procedure Control

• SETBUSCON - Set Bus Context

• DEFGRPA / RSTGRPA - Group Address (not supported, NACKed)

• MLANE - Multi-Lane (not supported, NACKed)

Direct CCCs¶

The following Direct CCCs are currently supported by the core (all required Direct CCCs, plus several optional/conditional ones):

• ENEC (R) - Enable Events Command

• DISEC (R) - Disable Events Command

• SETDASA (O) - Set Dynamic Address from Static Address

  • Primary (Format 1)

• SETNEWDA (C) - Set New Dynamic Address

• SETMWL (R) - Set Max Write Length

• SETMRL (R) - Set Max Read Length

• GETMWL (R) - Get Max Write Length

• GETMRL (R) - Get Max Read Length

• GETPID (C) - Get Provisioned ID

• GETBCR (C) - Get Bus Characteristics Register

• GETDCR (C) - Get Device Characteristics Register

• GETSTATUS (R) - Get Device Status

  • The two-byte format (Format 1)

• GETCAPS (R) - Get Optional Feature Capabilities

  • Without defining byte (Format 1)

  • With defining byte 0x93

• RSTACT (R) - Target Reset Action

  • Direct Write (Format 2) supports defining bytes 0x0, 0x1 and 0x2

  • Direct Read (Format 3) supports defining bytes 0x81, 0x82, and 0x84 and returns 0xFF as recovery timing

• ENDXFER - Data Transfer Ending Procedure Control

CCCs That Update Registers Without Firmware Notification¶

The following CCCs autonomously update internal registers without generating an interrupt to notify firmware. Firmware should poll these registers if current values are needed:

Multi-Byte CCC Register Atomicity¶

Several Direct GET CCCs return multi-byte values. The CCC state machine transmits these byte-by-byte, selecting each byte from the source signal combinationally as it is needed. There is no snapshot or shadow register; the source is re-read on every byte. If the underlying CSR is modified mid-transfer, remaining bytes will reflect the new value while already-transmitted bytes retain the old value.

GETPID: The 48-bit PID is assembled combinationally from two CSR registers (STBY_CR_DEVICE_CHAR and STBY_CR_DEVICE_PID_LO). If firmware writes either register while a GETPID CCC is in progress, the byte being transmitted in that cycle and all subsequent bytes will use the new register value. Firmware should write both PID registers before the Target receives a dynamic address (before ENTDAA / SETDASA / SETAASA), since GETPID is only issued after address assignment.

GETMWL / GETMRL: These read internal flops that are only written by the SETMWL / SETMRL CCC handler. Since only one CCC can be active on the bus at a time, GET and SET cannot overlap. These registers are read-only to firmware (sw = r).

For SET CCCs, SETMRL commits MRL (bytes 0-1) and IBIL (byte 2) to STBY_CR_MRL on separate clock cycles. A firmware read of STBY_CR_MRL between those two updates sees the new MRL with the stale IBIL. SETMWL commits both MWL bytes to STBY_CR_MWL in a single cycle.

CCC Error Handling¶

The core detects errors during CCC processing:

• TE1: CCC command code parity error

• TE5: Wrong R/W direction for a Direct CCC (e.g., SET command with Read)

• Framing Error: SETDASA/SETNEWDA padding bit error (Bit[0] != 0)

These errors are reported through the TTI.TARGET_ERR_INTR_STATUS register and the TTI.STATUS.PROTOCOL_ERROR bit (readable via GETSTATUS CCC). See Error Detection and Recovery for full details.