Controller Interface Queues¶
Controller Interface queues consist of:
Command queue
The commands are fetched by the
hci
module from theCOMMAND_PORT
.
TX data queue
Data is fetched by the
hci
module from theXFER_DATA_PORT
.
RX data queue
Data is put to the
XFER_DATA_PORT
by thehci
module.
Response queue
Responses are retrieved from
i3c_ctrl
and put to theXFER_DATA_PORT
by thehci
module.
Controller Interface queues are depth-configurable with the I3C Configuration.
Queues generate several status indicators that will be used to trigger appropriate interrupts:
*_fifo_empty_
- no elements are enqueued in the corresponding FIFO.*_fifo_full_
-*_FIFO_DEPTH
are enqueued in the corresponding FIFO.*_fifo_apch_thld_
- the user-defined threshold has been reached.
Queue threshold¶
Command and response queue thresholds are controlled via the QUEUE_THLD_CTRL register. RX and TX data queue thresholds are controlled via DATA_BUFFER_THLD_CTRL.
Command queue threshold¶
The threshold for command queue is set by a write to the 8-bit
CMD_EMPTY_BUF_THLD
field of theQUEUE_THLD_CTRL
register.The
N
threshold of<1, 255>
range (inclusive) will cause anCMD_QUEUE_READY_STAT
interrupt when there’sN
or more remaining empty entries in the command queue.If the
N
value is greater than the size of the command queue (CMD_FIFO_DEPTH
), the full depth will be considered (the threshold will be set toCMD_FIFO_DEPTH
).
Response queue threshold¶
The threshold for response queue is set by a write to the 8-bit
RESP_BUF_THLD
field of theQUEUE_THLD_CTRL
register.The
N
threshold of<1, 255>
range (inclusive) will cause anRESP_READY_STAT
interrupt when there’sN
or more responses enqueued in the response queue.If the
N
value is greater or equal than the size of the response queue (RESP_FIFO_DEPTH
), the full depth will be considered (the threshold will be set toRESP_FIFO_DEPTH - 1
)
TX queue threshold¶
The threshold for the TX queue is set by a write to the 3-bit
TX_BUF_THLD
field of theDATA_BUFFER_THLD_CTRL
register.The
N
threshold of<0, 7>
range (inclusive) will trigger anTX_THLD_STAT
interrupt when2^(N+1)
(2
to the power ofN+1
) emptyDWORD
entries are available in the TX queue.The software must provide an
N
value that corresponds to the threshold less or equal thanTX_FIFO_DEPTH
, otherwiseclog2(TX_FIFO_DEPTH) - 1
will be applied.
RX queue threshold¶
The threshold for the RX queue is set by a write to the 3-bit
RX_BUF_THLD
field of theDATA_BUFFER_THLD_CTRL
register.The
N
threshold of<0, 7>
range (inclusive) will trigger anRX_THLD_STAT
interrupt when2^(N+1)
(2
to the power ofN+1
)DWORD
entries are enqueued in the RX queue.The software must provide an
N
value that corresponds to the threshold less thanRX_FIFO_DEPTH
, otherwiseclog2(RX_FIFO_DEPTH) - 2
will be applied.
All queues utilize the caliptra_prim_fifo_sync.sv FIFO implementation.