CHIPS Alliance Caliptra Open Source I3C core¶
- Introduction
- I3C Target overview
- I3C Controller overview
- Physical Layer
- I3C Common Command Codes (CCC)
- Error Detection and Recovery
- Firmware Integration Guide
- I3C Core Bring-Up Flow
- PIOControl Registers – Do Not Access
- In-Band Interrupt (IBI) Configuration
- Address Behavior and Priority
- RESET_CONTROL Register Limitations
- Max Read/Write Length (MRL/MWL)
- Private Writes During Recovery Flows
- Transmit FIFO Behavior on Controller Early Termination
- Unanticipated Private Reads
- Registers Updated by CCC Without Firmware Notification
- Routing Requirements
- Design verification
- Specification for I3C Vendor-Specific Extended Capabilities
- Recovery flow
- AXI Transaction ID Filtering
- AXI Recovery Flow
- Register descriptions
- I3C Timing Register Configurations
Last update:
2026-06-11