1. RISC-V VeeR EL2 Programmer’s Reference Manual¶

Revision: 1.4 December 22, 2022

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1.1. Document Revision History¶

Table 1.1 Revision History¶
Revision	Date	Contents
1.0	Jan 23, 2020	Changes: initial revision
1.1	Mar 4, 2020	Changes: added note that mscause values are subject to change (section Machine Secondary Cause Register (mscause)) added note that uninitialized DCCM may cause loads to get incorrect data (section Error Detection and Handling) added Debug Module reset description (section Debug Module Reset (dbg_rst_l)) updated port list (Table 16.1): added dbg_rst_l signal added footnote clarifying trace port signals fixed width of trace_rv_i_interrupt_ip bus added ‘Compliance Test Suite Failures’ chapter Compliance Test Suite Failures
1.2	Mar 29, 2020	Changes: fixed note how writing illegal value to mrac register is handled by hardware in Region Access Control Register (mrac) removed note that mscause values are subject to change in Machine Secondary Cause Register (mscause) updated mscause values (Table 3.10) added Internal Timers chapter and references throughout document incremented mimpid register value from ‘1’ to ‘2’ (Table 13.1)
1.3	Nov 16, 2020	Changes: updated versions of RISC-V Base ISA [1] and Privileged [2] and link to RISC-V Debug [3] specifications (Reference Documents) added RISC-V Bit-manipulation sub-extensions (Reference Documents, sections Features and Standard Extensions, and Table 8.1) added footnote that misaligned accesses to side-effect regions trigger a misaligned exception instead of the recommended access fault exception (Table 3.3) added note to mdseac register description clarifying captured address in D-Bus First Error Address Capture Register (mdseac) clarified that mscause value of ‘0’ indicates no additional information available (Machine Secondary Cause Register (mscause)) added description of SoC access expectation (Expected SoC Behavior for Accesses) added note that NMIs are fatal (Non-Maskable Interrupt (NMI) Signal and Vector) added note that mitcnt0/1 register is not cleared if write to it coincides with internal timer interrupt (Internal Timer Counter 0 / 1 Register (mitcnt0/1)) clarified note that debug single-step action is delayed while MPC debug halted (Power States) added cross-references to debug CSR descriptions (Table 6.2, Table 6.4, Table 13.2, and sections Count-Impacting Conditions and Core Complex Reset to Debug Mode) added note that debug single-stepping stays pending while MPC debug halted (Single Stepping) removed note that PMU halt or run request may not be acknowledged if already in requested activity state (Power Control and Status Signals) amended debug_mode_status signal description (Table 6.4) added note that mpc_debug_run_req is required to exit Debug Mode if entered after reset using mpc_reset_run_req (Multi-Core Debug Control and Status Signals) added PIC I/O power reduction feature description (sections Features, Power Reduction, and External Interrupt Pending Registers (meipX) and Table 11.2) added note that spurious interrupts may be captured for disabled external interrupts (Gateway) added note that edge-triggered interrupt lines must be tied off to inactive state (Gateway) fixed gateway initialization macro example (Example Interrupt Macros) added note that mtime and mtimecmp registers must be provided by SoC (Standard RISC-V Registers) changed value when writing unsupported event number to mhpmevent3-6 registers to ‘0’ (Events) added note that index field does not have WARL behavior (Table 9.1) added Debug Support chapter added ‘trace disable’ bit to mfdc register (Table 11.1) clarified effect of sepd bit of mfdc register (Table 11.1) added note regarding physical design considerations for rst_l signal (Core Complex Reset (rst_l)) updated ‘Reset to Debug-Mode’ description (Core Complex Reset to Debug Mode) updated trace port interrupt/exception signaling to new optimized scheme (Table 16.1) added erratum for abstract command register read capability (Debug Abstract Command Register May Return Non-Zero Value On Read) incremented mimpid register value from ‘2’ to ‘3’ (Table 13.1)
1.4	Apr 19, 2022	Changes: updated version and link of RISC-V Bit-manipulation [4] specification (Reference Documents) updated list of sub-extension instructions to RISC-V Bitmanip Extension specification version 0.94-draft (1/20/21) (Standard Extensions) updated note regarding priority of simultaneous store and non-blocking load bus errors (Imprecise Bus Error Non-Maskable Interrupt) fixed register name and added cross-reference (Footnote 20) added footnote that load/store access crossing upper boundary of DCCM or PIC memory range report base address of access in mtval register (Footnote 22) clarified that correctable error counter/threshold registers are always instantiated (sections I-Cache Error Counter/Threshold Register (micect), Iccm Correctable Error Counter/Threshold Register (miccmect), and Dccm Correctable Error Counter/Threshold Register (mdccmect)) corrected PIC I/O power reduction feature description (Power Reduction) incremented mimpid register value from ‘3’ to ‘4’ (Table 13.1)

1.2. Reference Documents¶

Table 1.2 Reference Documents¶
Item #	Document	Revision Used	Comment
1	The RISC-V Instruction Set Manual Volume I: User-Level ISA	20190608-Base-Ratified	Specification ratified
2	The RISC-V Instruction Set Manual Volume II: Privileged Architecture	20190608-Priv-MSU-Ratified	Specification ratified
2 (PLIC)	The RISC-V Instruction Set Manual Volume II: Privileged Architecture	1.11-draft December 1, 2018	Last specification version with PLIC chapter
3	RISC-V External Debug Support	0.13.2	Specification ratified
4	RISC-V Bitmanip Extension	0.94-draft (January 20, 2021)	Zba, Zbb, Zbc, and Zbs subextensions are “frozen”
5	The RISC-V Instruction Set Manual Volume II: Privileged Architecture	Document Version 20211203	Specification ratified
6	PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp)	Version 1.0, 12/2021	Specification ratified

1.3. Abbreviations¶

Table 1.3 Abbreviations¶
Abbreviation	Description
AHB	Advanced High-performance Bus (by ARM)
AMBA	Advanced Microcontroller Bus Architecture (by ARM)
ASIC	Application Specific Integrated Circuit
AXI	Advanced eXtensible Interface (by ARM)
CCM	Closely Coupled Memory (= TCM)
CPU	Central Processing Unit
CSR	Control and Status Register
DCCM	Data Closely Coupled Memory (= DTCM)
DEC	DECoder unit (part of core)
DMA	Direct Memory Access
DTCM	Data Tightly Coupled Memory (= DCCM)
ECC	Error Correcting Code
EXU	EXecution Unit (part of core)
ICCM	Instruction Closely Coupled Memory (= ITCM)
IFU	Instruction Fetch Unit
ITCM	Instruction Tightly Coupled Memory (= ICCM)
JTAG	Joint Test Action Group
LSU	Load/Store Unit (part of core)
MPC	Multi-Processor Controller
MPU	Memory Protection Unit
NMI	Non-Maskable Interrupt
PIC	Programmable Interrupt Controller
PLIC	Platform-Level Interrupt Controller
POR	Power-On Reset
RAM	Random Access Memory
RAS	Return Address Stack
ROM	Read-Only Memory
SECDED	Single-bit Error Correction/Double-bit Error Detection
SEDDED	Single-bit Error Detection/Double-bit Error Detection
SoC	System on Chip
TBD	To Be Determined
TCM	Tightly Coupled Memory (= CCM)

Last update: 2024-10-02