RISC-V VeeR EL2 Programmer's Reference Manual documentation

RISC-V VeeR EL2 Programmer’s Reference Manual

RISC-V VeeR EL2 Programmer’s Reference Manual¶

1. RISC-V VeeR EL2 Programmer’s Reference Manual
- 1.1. Document Revision History
- 1.2. Reference Documents
- 1.3. Abbreviations
2. Core Overview
- 2.1. Features
- 2.2. Core Complex
- 2.3. Functional Blocks
- 2.4. Standard Extensions
3. Memory Map
- 3.1. Address Regions
- 3.2. Access Properties
- 3.3. Memory Types
- 3.4. Memory Type Access Properties
- 3.5. Memory Access Ordering
- 3.6. Memory Protection
- 3.7. Exception Handling
- 3.8. Control/Status Registers
- 3.9. Memory Address Map
- 3.10. Behavior of Loads to Side-Effect Addresses
- 3.11. Partial Writes
- 3.12. Expected SoC Behavior for Accesses
- 3.13. Speculative Bus Accesses
- 3.14. DMA Slave Port
- 3.15. Reset Signal and Vector
- 3.16. Non-Maskable Interrupt (NMI) Signal and Vector
- 3.17. Software Interrupts
4. Memory Error Protection
- 4.1. General Description
- 4.2. Selecting the Proper Error Protection Level
- 4.3. Memory Hierarchy
- 4.4. Error Detection and Handling
- 4.5. Core Error Counter/Threshold Registers
5. Internal Timers
- 5.1. Features
- 5.2. Description
- 5.3. Internal Timer Local Interrupts
- 5.4. Control/Status Registers
6. Power Management and Multi-Core Debug Control
- 6.1. Features
- 6.2. Core Control Interfaces
- 6.3. Power States
- 6.4. Power Control
- 6.5. Control/Status Registers
7. External Interrupts
- 7.1. Features
- 7.2. Naming Convention
- 7.3. Overview of Major Functional Units
- 7.4. PIC Block Diagram
- 7.5. Theory Of Operation
- 7.6. Support for Vectored External Interrupts
- 7.7. Interrupt Chaining
- 7.8. Interrupt Nesting
- 7.9. Power Reduction
- 7.10. Performance Targets
- 7.11. Configurability
- 7.12. PIC Control/Status Registers
- 7.13. PIC CSR Address Map
- 7.14. PIC Memory-Mapped Register Address Map
- 7.15. Interrupt Enable/Disable Code Samples
8. Performance Monitoring
- 8.1. Features
- 8.2. Control/Status Registers
- 8.3. Counters
- 8.4. Count-Impacting Conditions
- 8.5. Events
9. Cache Control
- 9.1. Features
- 9.2. Feature Descriptions
- 9.3. Use Cases
- 9.4. Theory Of Operation
- 9.5. I-Cache Control/Status Registers
10. Debug Support
- 10.1. Control/Status Registers
11. Low-Level Core Control
- 11.1. Control/Status Registers
12. Standard RISC-V CSRs with Core-Specific Adaptations
- 12.1. Machine Interrupt Enable (mie) and Machine Interrupt Pending (mip) Registers
- 12.2. Machine Cause Register (mcause)
- 12.3. Machine Hardware Thread ID Register (mhartid)
13. CSR Address Map
- 13.1. Standard RISC-V CSRs
- 13.2. Non-Standard RISC-V CSRs
14. Interrupt Priorities
15. Clock And Reset
- 15.1. Features
- 15.2. Clocking
- 15.3. Reset
16. Complex Port List
17. Build Arguments
- 17.1. Memory Protection Build Arguments
- 17.2. Core Memory-Related Build Arguments
18. Compliance Test Suite Failures
- 18.1. I-MISALIGN_LDST-01
- 18.2. I-MISALIGN_JMP-01
- 18.3. I-FENCE.I-01 and fence_i
- 18.4. Breakpoint
19. Errata
- 19.1. Back-To-Back Write Transactions Not Supported on AHB-Lite Bus
- 19.2. Debug Abstract Command Register May Return Non-Zero Value On Read
20. Physical Memory Protection
- 20.1. Theory of Operation
- 20.2. Physical Memory Protection CSRs
- 20.3. Exceptions
- 20.4. PMP module
- 20.5. Verification
- 20.6. PMP check example
21. User Mode
- 21.1. Machine ISA Register (misa)
- 21.2. Machine Status Register (mstatus)
- 21.3. Machine Environment Configuration Registers (menvcfg,menvcfgh)
- 21.4. User Mode Performance Counters (cycle, cycleh, instret, instreth)
- 21.5. Machine Counter-Enable Register (mcounteren)
- 21.6. Machine Security Configuration Register (mseccfg, mseccfgh)
- 21.7. Privilege Mode Transitions and Exception Handling
- 21.8. PMP Enhancements for Memory Access and Execution Prevention on Machine Mode
22. Verification
- 22.1. RTL-level tests
- 22.2. Software execution tests
- 22.3. RISCV-DV verification
- 22.4. Verification coverage

Last update: 2024-08-29