RISC-V VeeR EL2 Programmer's Reference Manual documentation

RISC-V VeeR EL2 Programmer’s Reference Manual

RISC-V VeeR EL2 Programmer’s Reference Manual¶

1. RISC-V VeeR EL2 Programmer’s Reference Manual
- 1.1. Document Revision History
- 1.2. Reference Documents
- 1.3. Abbreviations
2. Core Overview
- 2.1. Features
- 2.2. Core Complex
- 2.3. Functional Blocks
- 2.4. Standard Extensions
3. Memory Map
- 3.1. Address Regions
- 3.2. Access Properties
- 3.3. Memory Types
- 3.4. Memory Type Access Properties
- 3.5. Memory Access Ordering
- 3.6. Memory Protection
- 3.7. Exception Handling
- 3.8. Control/Status Registers
- 3.9. Memory Address Map
- 3.10. Behavior of Loads to Side-Effect Addresses
- 3.11. Partial Writes
- 3.12. Expected SoC Behavior for Accesses
- 3.13. Speculative Bus Accesses
- 3.14. DMA Slave Port
- 3.15. Reset Signal and Vector
- 3.16. Non-Maskable Interrupt (NMI) Signal and Vector
- 3.17. Software Interrupts
4. Memory Error Protection
- 4.1. General Description
- 4.2. Selecting the Proper Error Protection Level
- 4.3. Memory Hierarchy
- 4.4. Error Detection and Handling
- 4.5. Core Error Counter/Threshold Registers
5. Dual-Core Lockstep (DCLS)
- 5.1. VeeR EL2 DCLS Overview
- 5.2. Shadow Core Control
- 5.3. Configuration
- 5.4. Validation Plan
6. Internal Timers
- 6.1. Features
- 6.2. Description
- 6.3. Internal Timer Local Interrupts
- 6.4. Control/Status Registers
7. Power Management and Multi-Core Debug Control
- 7.1. Features
- 7.2. Core Control Interfaces
- 7.3. Power States
- 7.4. Power Control
- 7.5. Control/Status Registers
8. External Interrupts
- 8.1. Features
- 8.2. Naming Convention
- 8.3. Overview of Major Functional Units
- 8.4. PIC Block Diagram
- 8.5. Theory Of Operation
- 8.6. Support for Vectored External Interrupts
- 8.7. Interrupt Chaining
- 8.8. Interrupt Nesting
- 8.9. Power Reduction
- 8.10. Performance Targets
- 8.11. Configurability
- 8.12. PIC Control/Status Registers
- 8.13. PIC CSR Address Map
- 8.14. PIC Memory-Mapped Register Address Map
- 8.15. Interrupt Enable/Disable Code Samples
9. Performance Monitoring
- 9.1. Features
- 9.2. Control/Status Registers
- 9.3. Counters
- 9.4. Count-Impacting Conditions
- 9.5. Events
10. Cache Control
- 10.1. Features
- 10.2. Feature Descriptions
- 10.3. Use Cases
- 10.4. Theory Of Operation
- 10.5. I-Cache Control/Status Registers
11. Debug Support
- 11.1. Control/Status Registers
12. Low-Level Core Control
- 12.1. Control/Status Registers
13. Standard RISC-V CSRs with Core-Specific Adaptations
- 13.1. Machine Interrupt Enable (mie) and Machine Interrupt Pending (mip) Registers
- 13.2. Machine Cause Register (mcause)
- 13.3. Machine Hardware Thread ID Register (mhartid)
14. CSR Address Map
- 14.1. Standard RISC-V CSRs
- 14.2. Non-Standard RISC-V CSRs
15. Interrupt Priorities
16. Clock And Reset
- 16.1. Features
- 16.2. Clocking
- 16.3. Reset
17. Complex Port List
18. Build Arguments
- 18.1. Memory Protection Build Arguments
- 18.2. Core Memory-Related Build Arguments
19. Compliance Test Suite Failures
- 19.1. I-MISALIGN_LDST-01
- 19.2. I-MISALIGN_JMP-01
- 19.3. I-FENCE.I-01 and fence_i
- 19.4. Breakpoint
20. Errata
- 20.1. Back-To-Back Write Transactions Not Supported on AHB-Lite Bus
- 20.2. Debug Abstract Command Register May Return Non-Zero Value On Read
21. Physical Memory Protection
- 21.1. Theory of Operation
- 21.2. Physical Memory Protection CSRs
- 21.3. Exceptions
- 21.4. PMP module
- 21.5. Verification
- 21.6. PMP check example
22. User Mode
- 22.1. Machine ISA Register (misa)
- 22.2. Machine Status Register (mstatus)
- 22.3. Machine Environment Configuration Registers (menvcfg,menvcfgh)
- 22.4. User Mode Performance Counters (cycle, cycleh, instret, instreth)
- 22.5. Machine Counter-Enable Register (mcounteren)
- 22.6. Machine Security Configuration Register (mseccfg, mseccfgh)
- 22.7. Privilege Mode Transitions and Exception Handling
- 22.8. PMP Enhancements for Memory Access and Execution Prevention on Machine Mode
23. Verification
- 23.1. RTL-level tests
- 23.2. Software execution tests
- 23.3. RISCV-DV verification
- 23.4. Verification coverage
24. Interactive Debugging in Simulation
- 24.1. Automation
25. Running Tock OS
- 25.1. Prerequisites
- 25.2. Fetching sources
- 25.3. Running simulation in Verilator
- 25.4. Running simulation in Verilator with applications

Last update: 2025-02-20