8. Performance Monitoring¶

This chapter describes the performance monitoring features of the VeeR EL2 core.

8.1. Features¶

VeeR EL2 provides these performance monitoring features:

• Four standard 64-bit wide event counters

• Standard separate event selection for each counter

• Standard selective count enable/disable controllability

• Standard synchronized counter enable/disable controllability

• Standard cycle counter

• Standard retired instructions counter

• Support for standard SoC-based machine timer registers

8.2. Control/Status Registers¶

8.2.1. Standard RISC-V Registers¶

A list of performance monitoring-related standard RISC-V CSRs with references to their definitions:

• Machine Hardware Performance Monitor (mcycle{|h}, minstret{|h}, mhpmcounter3{|h}- mhpmcounter31{|h}, and mhpmevent3-mhpmevent31) (see Section 3.1.11 in [2])

• Machine Counter-Inhibit Register [1] (mcountinhibit) (see Section 3.1.13 in [2])

• Machine Timer Registers (mtime and mtimecmp) (see Section 3.1.10 in [2])

8.3. Counters¶

Only event counters 3 to 6 (mhpmcounter3{|h}-mhpmcounter6{|h}) and their corresponding event selectors (mhpmevent3-mhpmevent6) are functional on VeeR EL2.

Event counters 7 to 31 (mhpmcounter7{|h}-mhpmcounter31{|h}) and their corresponding event selectors (mhpmevent7-mhpmevent31) are hardwired to ‘0’.

8.4. Count-Impacting Conditions¶

A few comments to consider on conditions that have an impact on the performance monitor counting:

• While in the pmu/fw-halt power management state, performance counters (including the mcycle counter) are disabled.

• While in debug halt (db-halt) state, the stopcount bit of the dcsr register (see Debug Control and Status Register (dcsr)) determines if performance counters are enabled.

• While in the pmu/fw-halt power management state or the debug halt (db-halt) state with the stopcount bit set, DMA accesses are allowed, but not counted by the performance counters. It would be up to the bus master to count accesses while the core is in a halt state.

• While executing PAUSE, performance counters are enabled.

Also, it is recommended that the performance counters are disabled (using the mcountinhibit register) before the counters and event selectors are modified, and then reenabled again. This minimizes the impact of reading and writing the counter and event selector CSRs on the event count values, specifically for the CSR read/write events (i.e., events #16 and #17). In general, performance counters are incremented after a read access to the counter CSRs, but before a write access to the counter CSRs.

8.5. Events¶

Table 8.1 provides a list of the countable events.