10. Debug Support¶

0x01

IDCODE

TAG IDCODE

IDCODE Register (IDCODE)

0x11

dmi

Debug module interface access

Debug Module Interface Access Register (dmi)

version

31:28

Identifies release version of this part

R

jtag_id[31:28] value

(see Complex Port List)

manufid

11:1

Identifies designer/manufacturer of this part

R

jtag_id[11:1] value

(see Complex Port List)

Reserved

31:18

Reserved

R

0

dmireset

16

Not implemented

Note: Reset of DTM’s error state not required in VeeR EL2 because DMI accesses always succeed. Writes to this bit ignored.

R

0

idle

14:12

Hint to debugger of minimum number of cycles debugger should spend in Run-Test/Idle after every DMI scan to avoid a ‘busy’ return code (dmistat of 3). Debugger must still check dmistat when necessary:

• 0: Not necessary to enter Run-Test/Idle at all.

Other values not implemented.

R

0

abits

9:4

Size of address field in dmi register (see Table 10.4)

R

7

address

40:34

Address used for DMI access. In Update-DR, value used to access DM over DMI.

R/W

0

op

1:0

For write:

• 0: Ignore data and address (nop)

• 1: Read from address (read)

• 2: Write data to address (write)

• 3: Not implemented (do not use)

For read:

• 0: Previous operation completed successfully

• 1..3: Not implemented (DMI accesses always succeed)

R/W

0

bypass

0

Bypass

-

0

0x04

data0

Abstract data 0

Abstract Data 0 / 1 Registers (data0/1)

0x10

dmcontrol

Debug module control

System Bus Address 31:0 Register (sbaddress0)

0x16

abstractcs

Abstract control and status

Abstract Control and Status Register (abstractcs)

0x18

abstractauto

Abstract command autoexec

Abstract Command Autoexec Register (abstractauto)

0x39

sbaddress0

System bus address 31:0

System Bus Address 31:0 Register (sbaddress0)

0x3D

sbdata1

System bus data 63:32

System Bus Data 63:32 Register (sbdata1)

haltreq

31

Halt request:

• 0: Clears halt request bit.

  Note: May cancel outstanding halt request.

• 1: Sets halt request bit.

  Note: Running hart halts whenever halt request bit is set.

R0/W

0

hartreset

29

Not implemented (i.e., 0: Deasserted)

R

0

Reserved

27

Reserved

R

0

hartsello

25:16

Not implemented (VeeR EL2 is single-thread)

R

0

Reserved

5:4

Reserved

R

0

clrresethaltreq

2

Not implemented

Note: hasresethaltreq bit in dmstatus register (Table 10.8) is ‘0’.

R

0

dmactive

0

Reset signal for Debug Module (DM):

• 0: Module’s state takes its reset values

  Note: Only dmactive bit may be written to value other than its reset value. Writes to all other bits of this register are ignored.

• 1: Module functions normally

  Debugger may pulse this bit low to get Debug Module into known state.

  Note: The core complex’s dbg_rst_l signal (see Complex Port List) resets the Debug Module. It should only be used to reset the Debug Module at power up or possibly with a global reset signal which resets the entire platform.

R/W

0

Reserved

31:23

Reserved

R

0

Reserved

21:20

Reserved

R

0

anyhavereset

18

‘1’ when hart has been reset and reset has not been acknowledged

R

-

anyresumeack

16

‘1’ when hart has acknowledged last resume request

R

-

anynonexistent

14

Not implemented (VeeR EL2 is single-thread)

R

0

anyunavail

12

‘1’ when hart is unavailable [1]

R

-

anyrunning

10

‘1’ when hart is running

R

-

anyhalted

8

‘1’ when hart is halted

R

-

authbusy

6

Not implemented (i.e., 0: Authentication module never busy)

R

0

confstrptrvalid

4

Not implemented

Note: VeeR EL2 does not provide information relevant to configuration string.

R

0

Reserved

31:1

Reserved

R

0

Reserved

31:29

Reserved

R

0

Reserved

23:13

Reserved

R

0

Reserved

11

Reserved

R

0

Reserved

7:4

Reserved

R

0

cmdtype

31:24

Abstract command type:

• 0: Access Register Command

• 2: Access Memory Command

Note: Other values not implemented or reserved for future use. Writing this field to value different than ‘0’ or ‘2’ causes abstract command to fail and cmderr field of abstractcs register to be set to ‘2’.

R0/W

0

Reserved

23

Reserved

R

0

aarpostincrement

19

Access register post-increment control:

• 0: No post-increment

• 1: After every successful access register command completion, increment regno field (wrapping around to 0)

R/W

0

transfer

17

Transfer:

• 0: Do not perform operation specified by write

  Note: Selection of unimplemented options (except for aarsize and regno fields) causes cmderr field of abstractcs register to be set to ‘2’.

• 1: Perform operation specified by write

  Note: Selection of unimplemented options causes abstract command to fail and cmderr field of abstractcs register to be set to ‘2’.

R

1

regno

15:0

Register access:

• 0x0000 - 0x0FFF: CSRs

• 0x1000 - 0x101F: GPRs

• 0x1020 - 0xFFFF: Not implemented or reserved

Note: Selecting illegal register address causes abstract command to fail and cmderr field of abstractcs register to be set to ‘3’, except if transfer is ‘0’.

R0/W

0

aamvirtual

23

Not implemented (i.e., 0: Addresses are physical)

Note: VeeR EL2 supports physical addresses only. Since physical and virtual address are identical, no error is flagged [2] even if written to ‘1’.

R

0

aampostincrement

19

Access memory post-increment control:

• 0: No post-increment

• 1: After every successful access memory command completion, increment data1 register (which contains memory address, see Abstract Data 0 / 1 Registers (data0/1)) by number of bytes encoded in aamsize field

R/W

0

write

16

Read or write memory location:

• 0 (read): Copy data from memory location specified in data1 register (i.e., address) into data0 register (i.e., data) (Abstract Data 0 / 1 Registers (data0/1))

• 1 (write): Copy data from data0 register (i.e., data) into memory location specified in data1 register (i.e., address) (Abstract Data 0 / 1 Registers (data0/1))

R0/W

0

Reserved

13:0

Reserved

R

0

Reserved

31:2

Reserved

R

0

autoexecdata0

0

Auto-execution control for data0 register:

• 0: No automatic triggering of abstract command execution

• 1: Reading or writing data0 causes abstract command to be executed again

R/W

0

data

31:0

Abstract command data:

• data0: data value (access register and access memory command)

• data1: address (access memory command)

R/W

0

sbversion

31:29

System Bus interface conforms to RISC-V Debug specification, Version 0.13.2

R

1

sbbusyerror

22

Set when debugger attempts to read data while a read is in progress, or when debugger initiates a new access while one is still in progress (i.e., while sbbusy bit is set). Remains set until explicitly cleared by debugger.

Note: When set, Debug Module cannot initiate more system bus accesses.

R/W1C

0

sbreadonaddr

20

Auto-read on address write:

• 0: No auto-read on address write

• 1: Every write to sbaddress0 (see System Bus Address 31:0 Register (sbaddress0)) automatically triggers system bus read at new address

R/W

0

sbautoincrement

16

Auto-address increment:

• 0: No auto-address increment

• 1: sbaddress0 register (see System Bus Address 31:0 Register (sbaddress0)) incremented by access size (in bytes) selected in sbaccess field after every successful system bus access

R/W

0

sberror

14:12

Set when Debug Module’s system bus master encounters an error: While this field is non-zero, no more system bus accesses can be initiated by the Debug Module.

• 0: No bus error

• 1: Not implemented (no timeout)

• 2: Bad address accessed

• 3: Alignment error

• 4: Access of unsupported size requested

• 5..7: Not implemented (no other error conditions)

Note: Bits in this field remain set until cleared by writing ‘111’.

Note: Debug Module may not initiate next system bus access until value is reset to ‘0’.

R/W1C

0

sbaccess128

4

128-bit system bus accesses not supported

R

0

sbaccess32

2

32-bit system bus accesses supported

R

1

sbaccess8

0

8-bit system bus accesses supported

R

1

address

31:0

System bus address

R/W

0

data

31:0

System bus data[31:0] for system bus read and write accesses

R/W

0

data

31:0

System bus data[63:32] for system bus read and write accesses

R/W

0

Reserved

31:2

Reserved

R

0

type

31:28

See Table 10.20 below.

R

2

data

26:0

See Table 10.20 below.

See Table 10.20 below.

See Table 10.20 below.

type

31:28

Address/data match trigger (= mcontrol)

R

2

maskmax

26:21

\(2^{31}\) bytes is largest naturally aligned powers-of-two (NAPOT) range supported by hardware when match field is ‘1’.

R

31

select

19

Match selection:

0: Perform match on address

1: Perform match on store data value

R/W

0

sizelo

17:16

Match size:

• 0: Trigger attempts to match against access of any size.

  • Match against address (if select bit is ‘0’)

  • Match against store data (if select bit is ‘1’)

  Note: Data is zero extended for byte or halfword stores.

  Note: If match bit is ‘1’, the mask in the tdata2 register is applied independent of the select bit value (i.e., in address or data matches).

  Note: Other match size values not implemented.

R

0

chain

11

Trigger chaining:

• 0: When this trigger matches, the configured action is taken.

• 1: While this trigger does not match, it prevents the trigger with the next index from matching.

Note: Supported for triggers 0 and 2 only, attempts to set this bit for triggers 1 and 3 are ignored.

Note: In VeeR EL2, only pairs of triggers (i.e., triggers 0/1 and triggers 2/3) are chainable.

Note: If chain bit of trigger 0/2 is ‘1’, it is chained to trigger 1/3. Only action field of trigger 1/3 is used (i.e., action field of trigger 0/2 is ignored). The action on second trigger is taken if and only if both triggers in chain match at the same time.

Note: Because the chain bit affects the next trigger, hardware resets it to ‘0’ for mcontrol register writes with dmode bit of ‘0’ if the next trigger has a dmode bit of ‘1’. In addition, hardware ignores writes to the mcontrol register which would set the dmode bit to ‘1’ if the previous trigger has both a dmode bit of ‘0’ and a chain bit of ‘1’. Debuggers must avoid the latter case by checking the chain bit of the previous trigger when writing the mcontrol register.

R/W (for triggers 0 and 2) R (for triggers 1 and 3)

0

m

6

When set, enable this trigger in M-mode

R/W

0

s

4

Not implemented

R

0

execute

2

When set, trigger fires on address of executed instruction

Note: For writes, written to ‘0’ if select bit is written to ‘1’.

R/W

0

load

0

When set, trigger fires on address of load

Note: For writes, written to ‘0’ if select bit is written to ‘1’.

R/W

0

value

31:0

Match value:

• Address or data value for match:

• Address of load, store, or executed instruction [4]

• Data value of store

• Match mask (see match field of mcontrol register (Table 10.20) set to ‘1’)

R/W

0

xdebugver

31:28

External debug support exists as described in this chapter and [3]

R

4

ebreakm

15

• 0: ebreak in M-mode behaves as described in RISC-V Privileged specification [2]

• 1: ebreak in M-mode enters Debug Mode

R/W

0

ebreaks

13

Not implemented

R

0

stepie

11

• 0: Interrupts disabled during single stepping

• 1: Interrupts enabled during single stepping

• Note: Debugger must not change value while hart is running.

R/W

0

stoptime

9

Increment timers same as in non-debug mode

R

0

Reserved

5

Reserved

R

0

nmip

3

Non-Maskable Interrupt (NMI) pending for hart when set

Note: NMI may indicate a hardware error condition, reliable debugging may no longer be possible once bit is set.

R

0

prv

1:0

Indicates privilege level hart was operating in when Debug Mode was entered (3 = M-mode)

R

3

dpc

31:0

Address captured for:

ebreak:

• Address of ebreak instruction

Single step:

• Address of instruction which would be executed next if not in Debug Mode (i.e., PC + 4 for 32-bit instructions which don’t change program flow, destination PC on taken jumps/branches, etc.)

Trigger module:

If timing (see timing bit in mcontrol register in Table 10.20) is:

• 0: Address of instruction which caused trigger to fire

• 1: Address of next instruction to be executed when Debug Mode was entered

Halt request:

• Address of next instruction to be executed when Debug Mode was entered

R/W

0