13. CSR Address Map¶

13.1. Standard RISC-V CSRs¶

Table 13.1 lists the VeeR EL2 core-specific standard RISC-V Machine Information CSRs.

Table 13.1 VeeR EL2 Core-Specific Standard RISC-V Machine Information CSRs¶
Number	Privilege	Name	Description	Value
0x301	MRW	misa	ISA and extensions Note: writes ignored	0x4000_1104
0xF11	MRO	mvendorid	Vendor ID	0x0000_0045
0xF12	MRO	marchid	Architecture ID	0x0000_0010
0xF13	MRO	mimpid	Implementation ID	0x0000_0004
0xF14	MRO	mhartid	Hardware thread ID	see Machine Hardware Thread ID Register (mhartid)

Table 13.2 lists the VeeR EL2 standard RISC-V CSR address map.

Table 13.2 VeeR EL2 Standard RISC-V CSR Address Map¶
Number	Privilege	Name	Description	Section
0x300	MRW	mstatus	Machine status	-
0x304	MRW	mie	Machine interrupt enable	Machine Interrupt Enable (mie) and Machine Interrupt Pending (mip) Registers
0x305	MRW	mtvec	Machine trap-handler base address	-
0x320	MRW	mcountinhibit	Machine counter-inhibit register	Standard RISC-V Registers
0x323	MRW	mhpmevent3	Machine performance-monitoring event selector 3	Standard RISC-V Registers
0x324	MRW	mhpmevent4	Machine performance-monitoring event selector 4	Standard RISC-V Registers
0x325	MRW	mhpmevent5	Machine performance-monitoring event selector 5	Standard RISC-V Registers
0x326	MRW	mhpmevent6	Machine performance-monitoring event selector 6	Standard RISC-V Registers
0x340	MRW	mscratch	Scratch register for machine trap handlers	-
0x341	MRW	mepc	Machine exception program counter	-
0x342	MRW	mcause	Machine trap cause	Machine Cause Register (mcause)
0x343	MRW	mtval	Machine bad address or instruction	-
0x344	MRW	mip	Machine interrupt pending	Machine Interrupt Enable (mie) and Machine Interrupt Pending (mip) Registers
0x7A0	MRW	tselect	Debug/Trace trigger register select	Trigger Select Register (tselect)
0x7A1	MRW	tdata1	First Debug/Trace trigger data	Trigger Data 1 Register (tdata1)
0x7A1	MRW	mcontrol	Match control	Match Control Register (mcontrol)
0x7A2	MRW	tdata2	Second Debug/Trace trigger data	Trigger Data 2 Register (tdata2)
0x7B0	DRW	dcsr	Debug control and status register	Debug Control and Status Register (dcsr)
0x7B1	DRW	dpc	Debug PC	Debug PC Register (dpc)
0xB00	MRW	mcycle	Machine cycle counter	Standard RISC-V Registers
0xB02	MRW	minstret	Machine instructions-retired counter	Standard RISC-V Registers
0xB03	MRW	mhpmcounter3	Machine performance-monitoring counter 3	Standard RISC-V Registers
0xB04	MRW	mhpmcounter4	Machine performance-monitoring counter 4	Standard RISC-V Registers
0xB05	MRW	mhpmcounter5	Machine performance-monitoring counter 5	Standard RISC-V Registers
0xB06	MRW	mhpmcounter6	Machine performance-monitoring counter 6	Standard RISC-V Registers
0xB80	MRW	mcycleh	Upper 32 bits of mcycle, RV32I only	Standard RISC-V Registers
0xB82	MRW	minstreth	Upper 32 bits of minstret, RV32I only	Standard RISC-V Registers
0xB83	MRW	mhpmcounter3h	Upper 32 bits of mhpmcounter3, RV32I only	Standard RISC-V Registers
0xB84	MRW	mhpmcounter4h	Upper 32 bits of mhpmcounter4, RV32I only	Standard RISC-V Registers
0xB85	MRW	mhpmcounter5h	Upper 32 bits of mhpmcounter5, RV32I only	Standard RISC-V Registers
0xB86	MRW	mhpmcounter6h	Upper 32 bits of mhpmcounter6, RV32I only	Standard RISC-V Registers

13.2. Non-Standard RISC-V CSRs¶

Table 13.3 summarizes the VeeR EL2 non-standard RISC-V CSR address map.

Table 13.3 VeeR EL2 Non-Standard RISC-V CSR Address Map¶
Number	Privilege	Name	Description	Section
0x7C0	MRW	mrac	Region access control	Region Access Control Register (mrac)
0x7C2	MRW	mcpc	Core pause control	Core Pause Control Register (mcpc)
0x7C4	DRW	dmst	Memory synchronization trigger (Debug Mode only)	Memory Synchronization Trigger Register (dmst)
0x7C6	MRW	mpmc	Power management control	Power Management Control Register (mpmc)
0x7C8	DRW	dicawics	I-cache array/way/index selection (Debug Mode only)	I-Cache Array/Way/Index Selection Register (dicawics)
0x7C9	DRW	dicad0	I-cache array data 0 (Debug Mode only)	I-Cache Array Data 0 Register (dicad0)
0x7CA	DRW	dicad1	I-cache array data 1 (Debug Mode only)	I-Cache Array Data 1 Register (dicad1)
0x7CB	DRW	dicago	I-cache array go (Debug Mode only)	I-Cache Array Go Register (dicago)
0x7CC	DRW	dicad0h	I-cache array data 0 high (Debug Mode only)	I-Cache Array Data 0 High Register (dicad0h)
0x7CE	MRW	mfdht	Force debug halt threshold	Forced Debug Halt Threshold Register (mfdht)
0x7CF	MRW	mfdhs	Force debug halt status	Forced Debug Halt Status Register (mfdhs)
0x7D2	MRW	mitcnt0	Internal timer counter 0	Internal Timer Counter 0 / 1 Register (mitcnt0/1)
0x7D3	MRW	mitb0	Internal timer bound 0	Internal Timer Bound 0 / 1 Register (mitb0/1)
0x7D4	MRW	mitctl0	Internal timer control 0	Internal Timer Control 0 / 1 Register (mitctl0/1)
0x7D5	MRW	mitcnt1	Internal timer counter 1	Internal Timer Counter 0 / 1 Register (mitcnt0/1)
0x7D6	MRW	mitb1	Internal timer bound 1	Internal Timer Bound 0 / 1 Register (mitb0/1)
0x7D7	MRW	mitctl1	Internal timer control 1	Internal Timer Control 0 / 1 Register (mitctl0/1)
0x7F0	MRW	micect	I-cache error counter/threshold	I-Cache Error Counter/Threshold Register (micect)
0x7F1	MRW	miccmect	ICCM correctable error counter/threshold	ICCM Correctable Error Counter/Threshold Register (miccmect)
0x7F2	MRW	mdccmect	DCCM correctable error counter/threshold	DCCM Correctable Error Counter/Threshold Register (mdccmect)
0x7F8	MRW	mcgc	Clock gating control	Clock Gating Control Register (mcgc)
0x7F9	MRW	mfdc	Feature disable control	Feature Disable Control Register (mfdc)
0x7FF	MRW	mscause	Machine secondary cause	Machine Secondary Cause Register (mscause)
0xBC0	MRW	mdeau	D-Bus error address unlock	D-Bus Error Address Unlock Register (mdeau)
0xBC8	MRW	meivt	External interrupt vector table	External Interrupt Vector Table Register (meivt)
0xBC9	MRW	meipt	External interrupt priority threshold	External Interrupt Priority Threshold Register (meipt)
0xBCA	MRW	meicpct	External interrupt claim ID / priority level capture trigger	External Interrupt Claim ID / Priority Level Capture Trigger Register (meicpct)
0xBCB	MRW	meicidpl	External interrupt claim ID’s priority level	External Interrupt Claim ID's Priority Level Register (meicidpl)
0xBCC	MRW	meicurpl	External interrupt current priority level	External Interrupt Current Priority Level Register (meicurpl)
0xFC0	MRO	mdseac	D-bus first error address capture	D-Bus First Error Address Capture Register (mdseac)
0xFC8	MRO	meihap	External interrupt handler address pointer	External Interrupt Handler Address Pointer Register (meihap)

Last update: 2024-10-02