12. Standard RISC-V CSRs with Core-Specific Adaptations¶

A summary of standard RISC-V control/status registers in CSR space with platform-specific adaptations:

• Machine Interrupt Enable (mie) and Machine Interrupt Pending (mip) Registers

• Machine Cause Register (mcause)

• Machine Hardware Thread ID Register (mhartid)

All reserved and unused bits in these control/status registers must be hardwired to ‘0’. Unless otherwise noted, all read/write control/status registers must have WARL (Write Any value, Read Legal value) behavior.

12.1. Machine Interrupt Enable (mie) and Machine Interrupt Pending (mip) Registers¶

The standard RISC-V mie and mip registers hold the machine interrupt enable and interrupt pending bits, respectively. Since VeeR EL2 only supports machine and user mode, all supervisor-specific bits are not implemented. In addition, the mie/mip registers also host the platform-specific local interrupt enable/pending bits (shown with a gray background in Table 12.1 and Table 12.2 below).

The mie register is a standard read/write CSR.

The mip register is a standard read/write CSR.

12.2. Machine Cause Register (mcause)¶

The standard RISC-V mcause register indicates the cause for a trap as shown in Table 12.3, including standard exceptions/interrupts, platform-specific local interrupts (with light gray background), and NMI causes (with dark gray background).

Additional trap information is provided in the mscause register, see Machine Secondary Cause Register (mscause) which allows the determination of the exact cause of a trap for cases where multiple, different conditions share a single trap code.

The mcause register has WLRL (Write Legal value, Read Legal value) behavior.

This register is a standard read/write CSR.

12.3. Machine Hardware Thread ID Register (mhartid)¶

The standard RISC-V mhartid register provides the integer ID of the hardware thread running the code. Hart IDs must be unique. Hart IDs might not necessarily be numbered contiguously in a multiprocessor system, but at least one hart must have a hart ID of zero.

The mhartid register is split into two fixed-sized fields. The SoC must provide a hardwired core ID on the core_id[31:4] bus. The value provided on that bus sources the mhartid register’s coreid field. If the SoC hosts more than one RISC-V core, each core must have its own unique core_id value. Each hardware thread of the core has a unique, hardwired thread ID which is reflected in the mhartid register’s hartid field starting at 0x0 up to 0xF.

VeeR EL2 implements a single hardware thread with thread ID 0x0.

This register is a standard read-only CSR.