Name Implemented tests Planned tests Implementation progress Passing runs Total runs Pass Rate
bus_monitor 1 1100% 1 1100%
bus_rx_flow 2 2100% 2 2100%
bus_timers 1 1100% 1 1100%
bus_tx 5 5100% 19 19100%
bus_tx_flow 5 5100% 9 9100%
ccc 1 1100% 1 1100%
controller_axi_filtering 18 18100% 0 180.0%
csr_sw_access 6 6100% 0 60.0%
hci_queues 0 200.0% 0 0 --%
descriptor_rx 1 1100% 1 1100%
descriptor_tx 1 1100% 1 1100%
drivers 0 10.0% 0 0 --%
edge_detector 6 6100% 6 6100%
i3c_bus_monitor 2 2100% 2 2100%
pec 1 1100% 1 1100%
target_axi_filtering 19 19100% 19 19100%
tti_queues 13 13100% 13 13100%
width_converter_8toN 2 2100% 2 2100%
width_converter_Nto8 2 2100% 2 2100%

Progress of stages

Stage Implemented tests Planned tests Implementation progress Passing runs Total runs Pass Rate
N.A. 86 10780.4% 80 10476.9%