| controller_axi_filtering_disabled | read_hci_version_csr_id_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_off | 0 | 0 | 0 | 1 | 0.0% |
| controller_axi_filtering_priv | read_hci_version_csr_id_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_on_priv | 0 | 0 | 0 | 1 | 0.0% |
| controller_axi_filtering_non_priv | read_hci_version_csr_id_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | read_pio_section_offset_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_to_controller_device_addr_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | write_should_not_affect_ro_csr_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_read_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | sequence_csr_write_filter_on_non_priv | 0 | 0 | 0 | 1 | 0.0% |
| | TOTAL | | | 0 | 18 | 0.0% |