verible-verilog-lint
Tool for linting Verilog and SystemVerilog code. Part of the Verible tool suite.
verible-verilog-lint: usage: /tmp/verible-bin/verible-verilog-lint [options] <file> [<file>...]
Flags from external/com_google_absl/absl/flags/parse.cc:
--flagfile (comma-separated list of files to load flags from); default: ;
--fromenv (comma-separated list of flags to set from the environment [use
'export FLAGS_flag1=value']); default: ;
--tryfromenv (comma-separated list of flags to try to set from the
environment if present); default: ;
--undefok (comma-separated list of flag names that it is okay to specify on
the command line even if the program does not define a flag with that
name); default: ;
Flags from verible/verilog/analysis/verilog-linter.cc:
--rules (Comma-separated of lint rules to enable. No prefix or a '+' prefix
enables it, '-' disable it. Configuration values for each rules placed
after '=' character.); default: ;
--rules_config (Path to lint rules configuration file. Disables
--rule_config_search if set.); default: "";
--rules_config_search (Look for lint rules configuration file
'.rules.verible_lint' searching upward from the location of each analyzed
file.); default: false;
--ruleset ([default|all|none], the base set of rules used by linter);
default: default;
--waiver_files (Path to waiver config files (comma-separated). Please refer
to the README file for information about its format.); default: "";
Flags from verible/verilog/parser/verilog-parser.cc:
--verilog_trace_parser (Trace verilog parser); default: false;
Flags from verible/verilog/tools/lint/verilog-lint.cc:
--autofix (autofix mode; one of
[no|patch-interactive|patch|inplace-interactive|inplace|generate-waiver]);
default: no;
--autofix_output_file (File to write a patch with autofixes to if
--autofix=patch or --autofix=patch-interactive or a waiver file if
--autofix=generate-waiver); default: "";
--check_syntax (If true, check for lexical and syntax errors, otherwise
ignore.); default: true;
--generate_markdown (If true, print the description of every rule formatted
for the Markdown and exit immediately. Intended for the output to be
written to a snippet of Markdown.); default: false;
--help_rules ([all|<rule-name>], print the description of one rule/all rules
and exit immediately.); default: "";
--lint_fatal (If true, exit nonzero if linter finds violations.);
default: true;
--parse_fatal (If true, exit nonzero if there are any syntax errors.);
default: true;
--print_rules_file (Print the current set of lint rules in a format that can
be used to create a lint rules configuration file (i.e.
.rules.verible_lint) and exit immediately.); default: false;
--show_diagnostic_context (prints an additional line on which the diagnostic
was found,followed by a line with a position marker); default: false;
Try --helpfull to get a list of all flags or --help=substring shows help for
flags which include specified substring in either in the name, or description or
path.
Checks that there are no occurrences of always @*
. Use always_comb
instead. See [Style: combinational-logic].
Enabled by default: true
Checks that there are no occurrences of non-blocking assignment in combinational logic. See [Style: combinational-logic].
Enabled by default: true
Checks that blocking assignments are, at most, targeting locals in sequential logic. See [Style: sequential-logic].
catch_modifying_assignments
Default: false
waive_for_locals
Default: false
Enabled by default: true
Checks for banned declared name against set of unwanted patterns. See [Style: identifiers].
Enabled by default: false
Checks that a default case-item is always defined unless the case statement has the unique
qualifier. See [Style: case-statements].
Enabled by default: true
Check that constraint names follow the required name style specified by a regular expression. See [Style: constraints].
pattern
Default: ([a-z0-9]+_)+c
Enabled by default: true
Checks that the ‘name’ argument of type_id::create()
matches the name of the variable to which it is assigned. See [Style: uvm-naming].
Enabled by default: true
Checks that D Flip-Flops use appropiate naming conventions in both input and output ports. The left hand side (output) and right hand side (input) are checked against a set of valid suffixes. Additionally, register names might end in a number to denote the pipeline stage index (var_q/var_q1, var_q2, …). Pipelined signals must get their value from the previous stage: var_q3 <= var_q2. Exceptions to this rule can be configured using a regular expression or waiving whole if
blocks See [Style: dff-name-style].
input
Default: next,n,d
Comma separated list of allowed suffixes for the input port. Suffixes should not include the preceding “_”. Empty field means no checks for the input portoutput
Default: reg,r,ff,q
Comma separated list of allowed suffixes for the output port. Should not include the preceding “_”. Empty field means no checks for the output portwaive_ifs_with_conditions
Default: !rst_ni,flush_i,!rst_ni || flush_i,flush_i || !rst_ni
Comma separated list of conditions that will disable the rule inside the if
s they are evaluated inwaive_lhs_regex
Default: (?i)mem.*
Nonblocking assigments whose lhs match the regex will not be evaluatedEnabled by default: false
Checks that there are no occurrences of disable some_label
if label is referring to a fork or other none sequential block label. Use disable fork
instead. See [Style: disable-invalid-in-non-sequential].
Enabled by default: false
Checks that a Verilog `endif
directive is followed by a comment that matches the name of the opening `ifdef
or `ifndef
. See [Style: endif-comment].
Enabled by default: false
Checks that enum type names follow a naming convention defined by a RE2 regular expression. The default regex pattern expects “lower_snake_case” with either a “_t” or “_e” suffix. Refer to https://github.com/chipsalliance/verible/tree/master/verilog/tools/lint#readme for more detail on verible regex patterns. See [Style: enumerations].
style_regex
Default: [a-z_0-9]+(_t|_e)
A regex used to check enum type name style.Enabled by default: true
Checks that a Verilog begin
directive follows all if, else, always, always_comb, always_latch, always_ff, for, forever, foreach, while and initial statements. See [Style: explicit-begin].
if_enable
Default: true
All if statements require an explicit begin-end blockelse_enable
Default: true
All else statements require an explicit begin-end blockalways_enable
Default: true
All always statements require an explicit begin-end blockalways_comb_enable
Default: true
All always_comb statements require an explicit begin-end blockalways_latch_enable
Default: true
All always_latch statements require an explicit begin-end blockalways_ff_enable
Default: true
All always_ff statements require an explicit begin-end blockfor_enable
Default: true
All for statements require an explicit begin-end blockforever_enable
Default: true
All forever statements require an explicit begin-end blockforeach_enable
Default: true
All foreach statements require an explicit begin-end blockwhile_enable
Default: true
All while statements require an explicit begin-end blockinitial_enable
Default: true
All initial statements require an explicit begin-end blockEnabled by default: false
Checks that every function declared outside of a class is declared with an explicit lifetime (static or automatic). See [Style: function-task-explicit-lifetime].
Enabled by default: true
Checks that every function and task parameter is declared with an explicit storage type. See [Style: function-task-argument-types].
Enabled by default: true
Checks that every parameter
and localparam
is declared with an explicit storage type. See [Style: constants].
exempt_type
Default: `` Set to string
to exempt string typesEnabled by default: true
Checks that every task declared outside of a class is declared with an explicit lifetime (static or automatic). See [Style: function-task-explicit-lifetime].
Enabled by default: true
Checks that there are no occurrences of consecutive null statements like ;;
See [Style: redundant-semicolons].
Enabled by default: true
Do not use defparam. See [Style: module-instantiation].
Enabled by default: true
Checks that there are no occurrences of \
when breaking the string literal line. Use concatenation operator with braces instead. See [Style: forbid-line-continuations].
Enabled by default: true
Check for negative constant literals inside array dimensions. See [Style: forbid-negative-array-dim].
Enabled by default: false
Checks that no forbidden macro calls are used. See [Style: uvm-logging].
Enabled by default: true
Checks that every generate block statement is labeled. See [Style: generate-statements].
Enabled by default: true
Checks that every generate block label starts with g_ or gen_. See [Style: generate-constructs].
Enabled by default: true
Warns if there are multiple declarations in the same scope that shadow each other with the same name. See [Style: mark-shadowed-instances].
Enabled by default: false
Checks that ‘interface’ names follow a naming convention defined by a RE2 regular expression. The default regex pattern expects “lower_snake_case” with a “_if” or “_e” suffix. Refer to https://github.com/chipsalliance/verible/tree/master/verilog/tools/lint#readme for more detail on regex patterns. See [Style: interface-conventions].
style_regex
Default: [a-z_0-9]+(_if)
A regex used to check interface name style.Enabled by default: true
Checks that no forbidden system tasks or functions are used. These consist of the following functions: $psprintf
, $random
, and $dist_*
. As well as non-LRM function $srandom
. See [Style: forbidden-system-functions].
Enabled by default: true
Checks that there are no generate regions. See [Style: generate-constructs].
Enabled by default: false
Checks that there are no separate genvar
declarations. See [Style: generate-constructs].
Enabled by default: false
Checks that all lines do not exceed the maximum allowed length. See [Style: line-length].
length
Default: 100
Desired line lengthEnabled by default: true
Checks that macro names conform to a naming convention defined by a RE2 regular expression. The default regex pattern expects “UPPER_SNAKE_CASE”. Exceptions are made for UVM like macros, where macros named ‘uvm_’ and ‘UVM_’ follow “lower_snake_case” and “UPPER_SNAKE_CASE” naming conventions respectively. Refer to https://github.com/chipsalliance/verible/tree/master/verilog/tools/lint#readme for more detail on verible regex patterns. See [Style: defines].
style_regex
Default: [A-Z_0-9]+
A regex used to check macro names style.Enabled by default: true
Concatenation will not be evaluated here. Use "...
” instead. See [Style: defines].
Enabled by default: false
Check for matching begin/end labels. See [Style: mismatched-labels].
Enabled by default: false
Checks that there are no begin-end blocks declared at the module level. See [Style: floating-begin-end-blocks].
Enabled by default: true
If a module is declared, checks that at least one module matches the first dot-delimited component of the file name. Depending on configuration, it is also allowed to replace underscore with dashes in filenames. See [Style: file-names].
allow-dash-for-underscore
Default: false
Allow dashes in the filename where there are dashes in the module nameEnabled by default: true
Checks that module instantiations with more than one parameter are passed in as named parameters, rather than positional parameters. See [Style: module-instantiation].
Enabled by default: true
Checks that module instantiations with more than one port are passed in as named ports, rather than positional ports. See [Style: module-instantiation].
Enabled by default: true
Checks that no tabs are used. Spaces should be used instead of tabs. See [Style: tabs].
Enabled by default: true
Checks that there are no trailing spaces on any lines. See [Style: trailing-spaces].
Enabled by default: true
Checks that string literals with numeric format specifiers have proper prefixes for hex and bin values and no prefixes for decimal values. See [Style: number-formatting].
Enabled by default: false
Checks that at most one module is declared per file. See [Style: file-extensions].
Enabled by default: false
Checks that the package name matches the filename. Depending on configuration, it is also allowed to replace underscore with dashes in filenames. See [Style: file-names].
allow-dash-for-underscore
Default: false
Allow dashes in the filename corresponding to the underscores in the packageEnabled by default: true
Checks that packed dimension ranges are declare in little-endian (decreasing) order, e.g. [N-1:0]
. See [Style: packed-ordering].
Enabled by default: true
Checks that parameter and localparm names conform to a naming convention based on a choice of ‘CamelCase’, ‘ALL_CAPS’ and a user defined regex ORed together. Empty configurtaion: no style enforcement. Refer to https://github.com/chipsalliance/verible/tree/master/verilog/tools/lint#readme for more detail on verible regex patterns. See [Style: constants].
localparam_style
Default: CamelCase
Style of localparam namesparameter_style
Default: CamelCase|ALL_CAPS
Style of parameter names.localparam_style_regex
Default: `` A regex used to check localparam name style.parameter_style_regex
Default: `` A regex used to check parameter name style.Enabled by default: true
Checks that parameter type names follow the lower_snake_case naming convention and end with _t. See [Style: parametrized-objects].
Enabled by default: false
Checks that plusargs are always assigned a value, by ensuring that plusargs are never accessed using the $test$plusargs
system task. See [Style: plusarg-value-assignment].
Enabled by default: true
Check that port names end with _i for inputs, _o for outputs and _io for inouts. Alternatively, for active-low signals use _n[io], for differential pairs use _n[io] and _p[io]. See [Style: suffixes-for-signals-and-types].
Enabled by default: false
Checks that no parameter name starts with ‘disable’, using positive naming (starting with ‘enable’) is recommended. See [Style: binary-parameters].
Enabled by default: true
Checks that the file ends with a newline. See [Style: posix-file-endings].
Enabled by default: true
Checks that every parameter
declaration is inside a formal parameter list of modules/classes and every localparam
declaration is inside a module, class or package. See [Style: constants].
package_allow_parameter
Default: false
Allow parameters in packages (treated as a synonym for localparam).package_allow_localparam
Default: true
Allow localparams in packages.Enabled by default: false
Checks that signal names conform to a naming convention defined by a RE2 regular expression. Signals are defined as “a net, variable, or port within a SystemVerilog design”. The default regex pattern expects “lower_snake_case”. Refer to https://github.com/chipsalliance/verible/tree/master/verilog/tools/lint#readme for more detail on verible regex patterns. See [Style: signal-conventions].
style_regex
Default: [a-z_0-9]+
A regex used to check signal names style.Enabled by default: false
Checks that struct
and union
names use lower_snake_case naming convention and end with ‘_t’. See [Style: struct-union-conventions].
exceptions
Default: `` Comma separated list of allowed upper-case elements, such as unit-namesEnabled by default: true
Recommend extra parentheses around subexpressions where it helps readability. See [Style: parentheses].
Enabled by default: true
Checks that there are no suspicious semicolons that might affect code behaviour but escape quick visual inspection See [Style: bugprone].
Enabled by default: false
Checks that numeric literals are not longer than their stated bit-width to avoid undesired accidental truncation. See [Style: number-literals].
Enabled by default: true
Checks that a Verilog enum
declaration is named using typedef
. See [Style: typedef-enums].
Enabled by default: true
Checks that a Verilog struct
or union
declaration is named using typedef
. See [Style: typedef-structs-unions].
allow_anonymous_nested
Default: false
Allow nested structs/unions to be anonymous.Enabled by default: true
Checks that the digits of binary literals for the configured bases match their declared width, i.e. has enough padding prefix zeros. See [Style: number-literals].
bin
Default: true
Checking binary ‘b literals.oct
Default: false
Checking octal ‘o literals.hex
Default: false
Checking hexadecimal ‘h literals.lint_zero
Default: false
Also generate a lint warning for value zero such as 32'h0
; autofix suggestions would be to zero-expand or untype '0
.autofix
Default: true
Provide autofix suggestions, e.g. 32’hAB provides suggested fix 32’h000000AB.Enabled by default: true
Checks that unpacked dimension ranges are declared in big-endian order [0:N-1]
, and when an unpacked dimension range is zero-based [0:N-1]
, the size is declared as [N]
instead. See [Style: unpacked-ordering].
Enabled by default: true
Checks that no `uvm_* macro calls end with ‘;’. See [Style: uvm-macro-semicolon-convention].
Enabled by default: false
Checks that there are no generate-begin blocks inside a generate region. See [Style: generate-constructs].
Enabled by default: true
Checks that void casts do not contain certain function/method calls. See [Style: void-casts].
Enabled by default: true
Generated on 2024-12-01 22:55:50 -0800 from 936dfb1