System architecture¶

Block diagram¶

The following diagram illustrates the key components and interconnections of the Guineveer SoC:

The Guineveer reference System-on-Chip (SoC) design employs the VeeR EL2 core which is a 32-bit CPU supporting RISC-V’s extensions for integer (I), compressed instruction (C), multiplication and division (M), and instruction-fetch fence, CSR, and subset of bit manipulation instructions (Z).

The reference design features an AXI system bus which is used to communicate with several peripherals, including an SRAM memory module (accessed via an AXI_to_mem interface), an I3C core, and an AXI-to-AHB bridge (providing access to an OpenTitan UART peripheral). There are two VeeR cores, each having its own memory and connection to the AXI interconnect.

The SoC is split into two clock domains: one for the I3C core, and one for the rest of the SoC. On FPGA targets, the I3C core is clocked at 160 MHz, while the rest of the SoC is clocked at 32 MHz.

The entire SoC is described in Topwrap/design.yaml, which contains connections, parameters, and modules used in the top module that will be generated by Topwrap.

Currently used peripherals and components¶

Peripheral and component configuration¶

VeeR EL2¶

The VeeR EL2 core is configured with FPGA optimizations enabled; branch predictor, ICCM, DCCM, and I-cache disabled. The full set of configuration options used is found in the root Makefile.

I3C¶

The I3C core uses mostly its default configuration, with one notable difference: the input sync flip-flops are enabled, which is necessary for FPGAs to prevent glitches.

Memory map¶

The table below summarizes the Guineveer memory address map, including the start, end, and size for the various component types.