I3C Core - documentation¶

• Introduction

Hardware Design and Verification

• Overview
  • Top level
  • Legacy I2C Mode
• Controller Interfaces
  • Control and Status Registers
  • System Bus
  • Host Controller Interface (HCI)
• Standby Controller
  • Standby Controller
• Physical Layer
  • PHY
  • Common PHY Layer
• Design verification
  • Verification plan
• Controller Interface Queues
  • Queue threshold
• Electrical and timing specifications
  • Clock speed and oversampling
  • Open-drain vs Push-pull configuration
  • Rise and fall times
  • Timing control registers

Programmer's Reference Manual

• Boot and Initialization
  • Boot
  • Primary Controller Initialization
  • Secondary Controller Initialization
  • Minimal configuration
• Normal operation
  • Data transfers
  • In-band interrupts (IBI) handling
  • Interrupts
  • Address Assignment
  • Linux Kernel

Extended Capabilities and Recovery Flow

• Specification for I3C Vendor-Specific Extended Capabilities
  • Security
  • Extended Capabilities
  • Vendor-specific Extended Capabilities
  • Ideas for the future (informative)
• Recovery flow
  • Recovery handler
  • CSR access via I3C
  • Recovery handler operation

Integrating the I3C Core

• Configuring the I3C Core
• Integration with Caliptra Subsystem
  • Caliptra Subsystem
  • Controller Interface test
  • Interrupts
  • Target Device Provisioned ID
• FPGA Validation Platform
  • Devices
  • Test procedure