Changes to Registers

Comparing version 2.1 to 2.0
+921 additions -203 deletions
@@ -1,5 +1,5 @@
11 <div style="font-size: 0.85em; color: #656d76; margin-bottom: 1em; padding: 0.5em; background: #f6f8fa; border-radius: 4px;">
2-📄 Source: <a href="https://github.com/chipsalliance/i3c-core/blob/aae3424a8ecbd4edb7a60e23f76421de2d891712/doc/source/registers.md" target="_blank">chipsalliance/i3c-core/doc/source/registers.md</a> @ <code>aae3424</code>
2+📄 Source: <a href="https://github.com/chipsalliance/i3c-core/blob/bb79ebd9b487c61cd1bea1aec2574ae4740f104d/doc/source/registers.md" target="_blank">chipsalliance/i3c-core/doc/source/registers.md</a> @ <code>bb79ebd</code>
33 </div>
44
55 # Register descriptions
@@ -1084,16 +1084,16 @@
10841084
10851085 - Absolute Address: 0x100
10861086 - Base Offset: 0x100
1087-- Size: 0x16C
1087+- Size: 0x274
10881088
10891089 |Offset| Identifier | Name |
10901090 |------|-------------------------|----------------------------------|
10911091 | 0x000| SecFwRecoveryIf |Secure Firmware Recovery Interface|
10921092 | 0x080| StdbyCtrlMode | Standby Controller Mode |
1093-| 0x0C0| TTI | Target Transaction Interface |
1094-| 0x100| SoCMgmtIf | SoC Management Interface |
1095-| 0x160| CtrlCfg | Controller Config |
1096-| 0x168|TERMINATION_EXTCAP_HEADER| — |
1093+| 0x100| TTI | Target Transaction Interface |
1094+| 0x200| SoCMgmtIf | SoC Management Interface |
1095+| 0x268| CtrlCfg | Controller Config |
1096+| 0x270|TERMINATION_EXTCAP_HEADER| — |
10971097
10981098 ## SecFwRecoveryIf register file
10991099
@@ -1947,26 +1947,27 @@
19471947
19481948 - Absolute Address: 0x180
19491949 - Base Offset: 0x80
1950-- Size: 0x40
1951-
1952-|Offset| Identifier | Name |
1953-|------|--------------------------------|-------------------------------------------------|
1954-| 0x00 | EXTCAP_HEADER | — |
1955-| 0x04 | STBY_CR_CONTROL | Standby Controller Control |
1956-| 0x08 | STBY_CR_DEVICE_ADDR | Standby Controller Device Address |
1957-| 0x0C | STBY_CR_CAPABILITIES | Standby Controller Capabilities |
1958-| 0x10 | STBY_CR_VIRTUAL_DEVICE_CHAR |Standby Controller Virtual Device Characteristics|
1959-| 0x14 | STBY_CR_STATUS | Standby Controller Status |
1960-| 0x18 | STBY_CR_DEVICE_CHAR | Standby Controller Device Characteristics |
1961-| 0x1C | STBY_CR_DEVICE_PID_LO | Standby Controller Device PID Low |
1962-| 0x20 | STBY_CR_INTR_STATUS | Standby Controller Interrupt Status |
1963-| 0x24 | STBY_CR_VIRTUAL_DEVICE_PID_LO | Standby Controller Virtual Device PID Low |
1964-| 0x28 | STBY_CR_INTR_SIGNAL_ENABLE | Standby Controller Interrupt Signal Enable |
1965-| 0x2C | STBY_CR_INTR_FORCE | Standby Controller Interrupt Force |
1966-| 0x30 | STBY_CR_CCC_CONFIG_GETCAPS | Standby Controller CCC Configuration GETCAPS |
1967-| 0x34 |STBY_CR_CCC_CONFIG_RSTACT_PARAMS| Standby Controller CCC Configuration RSTACT |
1968-| 0x38 | STBY_CR_VIRT_DEVICE_ADDR | Standby Virtual Controller Device Address |
1969-| 0x3C | __rsvd_3 | Reserved 3 |
1950+- Size: 0x44
1951+
1952+|Offset| Identifier | Name |
1953+|------|--------------------------------|-----------------------------------------------------------------------|
1954+| 0x00 | EXTCAP_HEADER | — |
1955+| 0x04 | STBY_CR_CONTROL | Standby Controller Control |
1956+| 0x08 | STBY_CR_DEVICE_ADDR | Standby Controller Device Address |
1957+| 0x0C | STBY_CR_CAPABILITIES | Standby Controller Capabilities |
1958+| 0x10 | STBY_CR_VIRTUAL_DEVICE_CHAR | Standby Controller Virtual Device Characteristics |
1959+| 0x14 | STBY_CR_STATUS | Standby Controller Status |
1960+| 0x18 | STBY_CR_DEVICE_CHAR | Standby Controller Device Characteristics |
1961+| 0x1C | STBY_CR_DEVICE_PID_LO | Standby Controller Device PID Low |
1962+| 0x20 | STBY_CR_INTR_STATUS | Standby Controller Interrupt Status |
1963+| 0x24 | STBY_CR_VIRTUAL_DEVICE_PID_LO | Standby Controller Virtual Device PID Low |
1964+| 0x28 | STBY_CR_INTR_SIGNAL_ENABLE | Standby Controller Interrupt Signal Enable |
1965+| 0x2C | STBY_CR_INTR_FORCE | Standby Controller Interrupt Force |
1966+| 0x30 | STBY_CR_CCC_CONFIG_GETCAPS | Standby Controller CCC Configuration GETCAPS |
1967+| 0x34 |STBY_CR_CCC_CONFIG_RSTACT_PARAMS| Standby Controller CCC Configuration RSTACT |
1968+| 0x38 | STBY_CR_VIRT_DEVICE_ADDR | Standby Virtual Controller Device Address |
1969+| 0x3C | STBY_CR_MWL | Standby Controller Maximum Write Length (read-only) |
1970+| 0x40 | STBY_CR_MRL |Standby Controller Maximum Read Length and IBI Payload Size (read-only)|
19701971
19711972 ### EXTCAP_HEADER register
19721973
@@ -1977,7 +1978,7 @@
19771978 |Bits|Identifier|Access|Reset| Name |
19781979 |----|----------|------|-----|----------|
19791980 | 7:0| CAP_ID | r | 0x12| CAP_ID |
1980-|23:8|CAP_LENGTH| r | 0x10|CAP_LENGTH|
1981+|23:8|CAP_LENGTH| r | 0x20|CAP_LENGTH|
19811982
19821983 #### CAP_ID field
19831984
@@ -1997,10 +1998,10 @@
19971998
19981999 | Bits| Identifier | Access |Reset| Name |
19992000 |-----|---------------------|--------|-----|--------------------------------------------------|
2000-| 0 | PENDING_RX_NACK | rw | — | Pending RX NACK |
2001-| 1 | HANDOFF_DELAY_NACK | rw | — | Handoff Delay NACK |
2002-| 2 | ACR_FSM_OP_SELECT | rw | — | Active Controller Select |
2003-| 3 |PRIME_ACCEPT_GETACCCR| rw | — | Prime to Accept Controller Role |
2001+| 0 | PENDING_RX_NACK | rw | 0x0 | Pending RX NACK |
2002+| 1 | HANDOFF_DELAY_NACK | rw | 0x0 | Handoff Delay NACK |
2003+| 2 | ACR_FSM_OP_SELECT | rw | 0x0 | Active Controller Select |
2004+| 3 |PRIME_ACCEPT_GETACCCR| rw | 0x0 | Prime to Accept Controller Role |
20042005 | 4 | HANDOFF_DEEP_SLEEP |rw, wset| 0x0 | Handoff Deep Sleep |
20052006 | 5 | CR_REQUEST_SEND | w | 0x0 | Send Controller Role Request |
20062007 | 10:8| BAST_CCC_IBI_RING | rw | 0x0 |Ring Bundle IBI Selector for Broadcast CCC Capture|
@@ -2179,7 +2180,7 @@
21792180 |-----|----------|------|------|---------|
21802181 | 15:1| PID_HI | rw |0x7FFF| PID_HI |
21812182 |23:16| DCR | rw | 0xBD | DCR |
2182-|28:24| BCR_VAR | rw | 0x16 | BCR_VAR |
2183+|28:24| BCR_VAR | rw | 0x10 | BCR_VAR |
21832184 |31:29| BCR_FIXED| rw | 0x1 |BCR_FIXED|
21842185
21852186 #### PID_HI field
@@ -2193,7 +2194,7 @@
21932194 #### BCR_VAR field
21942195
21952196 <p>Bus Characteristics, Variable Part.</p>
2196-<p>Reset value is set to 5'b10110, because this device:</p>
2197+<p>Reset value is set to 5'b10000, because this device:</p>
21972198 <ul>
21982199 <li>
21992200 <p>[bit4] is a Virtual Target</p>
@@ -2202,10 +2203,10 @@
22022203 <p>[bit3] is not Offline Capable</p>
22032204 </li>
22042205 <li>
2205-<p>[bit2] uses the MDB in the IBI Payload</p>
2206-</li>
2207-<li>
2208-<p>[bit1] is capable of IBI requests</p>
2206+<p>[bit2] does not apply due to bit1</p>
2207+</li>
2208+<li>
2209+<p>[bit1] is not capable of IBI requests</p>
22092210 </li>
22102211 <li>
22112212 <p>[bit0] has no speed limitation</p>
@@ -2228,9 +2229,9 @@
22282229
22292230 |Bits| Identifier |Access|Reset| Name |
22302231 |----|-----------------|------|-----|-----------------|
2231-| 2 | AC_CURRENT_OWN | rw | — | AC_CURRENT_OWN |
2232-| 7:5|SIMPLE_CRR_STATUS| rw | — |SIMPLE_CRR_STATUS|
2233-| 8 | HJ_REQ_STATUS | rw | — | HJ_REQ_STATUS |
2232+| 2 | AC_CURRENT_OWN | rw | 0x0 | AC_CURRENT_OWN |
2233+| 7:5|SIMPLE_CRR_STATUS| rw | 0x0 |SIMPLE_CRR_STATUS|
2234+| 8 | HJ_REQ_STATUS | rw | 0x0 | HJ_REQ_STATUS |
22342235
22352236 #### AC_CURRENT_OWN field
22362237
@@ -2256,7 +2257,7 @@
22562257 |-----|----------|------|------|---------|
22572258 | 15:1| PID_HI | rw |0x7FFF| PID_HI |
22582259 |23:16| DCR | rw | 0xBD | DCR |
2259-|28:24| BCR_VAR | rw | 0x6 | BCR_VAR |
2260+|28:24| BCR_VAR | rw | 0x16 | BCR_VAR |
22602261 |31:29| BCR_FIXED| rw | 0x1 |BCR_FIXED|
22612262
22622263 #### PID_HI field
@@ -2270,16 +2271,16 @@
22702271 #### BCR_VAR field
22712272
22722273 <p>Bus Characteristics, Variable Part.</p>
2273-<p>Reset value is set to 5'b00110, because this device:</p>
2274+<p>Reset value is set to 5'b10110, because this device:</p>
22742275 <ul>
22752276 <li>
2276-<p>[bit4] is not a Virtual Target</p>
2277+<p>[bit4] exposes a Virtual Target</p>
22772278 </li>
22782279 <li>
22792280 <p>[bit3] is not Offline Capable</p>
22802281 </li>
22812282 <li>
2282-<p>[bit2] uses the MDB in the IBI Payload</p>
2283+<p>[bit2] (always) uses the MDB in the IBI Payload</p>
22832284 </li>
22842285 <li>
22852286 <p>[bit1] is capable of IBI requests</p>
@@ -2321,19 +2322,19 @@
23212322
23222323 |Bits| Identifier |Access|Reset| Name |
23232324 |----|--------------------------|------|-----|-------------------------------------------|
2324-| 0 |ACR_HANDOFF_OK_REMAIN_STAT| rw | — | |
2325-| 1 |ACR_HANDOFF_OK_PRIMED_STAT| rw | — | |
2326-| 2 | ACR_HANDOFF_ERR_FAIL_STAT| rw | — | |
2327-| 3 | ACR_HANDOFF_ERR_M3_STAT | rw | — | |
2328-| 10 | CRR_RESPONSE_STAT | rw | — | |
2329-| 11 | STBY_CR_DYN_ADDR_STAT | rw | — | |
2330-| 12 |STBY_CR_ACCEPT_NACKED_STAT| rw | — | |
2331-| 13 | STBY_CR_ACCEPT_OK_STAT | rw | — | |
2332-| 14 | STBY_CR_ACCEPT_ERR_STAT | rw | — | |
2325+| 0 |ACR_HANDOFF_OK_REMAIN_STAT| rw | 0x0 | |
2326+| 1 |ACR_HANDOFF_OK_PRIMED_STAT| rw | 0x0 | |
2327+| 2 | ACR_HANDOFF_ERR_FAIL_STAT| rw | 0x0 | |
2328+| 3 | ACR_HANDOFF_ERR_M3_STAT | rw | 0x0 | |
2329+| 10 | CRR_RESPONSE_STAT | rw | 0x0 | |
2330+| 11 | STBY_CR_DYN_ADDR_STAT | rw | 0x0 | |
2331+| 12 |STBY_CR_ACCEPT_NACKED_STAT| rw | 0x0 | |
2332+| 13 | STBY_CR_ACCEPT_OK_STAT | rw | 0x0 | |
2333+| 14 | STBY_CR_ACCEPT_ERR_STAT | rw | 0x0 | |
23332334 | 16 | STBY_CR_OP_RSTACT_STAT | rw | 0x0 |Secondary Controller Operation Reset Action|
2334-| 17 | CCC_PARAM_MODIFIED_STAT | rw | — | |
2335-| 18 | CCC_UNHANDLED_NACK_STAT | rw | — | |
2336-| 19 | CCC_FATAL_RSTDAA_ERR_STAT| rw | — | |
2335+| 17 | CCC_PARAM_MODIFIED_STAT | rw | 0x0 | |
2336+| 18 | CCC_UNHANDLED_NACK_STAT | rw | 0x0 | |
2337+| 19 | CCC_FATAL_RSTDAA_ERR_STAT| rw | 0x0 | |
23372338
23382339 #### ACR_HANDOFF_OK_REMAIN_STAT field
23392340
@@ -2416,19 +2417,19 @@
24162417
24172418 |Bits| Identifier |Access|Reset|Name|
24182419 |----|-------------------------------|------|-----|----|
2419-| 0 |ACR_HANDOFF_OK_REMAIN_SIGNAL_EN| rw | — | |
2420-| 1 |ACR_HANDOFF_OK_PRIMED_SIGNAL_EN| rw | — | |
2421-| 2 | ACR_HANDOFF_ERR_FAIL_SIGNAL_EN| rw | — | |
2422-| 3 | ACR_HANDOFF_ERR_M3_SIGNAL_EN | rw | — | |
2423-| 10 | CRR_RESPONSE_SIGNAL_EN | rw | — | |
2424-| 11 | STBY_CR_DYN_ADDR_SIGNAL_EN | rw | — | |
2425-| 12 |STBY_CR_ACCEPT_NACKED_SIGNAL_EN| rw | — | |
2426-| 13 | STBY_CR_ACCEPT_OK_SIGNAL_EN | rw | — | |
2427-| 14 | STBY_CR_ACCEPT_ERR_SIGNAL_EN | rw | — | |
2420+| 0 |ACR_HANDOFF_OK_REMAIN_SIGNAL_EN| rw | 0x0 | |
2421+| 1 |ACR_HANDOFF_OK_PRIMED_SIGNAL_EN| rw | 0x0 | |
2422+| 2 | ACR_HANDOFF_ERR_FAIL_SIGNAL_EN| rw | 0x0 | |
2423+| 3 | ACR_HANDOFF_ERR_M3_SIGNAL_EN | rw | 0x0 | |
2424+| 10 | CRR_RESPONSE_SIGNAL_EN | rw | 0x0 | |
2425+| 11 | STBY_CR_DYN_ADDR_SIGNAL_EN | rw | 0x0 | |
2426+| 12 |STBY_CR_ACCEPT_NACKED_SIGNAL_EN| rw | 0x0 | |
2427+| 13 | STBY_CR_ACCEPT_OK_SIGNAL_EN | rw | 0x0 | |
2428+| 14 | STBY_CR_ACCEPT_ERR_SIGNAL_EN | rw | 0x0 | |
24282429 | 16 | STBY_CR_OP_RSTACT_SIGNAL_EN | rw | 0x0 | |
2429-| 17 | CCC_PARAM_MODIFIED_SIGNAL_EN | rw | — | |
2430-| 18 | CCC_UNHANDLED_NACK_SIGNAL_EN | rw | — | |
2431-| 19 | CCC_FATAL_RSTDAA_ERR_SIGNAL_EN| rw | — | |
2430+| 17 | CCC_PARAM_MODIFIED_SIGNAL_EN | rw | 0x0 | |
2431+| 18 | CCC_UNHANDLED_NACK_SIGNAL_EN | rw | 0x0 | |
2432+| 19 | CCC_FATAL_RSTDAA_ERR_SIGNAL_EN| rw | 0x0 | |
24322433
24332434 #### ACR_HANDOFF_OK_REMAIN_SIGNAL_EN field
24342435
@@ -2494,15 +2495,15 @@
24942495
24952496 |Bits| Identifier |Access|Reset|Name|
24962497 |----|---------------------------|------|-----|----|
2497-| 10 | CRR_RESPONSE_FORCE | rw | — | |
2498-| 11 | STBY_CR_DYN_ADDR_FORCE | rw | — | |
2499-| 12 |STBY_CR_ACCEPT_NACKED_FORCE| rw | — | |
2500-| 13 | STBY_CR_ACCEPT_OK_FORCE | rw | — | |
2501-| 14 | STBY_CR_ACCEPT_ERR_FORCE | rw | — | |
2502-| 16 | STBY_CR_OP_RSTACT_FORCE | w | — | |
2503-| 17 | CCC_PARAM_MODIFIED_FORCE | rw | — | |
2504-| 18 | CCC_UNHANDLED_NACK_FORCE | rw | — | |
2505-| 19 | CCC_FATAL_RSTDAA_ERR_FORCE| rw | — | |
2498+| 10 | CRR_RESPONSE_FORCE | rw | 0x0 | |
2499+| 11 | STBY_CR_DYN_ADDR_FORCE | rw | 0x0 | |
2500+| 12 |STBY_CR_ACCEPT_NACKED_FORCE| rw | 0x0 | |
2501+| 13 | STBY_CR_ACCEPT_OK_FORCE | rw | 0x0 | |
2502+| 14 | STBY_CR_ACCEPT_ERR_FORCE | rw | 0x0 | |
2503+| 16 | STBY_CR_OP_RSTACT_FORCE | w | 0x0 | |
2504+| 17 | CCC_PARAM_MODIFIED_FORCE | rw | 0x0 | |
2505+| 18 | CCC_UNHANDLED_NACK_FORCE | rw | 0x0 | |
2506+| 19 | CCC_FATAL_RSTDAA_ERR_FORCE| rw | 0x0 | |
25062507
25072508 #### CRR_RESPONSE_FORCE field
25082509
@@ -2550,8 +2551,8 @@
25502551
25512552 |Bits| Identifier |Access|Reset|Name|
25522553 |----|----------------------|------|-----|----|
2553-| 2:0| F2_CRCAP1_BUS_CONFIG | rw | — | |
2554-|11:8|F2_CRCAP2_DEV_INTERACT| rw | — | |
2554+| 2:0| F2_CRCAP1_BUS_CONFIG | rw | 0x0 | |
2555+|11:8|F2_CRCAP2_DEV_INTERACT| rw | 0x0 | |
25552556
25562557 #### F2_CRCAP1_BUS_CONFIG field
25572558
@@ -2571,14 +2572,14 @@
25712572
25722573 | Bits| Identifier |Access|Reset| Name |
25732574 |-----|---------------------|------|-----|----------------------------------------|
2574-| 7:0 | RST_ACTION | r | 0x0 | Defining Byte of the RSTACT CCC |
2575+| 7:0 | RST_ACTION | r | 0x1 | Defining Byte of the RSTACT CCC |
25752576 | 15:8|RESET_TIME_PERIPHERAL| rw | 0x0 | Time to Reset Peripheral |
25762577 |23:16| RESET_TIME_TARGET | rw | 0x0 | Time to Reset Target |
25772578 | 31 | RESET_DYNAMIC_ADDR | rw | 0x1 |Reset Dynamic Address after Target Reset|
25782579
25792580 #### RST_ACTION field
25802581
2581-<p>Contains the Defining Byte received with the last Direct SET CCC sent by the Active Controller.</p>
2582+<p>Contains the Defining Byte received with the last Direct SET CCC sent by the Active Controller. If not armed (START or RSTACT with unsupported defining byte) set to spec default 0x1.</p>
25822583
25832584 #### RESET_TIME_PERIPHERAL field
25842585
@@ -2636,7 +2637,7 @@
26362637 1'b0: VIRT_DYNAMIC_ADDR field is not valid
26372638 1'b1: VIRT_DYNAMIC_ADDR field is valid</p>
26382639
2639-### __rsvd_3 register
2640+### STBY_CR_MWL register
26402641
26412642 - Absolute Address: 0x1BC
26422643 - Base Offset: 0x3C
@@ -2644,49 +2645,91 @@
26442645
26452646
26462647
2647-|Bits|Identifier|Access|Reset| Name |
2648-|----|----------|------|-----|--------|
2649-|31:0| __rsvd | rw | — |Reserved|
2650-
2651-#### __rsvd field
2652-
2653-
2648+|Bits|Identifier|Access|Reset| Name |
2649+|----|----------|------|-----|--------------------|
2650+|15:0| MWL | r |0x100|Maximum Write Length|
2651+
2652+#### MWL field
2653+
2654+<p>This field contains the maximum write length (MWL) (read-only)</p>
2655+
2656+### STBY_CR_MRL register
2657+
2658+- Absolute Address: 0x1C0
2659+- Base Offset: 0x40
2660+- Size: 0x4
2661+
2662+
2663+
2664+| Bits|Identifier|Access|Reset| Name |
2665+|-----|----------|------|-----|-------------------|
2666+| 15:0| MRL | r |0x100|Maximum Read Length|
2667+|23:16| IBIL | r | 0x10| IBI Payload Size |
2668+
2669+#### MRL field
2670+
2671+<p>This field contains the maximum read length (MRL) (read-only)</p>
2672+
2673+#### IBIL field
2674+
2675+<p>This field contains the IBI payload size (IBIL) (read-only)</p>
26542676
26552677 ## TTI register file
26562678
2657-- Absolute Address: 0x1C0
2658-- Base Offset: 0xC0
2659-- Size: 0x40
2660-
2661-|Offset| Identifier | Name |
2662-|------|---------------------|-------------------------------|
2663-| 0x00 | EXTCAP_HEADER | — |
2664-| 0x04 | CONTROL | TTI Control |
2665-| 0x08 | STATUS | TTI Status |
2666-| 0x0C | RESET_CONTROL | TTI Queue Reset Control |
2667-| 0x10 | INTERRUPT_STATUS | TTI Interrupt Status |
2668-| 0x14 | INTERRUPT_ENABLE | TTI Interrupt Enable |
2669-| 0x18 | INTERRUPT_FORCE | TTI Interrupt Force |
2670-| 0x1C | RX_DESC_QUEUE_PORT | TTI RX Descriptor Queue Port |
2671-| 0x20 | RX_DATA_PORT | TTI RX Data Port |
2672-| 0x24 | TX_DESC_QUEUE_PORT | TTI TX Descriptor Queue Port |
2673-| 0x28 | TX_DATA_PORT | TTI TX Data Port |
2674-| 0x2C | IBI_PORT | TTI IBI Data Port |
2675-| 0x30 | QUEUE_SIZE | TTI Queue Size |
2676-| 0x34 | IBI_QUEUE_SIZE | TTI IBI Queue Size |
2677-| 0x38 | QUEUE_THLD_CTRL | TTI Queue Threshold Control |
2678-| 0x3C |DATA_BUFFER_THLD_CTRL|TTI IBI Queue Threshold Control|
2679+- Absolute Address: 0x200
2680+- Base Offset: 0x100
2681+- Size: 0x94
2682+
2683+|Offset| Identifier | Name |
2684+|------|----------------------------------------|-------------------------------------------------------|
2685+| 0x00 | EXTCAP_HEADER | — |
2686+| 0x04 | CONTROL | TTI Control |
2687+| 0x08 | STATUS | TTI Status |
2688+| 0x0C | RESET_CONTROL | TTI Reset Control |
2689+| 0x10 | QUEUE_STATUS | TTI Queue Status |
2690+| 0x14 | DESC_QUEUE_DEPTH | TTI Descriptor Queue Depth |
2691+| 0x18 | DATA_QUEUE_DEPTH | TTI Data Queue Depth |
2692+| 0x1C | IBI_QUEUE_DEPTH | TTI IBI Queue Depth |
2693+| 0x20 | INTERRUPT_STATUS | TTI Interrupt Status |
2694+| 0x24 | INTERRUPT_ENABLE | TTI Interrupt Enable |
2695+| 0x28 | INTERRUPT_FORCE | TTI Interrupt Force |
2696+| 0x2C | TARGET_ERR_CTRL | TTI Target Error Detection Control |
2697+| 0x30 | TARGET_ERR_INTR_STATUS | TTI Target Error Interrupt Status |
2698+| 0x34 | TARGET_ERR_INTR_ENABLE | TTI Target Error Interrupt Enable |
2699+| 0x38 | TARGET_ERR_INTR_FORCE | TTI Target Error Interrupt Force |
2700+| 0x3C | TARGET_ERR_CNT_TE0 | TE0 Error Counter |
2701+| 0x40 | TARGET_ERR_CNT_TE1 | TE1 Error Counter |
2702+| 0x44 | TARGET_ERR_CNT_TE2 | TE2 Error Counter |
2703+| 0x48 | TARGET_ERR_CNT_TE3 | TE3 Error Counter |
2704+| 0x4C | TARGET_ERR_CNT_TE4 | TE4 Error Counter |
2705+| 0x50 | TARGET_ERR_CNT_TE5 | TE5 Error Counter |
2706+| 0x54 | TARGET_ERR_CNT_FRAMING | Framing Error Counter |
2707+| 0x58 | TARGET_ERR_CNT_RI_PEC | Recovery Interface PEC Error Counter |
2708+| 0x5C | TARGET_ERR_CNT_RI_LENGTH | Recovery Interface Length Error Counter |
2709+| 0x60 | TARGET_ERR_CNT_RI_READONLY | Recovery Interface Read-Only Error Counter |
2710+| 0x64 | TARGET_ERR_CNT_RI_UNSUPPORTED | Recovery Interface Unsupported Error Counter |
2711+| 0x68 | TARGET_ERR_CNT_RI_RX_FIFO_OVERFLOW | Recovery Interface RX FIFO Overflow Error Counter |
2712+| 0x6C |TARGET_ERR_CNT_RI_INDIRECT_FIFO_OVERFLOW|Recovery Interface INDIRECT FIFO Overflow Error Counter|
2713+| 0x70 | RX_DESC_QUEUE_PORT | TTI RX Descriptor Queue Port |
2714+| 0x74 | RX_DATA_PORT | TTI RX Data Port |
2715+| 0x78 | TX_DESC_QUEUE_PORT | TTI TX Descriptor Queue Port |
2716+| 0x7C | TX_DATA_PORT | TTI TX Data Port |
2717+| 0x80 | IBI_PORT | TTI IBI Data Port |
2718+| 0x84 | QUEUE_SIZE | TTI Queue Size |
2719+| 0x88 | IBI_QUEUE_SIZE | TTI IBI Queue Size |
2720+| 0x8C | QUEUE_THLD_CTRL | TTI Queue Threshold Control |
2721+| 0x90 | DATA_BUFFER_THLD_CTRL | TTI IBI Queue Threshold Control |
26792722
26802723 ### EXTCAP_HEADER register
26812724
2682-- Absolute Address: 0x1C0
2725+- Absolute Address: 0x200
26832726 - Base Offset: 0x0
26842727 - Size: 0x4
26852728
26862729 |Bits|Identifier|Access|Reset| Name |
26872730 |----|----------|------|-----|----------|
26882731 | 7:0| CAP_ID | r | 0xC4| CAP_ID |
2689-|23:8|CAP_LENGTH| r | 0x10|CAP_LENGTH|
2732+|23:8|CAP_LENGTH| r | 0x40|CAP_LENGTH|
26902733
26912734 #### CAP_ID field
26922735
@@ -2698,7 +2741,7 @@
26982741
26992742 ### CONTROL register
27002743
2701-- Absolute Address: 0x1C4
2744+- Absolute Address: 0x204
27022745 - Base Offset: 0x4
27032746 - Size: 0x4
27042747
@@ -2743,7 +2786,7 @@
27432786
27442787 ### STATUS register
27452788
2746-- Absolute Address: 0x1C8
2789+- Absolute Address: 0x208
27472790 - Base Offset: 0x8
27482791 - Size: 0x4
27492792
@@ -2751,8 +2794,8 @@
27512794
27522795 | Bits| Identifier |Access|Reset| Name |
27532796 |-----|---------------|------|-----|---------------|
2754-| 13 | PROTOCOL_ERROR| r | 0x0 | PROTOCOL_ERROR|
2755-|15:14|LAST_IBI_STATUS| r | 0x0 |LAST_IBI_STATUS|
2797+| 8 | PROTOCOL_ERROR| r | 0x0 | PROTOCOL_ERROR|
2798+|14:12|LAST_IBI_STATUS| r | 0x0 |LAST_IBI_STATUS|
27562799
27572800 #### PROTOCOL_ERROR field
27582801
@@ -2767,29 +2810,34 @@
27672810
27682811 <p>Status of last IBI. Should be read after IBI_DONE interrupt.</p>
27692812 <p>Values:</p>
2770-<p>00 - Success: IBI was transmitted and ACK'd by the Active Controller.
2771-01 - Failure: Active Controller NACK'd the IBI before any data was sent.
2772-The Target Device will retry sending the IBI once.
2773-10 - Failure: Active Controller NACK'd the IBI after partial data was sent.
2774-Part of data in the IBI queue is considered corrupted and will be discarded.
2775-11 - Failure: IBI was terminated after 1 retry.</p>
2813+<p>000 - Success: IBI was transmitted and ACK'd by the Active Controller.
2814+001 - FailureNack: Active Controller NACK'd the IBI before any data was sent.
2815+The device will retry sending the IBI as long as permitted by the retry counter.
2816+010 - FailurePartialData: Active Controller NACK'd the IBI after data was
2817+partially sent. The remaining part of data in the IBI queue is considered
2818+corrupted and will be discarded.
2819+011 - FailureRetry: IBI could not be serviced due to reached retry count.
2820+100 - FailureArbitration:: IBI could not be serviced as arbitration was lost
2821+during the address header. The device will retry sending the IBI as long as
2822+permitted by the retry counter.</p>
27762823
27772824 ### RESET_CONTROL register
27782825
2779-- Absolute Address: 0x1CC
2826+- Absolute Address: 0x20C
27802827 - Base Offset: 0xC
27812828 - Size: 0x4
27822829
2783-<p>Queue Reset Control</p>
2784-
2785-|Bits| Identifier |Access|Reset| Name |
2786-|----|-------------|------|-----|-------------|
2787-| 0 | SOFT_RST | rw | 0x0 | SOFT_RST |
2788-| 1 | TX_DESC_RST | rw | 0x0 | TX_DESC_RST |
2789-| 2 | RX_DESC_RST | rw | 0x0 | RX_DESC_RST |
2790-| 3 | TX_DATA_RST | rw | 0x0 | TX_DATA_RST |
2791-| 4 | RX_DATA_RST | rw | 0x0 | RX_DATA_RST |
2792-| 5 |IBI_QUEUE_RST| rw | 0x0 |IBI_QUEUE_RST|
2830+<p>Reset Control for Queues and IBI Retry Counter</p>
2831+
2832+|Bits| Identifier |Access|Reset| Name |
2833+|----|-----------------|------|-----|-----------------|
2834+| 0 | SOFT_RST | rw | 0x0 | SOFT_RST |
2835+| 1 | TX_DESC_RST | rw | 0x0 | TX_DESC_RST |
2836+| 2 | RX_DESC_RST | rw | 0x0 | RX_DESC_RST |
2837+| 3 | TX_DATA_RST | rw | 0x0 | TX_DATA_RST |
2838+| 4 | RX_DATA_RST | rw | 0x0 | RX_DATA_RST |
2839+| 5 | IBI_QUEUE_RST | rw | 0x0 | IBI_QUEUE_RST |
2840+| 6 |IBI_RETRY_CTR_RST| w | 0x0 |IBI_RETRY_CTR_RST|
27932841
27942842 #### SOFT_RST field
27952843
@@ -2805,7 +2853,7 @@
28052853
28062854 #### TX_DATA_RST field
28072855
2808-<p>TTI TX Data Queue Buffer Software Reset</p>
2856+<p>TTI TX Data Queue Buffer Software Reset. Also resets the tti_conv_Nto8 since first dword is immediately loaded into the converter and can't be cleared otherwise.</p>
28092857
28102858 #### RX_DATA_RST field
28112859
@@ -2815,10 +2863,133 @@
28152863
28162864 <p>TTI IBI Queue Buffer Software Reset</p>
28172865
2866+#### IBI_RETRY_CTR_RST field
2867+
2868+<p>TTI IBI Retry Counter Software Reset</p>
2869+
2870+### QUEUE_STATUS register
2871+
2872+- Absolute Address: 0x210
2873+- Base Offset: 0x10
2874+- Size: 0x4
2875+
2876+<p>Dynamic queue full/empty status for debug and monitoring</p>
2877+
2878+|Bits| Identifier |Access|Reset| Name |
2879+|----|-------------------|------|-----|-------------------|
2880+| 0 | RX_DESC_QUEUE_FULL| r | 0x0 | RX_DESC_QUEUE_FULL|
2881+| 1 |RX_DESC_QUEUE_EMPTY| r | 0x1 |RX_DESC_QUEUE_EMPTY|
2882+| 2 | TX_DESC_QUEUE_FULL| r | 0x0 | TX_DESC_QUEUE_FULL|
2883+| 3 |TX_DESC_QUEUE_EMPTY| r | 0x1 |TX_DESC_QUEUE_EMPTY|
2884+| 4 | RX_DATA_QUEUE_FULL| r | 0x0 | RX_DATA_QUEUE_FULL|
2885+| 5 |RX_DATA_QUEUE_EMPTY| r | 0x1 |RX_DATA_QUEUE_EMPTY|
2886+| 6 | TX_DATA_QUEUE_FULL| r | 0x0 | TX_DATA_QUEUE_FULL|
2887+| 7 |TX_DATA_QUEUE_EMPTY| r | 0x1 |TX_DATA_QUEUE_EMPTY|
2888+| 8 | IBI_QUEUE_FULL | r | 0x0 | IBI_QUEUE_FULL |
2889+| 9 | IBI_QUEUE_EMPTY | r | 0x1 | IBI_QUEUE_EMPTY |
2890+
2891+#### RX_DESC_QUEUE_FULL field
2892+
2893+<p>RX Descriptor Queue is full</p>
2894+
2895+#### RX_DESC_QUEUE_EMPTY field
2896+
2897+<p>RX Descriptor Queue is empty</p>
2898+
2899+#### TX_DESC_QUEUE_FULL field
2900+
2901+<p>TX Descriptor Queue is full</p>
2902+
2903+#### TX_DESC_QUEUE_EMPTY field
2904+
2905+<p>TX Descriptor Queue is empty</p>
2906+
2907+#### RX_DATA_QUEUE_FULL field
2908+
2909+<p>RX Data Queue is full</p>
2910+
2911+#### RX_DATA_QUEUE_EMPTY field
2912+
2913+<p>RX Data Queue is empty</p>
2914+
2915+#### TX_DATA_QUEUE_FULL field
2916+
2917+<p>TX Data Queue is full</p>
2918+
2919+#### TX_DATA_QUEUE_EMPTY field
2920+
2921+<p>TX Data Queue is empty</p>
2922+
2923+#### IBI_QUEUE_FULL field
2924+
2925+<p>IBI Queue is full</p>
2926+
2927+#### IBI_QUEUE_EMPTY field
2928+
2929+<p>IBI Queue is empty</p>
2930+
2931+### DESC_QUEUE_DEPTH register
2932+
2933+- Absolute Address: 0x214
2934+- Base Offset: 0x14
2935+- Size: 0x4
2936+
2937+<p>Current number of entries in descriptor queues</p>
2938+
2939+|Bits| Identifier |Access|Reset| Name |
2940+|----|-------------------|------|-----|-------------------|
2941+| 7:0|RX_DESC_QUEUE_DEPTH| r | 0x0 |RX_DESC_QUEUE_DEPTH|
2942+|15:8|TX_DESC_QUEUE_DEPTH| r | 0x0 |TX_DESC_QUEUE_DEPTH|
2943+
2944+#### RX_DESC_QUEUE_DEPTH field
2945+
2946+<p>Number of entries in RX Descriptor Queue</p>
2947+
2948+#### TX_DESC_QUEUE_DEPTH field
2949+
2950+<p>Number of entries in TX Descriptor Queue</p>
2951+
2952+### DATA_QUEUE_DEPTH register
2953+
2954+- Absolute Address: 0x218
2955+- Base Offset: 0x18
2956+- Size: 0x4
2957+
2958+<p>Current number of DWORD entries in data queues</p>
2959+
2960+|Bits| Identifier |Access|Reset| Name |
2961+|----|-------------------|------|-----|-------------------|
2962+| 7:0|RX_DATA_QUEUE_DEPTH| r | 0x0 |RX_DATA_QUEUE_DEPTH|
2963+|15:8|TX_DATA_QUEUE_DEPTH| r | 0x0 |TX_DATA_QUEUE_DEPTH|
2964+
2965+#### RX_DATA_QUEUE_DEPTH field
2966+
2967+<p>Number of DWORD entries in RX Data Queue</p>
2968+
2969+#### TX_DATA_QUEUE_DEPTH field
2970+
2971+<p>Number of DWORD entries in TX Data Queue</p>
2972+
2973+### IBI_QUEUE_DEPTH register
2974+
2975+- Absolute Address: 0x21C
2976+- Base Offset: 0x1C
2977+- Size: 0x4
2978+
2979+<p>Current number of entries in IBI queue</p>
2980+
2981+|Bits| Identifier |Access|Reset| Name |
2982+|----|---------------|------|-----|---------------|
2983+| 7:0|IBI_QUEUE_DEPTH| r | 0x0 |IBI_QUEUE_DEPTH|
2984+
2985+#### IBI_QUEUE_DEPTH field
2986+
2987+<p>Number of entries in IBI Queue</p>
2988+
28182989 ### INTERRUPT_STATUS register
28192990
2820-- Absolute Address: 0x1D0
2821-- Base Offset: 0x10
2991+- Absolute Address: 0x220
2992+- Base Offset: 0x20
28222993 - Size: 0x4
28232994
28242995 <p>Interrupt Status</p>
@@ -2835,7 +3006,8 @@
28353006 | 11 | RX_DESC_THLD_STAT |rw, woclr| 0x0 | RX_DESC_THLD_STAT |
28363007 | 12 | IBI_THLD_STAT |rw, woclr| 0x0 | IBI_THLD_STAT |
28373008 | 13 | IBI_DONE |rw, woclr| 0x0 | IBI_DONE |
2838-|18:15| PENDING_INTERRUPT | rw | 0x0 | PENDING_INTERRUPT |
3009+|19:16| PENDING_INTERRUPT | rw | 0x0 | PENDING_INTERRUPT |
3010+| 20 | PENDING_IBI | r | 0x0 | PENDING_IBI |
28393011 | 25 |TRANSFER_ABORT_STAT|rw, woclr| 0x0 |TRANSFER_ABORT_STAT|
28403012 | 26 | TX_DESC_COMPLETE |rw, woclr| 0x0 | TX_DESC_COMPLETE |
28413013 | 31 | TRANSFER_ERR_STAT |rw, woclr| 0x0 | TRANSFER_ERR_STAT |
@@ -2850,15 +3022,15 @@
28503022
28513023 #### RX_DESC_TIMEOUT field
28523024
2853-<p>Pending Write was NACK’ed, because the <code>RX_DESC_STAT</code> event was not handled in time</p>
3025+<p>NOT IMPLEMENTED. Pending Write was NACK’ed, because the <code>RX_DESC_STAT</code> event was not handled in time</p>
28543026
28553027 #### TX_DESC_TIMEOUT field
28563028
2857-<p>Pending Read was NACK’ed, because the <code>TX_DESC_STAT</code> event was not handled in time</p>
3029+<p>NOT IMPLEMENTED. Pending Read was NACK’ed, because the <code>TX_DESC_STAT</code> event was not handled in time</p>
28583030
28593031 #### TX_DATA_THLD_STAT field
28603032
2861-<p>TTI TX Data Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI TX Data Queue is &gt;= the value defined in <code>TTI_TX_DATA_THLD</code></p>
3033+<p>NOT IMPLEMENTED. TTI TX Data Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI TX Data Queue is &gt;= the value defined in <code>TTI_TX_DATA_THLD</code></p>
28623034
28633035 #### RX_DATA_THLD_STAT field
28643036
@@ -2866,7 +3038,7 @@
28663038
28673039 #### TX_DESC_THLD_STAT field
28683040
2869-<p>TTI TX Descriptor Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI TX Descriptor Queue is &gt;= the value defined in <code>TTI_TX_DESC_THLD</code></p>
3041+<p>NOT IMPLEMENTED. TTI TX Descriptor Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI TX Descriptor Queue is &gt;= the value defined in <code>TTI_TX_DESC_THLD</code></p>
28703042
28713043 #### RX_DESC_THLD_STAT field
28723044
@@ -2874,7 +3046,7 @@
28743046
28753047 #### IBI_THLD_STAT field
28763048
2877-<p>TTI IBI Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI IBI Queue is &gt;= the value defined in <code>TTI_IBI_THLD</code></p>
3049+<p>NOT IMPLEMENTED. TTI IBI Buffer Threshold Status, the Target Controller shall set this bit to 1 when the number of available entries in the TTI IBI Queue is &gt;= the value defined in <code>TTI_IBI_THLD</code></p>
28783050
28793051 #### IBI_DONE field
28803052
@@ -2884,9 +3056,13 @@
28843056
28853057 <p>Contains the interrupt number of any pending interrupt, or 0 if no interrupts are pending. This encoding allows for up to 15 numbered interrupts. If more than one interrupt is set, then the highest priority interrupt shall be returned.</p>
28863058
3059+#### PENDING_IBI field
3060+
3061+<p>At least one IBI is pending</p>
3062+
28873063 #### TRANSFER_ABORT_STAT field
28883064
2889-<p>Bus aborted transaction</p>
3065+<p>NOT IMPLEMENTED. Bus aborted transaction</p>
28903066
28913067 #### TX_DESC_COMPLETE field
28923068
@@ -2894,12 +3070,12 @@
28943070
28953071 #### TRANSFER_ERR_STAT field
28963072
2897-<p>Bus error occurred</p>
3073+<p>NOT IMPLEMENTED. Bus error occurred</p>
28983074
28993075 ### INTERRUPT_ENABLE register
29003076
2901-- Absolute Address: 0x1D4
2902-- Base Offset: 0x14
3077+- Absolute Address: 0x224
3078+- Base Offset: 0x24
29033079 - Size: 0x4
29043080
29053081 <p>Interrupt Enable</p>
@@ -2974,8 +3150,8 @@
29743150
29753151 ### INTERRUPT_FORCE register
29763152
2977-- Absolute Address: 0x1D8
2978-- Base Offset: 0x18
3153+- Absolute Address: 0x228
3154+- Base Offset: 0x28
29793155 - Size: 0x4
29803156
29813157 <p>Interrupt Force</p>
@@ -3048,10 +3224,522 @@
30483224
30493225 <p>Enables the corresponding interrupt bit <code>TRANSFER_ERR_STAT_FORCE</code></p>
30503226
3227+### TARGET_ERR_CTRL register
3228+
3229+- Absolute Address: 0x22C
3230+- Base Offset: 0x2C
3231+- Size: 0x4
3232+
3233+<p>Target Error Detection Control. Set bits to enable error detection. Clear to disable.</p>
3234+
3235+|Bits| Identifier |Access|Reset| Name |
3236+|----|------------------------------------|------|-----|------------------------------------|
3237+| 0 | TE0_ERR_DET_EN | rw | 0x1 | TE0_ERR_DET_EN |
3238+| 1 | TE1_ERR_DET_EN | rw | 0x1 | TE1_ERR_DET_EN |
3239+| 2 | TE2_ERR_DET_EN | rw | 0x1 | TE2_ERR_DET_EN |
3240+| 3 | TE3_ERR_DET_EN | rw | 0x1 | TE3_ERR_DET_EN |
3241+| 4 | TE4_ERR_DET_EN | rw | 0x1 | TE4_ERR_DET_EN |
3242+| 5 | TE5_ERR_DET_EN | rw | 0x1 | TE5_ERR_DET_EN |
3243+| 6 | FRAMING_ERR_DET_EN | rw | 0x1 | FRAMING_ERR_DET_EN |
3244+| 7 | RI_PEC_ERR_DET_EN | rw | 0x1 | RI_PEC_ERR_DET_EN |
3245+| 8 | RI_LENGTH_ERR_DET_EN | rw | 0x1 | RI_LENGTH_ERR_DET_EN |
3246+| 9 | RI_READONLY_ERR_DET_EN | rw | 0x1 | RI_READONLY_ERR_DET_EN |
3247+| 10 | RI_UNSUPPORTED_ERR_DET_EN | rw | 0x1 | RI_UNSUPPORTED_ERR_DET_EN |
3248+| 11 | RI_RX_FIFO_OVERFLOW_ERR_DET_EN | rw | 0x1 | RI_RX_FIFO_OVERFLOW_ERR_DET_EN |
3249+| 12 |RI_INDIRECT_FIFO_OVERFLOW_ERR_DET_EN| rw | 0x1 |RI_INDIRECT_FIFO_OVERFLOW_ERR_DET_EN|
3250+
3251+#### TE0_ERR_DET_EN field
3252+
3253+<p>Enable TE0 error detection. Set to 0 to disable.</p>
3254+
3255+#### TE1_ERR_DET_EN field
3256+
3257+<p>Enable TE1 error detection. Set to 0 to disable.</p>
3258+
3259+#### TE2_ERR_DET_EN field
3260+
3261+<p>Enable TE2 error detection. Set to 0 to disable.</p>
3262+
3263+#### TE3_ERR_DET_EN field
3264+
3265+<p>Enable TE3 error detection. Set to 0 to disable.</p>
3266+
3267+#### TE4_ERR_DET_EN field
3268+
3269+<p>Enable TE4 error detection. Set to 0 to disable.</p>
3270+
3271+#### TE5_ERR_DET_EN field
3272+
3273+<p>Enable TE5 error detection. Set to 0 to disable.</p>
3274+
3275+#### FRAMING_ERR_DET_EN field
3276+
3277+<p>Enable framing error detection. Set to 0 to disable.</p>
3278+
3279+#### RI_PEC_ERR_DET_EN field
3280+
3281+<p>Enable Recovery Interface PEC/CRC error detection. Set to 0 to disable.</p>
3282+
3283+#### RI_LENGTH_ERR_DET_EN field
3284+
3285+<p>Enable Recovery Interface length error detection. Set to 0 to disable.</p>
3286+
3287+#### RI_READONLY_ERR_DET_EN field
3288+
3289+<p>Enable Recovery Interface write-to-read-only error detection. Set to 0 to disable.</p>
3290+
3291+#### RI_UNSUPPORTED_ERR_DET_EN field
3292+
3293+<p>Enable Recovery Interface unsupported command error detection. Set to 0 to disable.</p>
3294+
3295+#### RI_RX_FIFO_OVERFLOW_ERR_DET_EN field
3296+
3297+<p>Enable Recovery Interface RX FIFO overflow error detection and transition to Error state. Set to 0 to disable (overflow is still recorded in interrupt status).</p>
3298+
3299+#### RI_INDIRECT_FIFO_OVERFLOW_ERR_DET_EN field
3300+
3301+<p>Enable Recovery Interface INDIRECT FIFO overflow error detection and transition to Error state. Set to 0 to disable (overflow is still recorded in interrupt status).</p>
3302+
3303+### TARGET_ERR_INTR_STATUS register
3304+
3305+- Absolute Address: 0x230
3306+- Base Offset: 0x30
3307+- Size: 0x4
3308+
3309+<p>Target Error Interrupt Status. Write 1 to clear individual bits.</p>
3310+
3311+|Bits| Identifier | Access |Reset| Name |
3312+|----|----------------------------------|---------|-----|----------------------------------|
3313+| 1 | TE0_ERR_STAT |rw, woclr| 0x0 | TE0_ERR_STAT |
3314+| 2 | TE1_ERR_STAT |rw, woclr| 0x0 | TE1_ERR_STAT |
3315+| 3 | TE2_ERR_STAT |rw, woclr| 0x0 | TE2_ERR_STAT |
3316+| 4 | TE3_ERR_STAT |rw, woclr| 0x0 | TE3_ERR_STAT |
3317+| 5 | TE4_ERR_STAT |rw, woclr| 0x0 | TE4_ERR_STAT |
3318+| 6 | TE5_ERR_STAT |rw, woclr| 0x0 | TE5_ERR_STAT |
3319+| 7 | FRAMING_ERR_STAT |rw, woclr| 0x0 | FRAMING_ERR_STAT |
3320+| 8 | RI_PEC_ERR_STAT |rw, woclr| 0x0 | RI_PEC_ERR_STAT |
3321+| 9 | RI_LENGTH_ERR_STAT |rw, woclr| 0x0 | RI_LENGTH_ERR_STAT |
3322+| 10 | RI_READONLY_ERR_STAT |rw, woclr| 0x0 | RI_READONLY_ERR_STAT |
3323+| 11 | RI_UNSUPPORTED_ERR_STAT |rw, woclr| 0x0 | RI_UNSUPPORTED_ERR_STAT |
3324+| 12 | RI_RX_FIFO_OVERFLOW_ERR_STAT |rw, woclr| 0x0 | RI_RX_FIFO_OVERFLOW_ERR_STAT |
3325+| 13 |RI_INDIRECT_FIFO_OVERFLOW_ERR_STAT|rw, woclr| 0x0 |RI_INDIRECT_FIFO_OVERFLOW_ERR_STAT|
3326+
3327+#### TE0_ERR_STAT field
3328+
3329+<p>TE0: Invalid reserved address + RnW combination</p>
3330+
3331+#### TE1_ERR_STAT field
3332+
3333+<p>TE1: CCC command parity error</p>
3334+
3335+#### TE2_ERR_STAT field
3336+
3337+<p>TE2: CCC or Private Write data parity error</p>
3338+
3339+#### TE3_ERR_STAT field
3340+
3341+<p>TE3: ENTDAA PID mismatch</p>
3342+
3343+#### TE4_ERR_STAT field
3344+
3345+<p>TE4: ENTDAA BCR/DCR mismatch</p>
3346+
3347+#### TE5_ERR_STAT field
3348+
3349+<p>TE5: Broadcast/Direct CCC wrong R/W direction</p>
3350+
3351+#### FRAMING_ERR_STAT field
3352+
3353+<p>DA padding error (Bit[0] != 0 in SETDASA/SETNEWDA)</p>
3354+
3355+#### RI_PEC_ERR_STAT field
3356+
3357+<p>Recovery Interface PEC/CRC error detected</p>
3358+
3359+#### RI_LENGTH_ERR_STAT field
3360+
3361+<p>Recovery Interface length mismatch error detected</p>
3362+
3363+#### RI_READONLY_ERR_STAT field
3364+
3365+<p>Recovery Interface write-to-read-only error detected</p>
3366+
3367+#### RI_UNSUPPORTED_ERR_STAT field
3368+
3369+<p>Recovery Interface unsupported command error detected</p>
3370+
3371+#### RI_RX_FIFO_OVERFLOW_ERR_STAT field
3372+
3373+<p>Recovery Interface RX FIFO overflow error detected</p>
3374+
3375+#### RI_INDIRECT_FIFO_OVERFLOW_ERR_STAT field
3376+
3377+<p>Recovery Interface INDIRECT FIFO overflow error detected</p>
3378+
3379+### TARGET_ERR_INTR_ENABLE register
3380+
3381+- Absolute Address: 0x234
3382+- Base Offset: 0x34
3383+- Size: 0x4
3384+
3385+<p>Target Error Interrupt Enable. Set bits to enable corresponding interrupts.</p>
3386+
3387+|Bits| Identifier |Access|Reset| Name |
3388+|----|--------------------------------|------|-----|--------------------------------|
3389+| 1 | TE0_ERR_EN | rw | 0x0 | TE0_ERR_EN |
3390+| 2 | TE1_ERR_EN | rw | 0x0 | TE1_ERR_EN |
3391+| 3 | TE2_ERR_EN | rw | 0x0 | TE2_ERR_EN |
3392+| 4 | TE3_ERR_EN | rw | 0x0 | TE3_ERR_EN |
3393+| 5 | TE4_ERR_EN | rw | 0x0 | TE4_ERR_EN |
3394+| 6 | TE5_ERR_EN | rw | 0x0 | TE5_ERR_EN |
3395+| 7 | FRAMING_ERR_EN | rw | 0x0 | FRAMING_ERR_EN |
3396+| 8 | RI_PEC_ERR_EN | rw | 0x0 | RI_PEC_ERR_EN |
3397+| 9 | RI_LENGTH_ERR_EN | rw | 0x0 | RI_LENGTH_ERR_EN |
3398+| 10 | RI_READONLY_ERR_EN | rw | 0x0 | RI_READONLY_ERR_EN |
3399+| 11 | RI_UNSUPPORTED_ERR_EN | rw | 0x0 | RI_UNSUPPORTED_ERR_EN |
3400+| 12 | RI_RX_FIFO_OVERFLOW_ERR_EN | rw | 0x0 | RI_RX_FIFO_OVERFLOW_ERR_EN |
3401+| 13 |RI_INDIRECT_FIFO_OVERFLOW_ERR_EN| rw | 0x0 |RI_INDIRECT_FIFO_OVERFLOW_ERR_EN|
3402+
3403+#### TE0_ERR_EN field
3404+
3405+<p>Enables the corresponding interrupt bit <code>TE0_ERR_STAT</code></p>
3406+
3407+#### TE1_ERR_EN field
3408+
3409+<p>Enables the corresponding interrupt bit <code>TE1_ERR_STAT</code></p>
3410+
3411+#### TE2_ERR_EN field
3412+
3413+<p>Enables the corresponding interrupt bit <code>TE2_ERR_STAT</code></p>
3414+
3415+#### TE3_ERR_EN field
3416+
3417+<p>Enables the corresponding interrupt bit <code>TE3_ERR_STAT</code></p>
3418+
3419+#### TE4_ERR_EN field
3420+
3421+<p>Enables the corresponding interrupt bit <code>TE4_ERR_STAT</code></p>
3422+
3423+#### TE5_ERR_EN field
3424+
3425+<p>Enables the corresponding interrupt bit <code>TE5_ERR_STAT</code></p>
3426+
3427+#### FRAMING_ERR_EN field
3428+
3429+<p>Enables the corresponding interrupt bit <code>FRAMING_ERR_STAT</code></p>
3430+
3431+#### RI_PEC_ERR_EN field
3432+
3433+<p>Enables the corresponding interrupt bit <code>RI_PEC_ERR_STAT</code></p>
3434+
3435+#### RI_LENGTH_ERR_EN field
3436+
3437+<p>Enables the corresponding interrupt bit <code>RI_LENGTH_ERR_STAT</code></p>
3438+
3439+#### RI_READONLY_ERR_EN field
3440+
3441+<p>Enables the corresponding interrupt bit <code>RI_READONLY_ERR_STAT</code></p>
3442+
3443+#### RI_UNSUPPORTED_ERR_EN field
3444+
3445+<p>Enables the corresponding interrupt bit <code>RI_UNSUPPORTED_ERR_STAT</code></p>
3446+
3447+#### RI_RX_FIFO_OVERFLOW_ERR_EN field
3448+
3449+<p>Enables the corresponding interrupt bit <code>RI_RX_FIFO_OVERFLOW_ERR_STAT</code></p>
3450+
3451+#### RI_INDIRECT_FIFO_OVERFLOW_ERR_EN field
3452+
3453+<p>Enables the corresponding interrupt bit <code>RI_INDIRECT_FIFO_OVERFLOW_ERR_STAT</code></p>
3454+
3455+### TARGET_ERR_INTR_FORCE register
3456+
3457+- Absolute Address: 0x238
3458+- Base Offset: 0x38
3459+- Size: 0x4
3460+
3461+<p>Target Error Interrupt Force. Set bits to force corresponding interrupts for testing.</p>
3462+
3463+|Bits| Identifier |Access|Reset| Name |
3464+|----|-----------------------------------|------|-----|-----------------------------------|
3465+| 1 | TE0_ERR_FORCE | rw | 0x0 | TE0_ERR_FORCE |
3466+| 2 | TE1_ERR_FORCE | rw | 0x0 | TE1_ERR_FORCE |
3467+| 3 | TE2_ERR_FORCE | rw | 0x0 | TE2_ERR_FORCE |
3468+| 4 | TE3_ERR_FORCE | rw | 0x0 | TE3_ERR_FORCE |
3469+| 5 | TE4_ERR_FORCE | rw | 0x0 | TE4_ERR_FORCE |
3470+| 6 | TE5_ERR_FORCE | rw | 0x0 | TE5_ERR_FORCE |
3471+| 7 | FRAMING_ERR_FORCE | rw | 0x0 | FRAMING_ERR_FORCE |
3472+| 8 | RI_PEC_ERR_FORCE | rw | 0x0 | RI_PEC_ERR_FORCE |
3473+| 9 | RI_LENGTH_ERR_FORCE | rw | 0x0 | RI_LENGTH_ERR_FORCE |
3474+| 10 | RI_READONLY_ERR_FORCE | rw | 0x0 | RI_READONLY_ERR_FORCE |
3475+| 11 | RI_UNSUPPORTED_ERR_FORCE | rw | 0x0 | RI_UNSUPPORTED_ERR_FORCE |
3476+| 12 | RI_RX_FIFO_OVERFLOW_ERR_FORCE | rw | 0x0 | RI_RX_FIFO_OVERFLOW_ERR_FORCE |
3477+| 13 |RI_INDIRECT_FIFO_OVERFLOW_ERR_FORCE| rw | 0x0 |RI_INDIRECT_FIFO_OVERFLOW_ERR_FORCE|
3478+
3479+#### TE0_ERR_FORCE field
3480+
3481+<p>Forces the corresponding interrupt bit <code>TE0_ERR_STAT</code> to be set to 1</p>
3482+
3483+#### TE1_ERR_FORCE field
3484+
3485+<p>Forces the corresponding interrupt bit <code>TE1_ERR_STAT</code> to be set to 1</p>
3486+
3487+#### TE2_ERR_FORCE field
3488+
3489+<p>Forces the corresponding interrupt bit <code>TE2_ERR_STAT</code> to be set to 1</p>
3490+
3491+#### TE3_ERR_FORCE field
3492+
3493+<p>Forces the corresponding interrupt bit <code>TE3_ERR_STAT</code> to be set to 1</p>
3494+
3495+#### TE4_ERR_FORCE field
3496+
3497+<p>Forces the corresponding interrupt bit <code>TE4_ERR_STAT</code> to be set to 1</p>
3498+
3499+#### TE5_ERR_FORCE field
3500+
3501+<p>Forces the corresponding interrupt bit <code>TE5_ERR_STAT</code> to be set to 1</p>
3502+
3503+#### FRAMING_ERR_FORCE field
3504+
3505+<p>Forces the corresponding interrupt bit <code>FRAMING_ERR_STAT</code> to be set to 1</p>
3506+
3507+#### RI_PEC_ERR_FORCE field
3508+
3509+<p>Forces the corresponding interrupt bit <code>RI_PEC_ERR_STAT</code> to be set to 1</p>
3510+
3511+#### RI_LENGTH_ERR_FORCE field
3512+
3513+<p>Forces the corresponding interrupt bit <code>RI_LENGTH_ERR_STAT</code> to be set to 1</p>
3514+
3515+#### RI_READONLY_ERR_FORCE field
3516+
3517+<p>Forces the corresponding interrupt bit <code>RI_READONLY_ERR_STAT</code> to be set to 1</p>
3518+
3519+#### RI_UNSUPPORTED_ERR_FORCE field
3520+
3521+<p>Forces the corresponding interrupt bit <code>RI_UNSUPPORTED_ERR_STAT</code> to be set to 1</p>
3522+
3523+#### RI_RX_FIFO_OVERFLOW_ERR_FORCE field
3524+
3525+<p>Forces the corresponding interrupt bit <code>RI_RX_FIFO_OVERFLOW_ERR_STAT</code> to be set to 1</p>
3526+
3527+#### RI_INDIRECT_FIFO_OVERFLOW_ERR_FORCE field
3528+
3529+<p>Forces the corresponding interrupt bit <code>RI_INDIRECT_FIFO_OVERFLOW_ERR_STAT</code> to be set to 1</p>
3530+
3531+### TARGET_ERR_CNT_TE0 register
3532+
3533+- Absolute Address: 0x23C
3534+- Base Offset: 0x3C
3535+- Size: 0x4
3536+
3537+<p>Counts TE0 errors. Saturates at 255. Write 0 to clear.</p>
3538+
3539+|Bits|Identifier|Access|Reset|Name|
3540+|----|----------|------|-----|----|
3541+| 7:0| CNT | rw | 0x0 | CNT|
3542+
3543+#### CNT field
3544+
3545+<p>Error count (saturates at 255). Write 0 to clear.</p>
3546+
3547+### TARGET_ERR_CNT_TE1 register
3548+
3549+- Absolute Address: 0x240
3550+- Base Offset: 0x40
3551+- Size: 0x4
3552+
3553+<p>Counts TE1 errors. Saturates at 255. Write 0 to clear.</p>
3554+
3555+|Bits|Identifier|Access|Reset|Name|
3556+|----|----------|------|-----|----|
3557+| 7:0| CNT | rw | 0x0 | CNT|
3558+
3559+#### CNT field
3560+
3561+<p>Error count (saturates at 255). Write 0 to clear.</p>
3562+
3563+### TARGET_ERR_CNT_TE2 register
3564+
3565+- Absolute Address: 0x244
3566+- Base Offset: 0x44
3567+- Size: 0x4
3568+
3569+<p>Counts TE2 errors. Saturates at 255. Write 0 to clear.</p>
3570+
3571+|Bits|Identifier|Access|Reset|Name|
3572+|----|----------|------|-----|----|
3573+| 7:0| CNT | rw | 0x0 | CNT|
3574+
3575+#### CNT field
3576+
3577+<p>Error count (saturates at 255). Write 0 to clear.</p>
3578+
3579+### TARGET_ERR_CNT_TE3 register
3580+
3581+- Absolute Address: 0x248
3582+- Base Offset: 0x48
3583+- Size: 0x4
3584+
3585+<p>Counts TE3 errors. Saturates at 255. Write 0 to clear.</p>
3586+
3587+|Bits|Identifier|Access|Reset|Name|
3588+|----|----------|------|-----|----|
3589+| 7:0| CNT | rw | 0x0 | CNT|
3590+
3591+#### CNT field
3592+
3593+<p>Error count (saturates at 255). Write 0 to clear.</p>
3594+
3595+### TARGET_ERR_CNT_TE4 register
3596+
3597+- Absolute Address: 0x24C
3598+- Base Offset: 0x4C
3599+- Size: 0x4
3600+
3601+<p>Counts TE4 errors. Saturates at 255. Write 0 to clear.</p>
3602+
3603+|Bits|Identifier|Access|Reset|Name|
3604+|----|----------|------|-----|----|
3605+| 7:0| CNT | rw | 0x0 | CNT|
3606+
3607+#### CNT field
3608+
3609+<p>Error count (saturates at 255). Write 0 to clear.</p>
3610+
3611+### TARGET_ERR_CNT_TE5 register
3612+
3613+- Absolute Address: 0x250
3614+- Base Offset: 0x50
3615+- Size: 0x4
3616+
3617+<p>Counts TE5 errors. Saturates at 255. Write 0 to clear.</p>
3618+
3619+|Bits|Identifier|Access|Reset|Name|
3620+|----|----------|------|-----|----|
3621+| 7:0| CNT | rw | 0x0 | CNT|
3622+
3623+#### CNT field
3624+
3625+<p>Error count (saturates at 255). Write 0 to clear.</p>
3626+
3627+### TARGET_ERR_CNT_FRAMING register
3628+
3629+- Absolute Address: 0x254
3630+- Base Offset: 0x54
3631+- Size: 0x4
3632+
3633+<p>Counts framing errors. Saturates at 255. Write 0 to clear.</p>
3634+
3635+|Bits|Identifier|Access|Reset|Name|
3636+|----|----------|------|-----|----|
3637+| 7:0| CNT | rw | 0x0 | CNT|
3638+
3639+#### CNT field
3640+
3641+<p>Error count (saturates at 255). Write 0 to clear.</p>
3642+
3643+### TARGET_ERR_CNT_RI_PEC register
3644+
3645+- Absolute Address: 0x258
3646+- Base Offset: 0x58
3647+- Size: 0x4
3648+
3649+<p>Counts Recovery Interface PEC errors. Saturates at 255. Write 0 to clear.</p>
3650+
3651+|Bits|Identifier|Access|Reset|Name|
3652+|----|----------|------|-----|----|
3653+| 7:0| CNT | rw | 0x0 | CNT|
3654+
3655+#### CNT field
3656+
3657+<p>Error count (saturates at 255). Write 0 to clear.</p>
3658+
3659+### TARGET_ERR_CNT_RI_LENGTH register
3660+
3661+- Absolute Address: 0x25C
3662+- Base Offset: 0x5C
3663+- Size: 0x4
3664+
3665+<p>Counts Recovery Interface length mismatch errors. Saturates at 255. Write 0 to clear.</p>
3666+
3667+|Bits|Identifier|Access|Reset|Name|
3668+|----|----------|------|-----|----|
3669+| 7:0| CNT | rw | 0x0 | CNT|
3670+
3671+#### CNT field
3672+
3673+<p>Error count (saturates at 255). Write 0 to clear.</p>
3674+
3675+### TARGET_ERR_CNT_RI_READONLY register
3676+
3677+- Absolute Address: 0x260
3678+- Base Offset: 0x60
3679+- Size: 0x4
3680+
3681+<p>Counts Recovery Interface write-to-read-only errors. Saturates at 255. Write 0 to clear.</p>
3682+
3683+|Bits|Identifier|Access|Reset|Name|
3684+|----|----------|------|-----|----|
3685+| 7:0| CNT | rw | 0x0 | CNT|
3686+
3687+#### CNT field
3688+
3689+<p>Error count (saturates at 255). Write 0 to clear.</p>
3690+
3691+### TARGET_ERR_CNT_RI_UNSUPPORTED register
3692+
3693+- Absolute Address: 0x264
3694+- Base Offset: 0x64
3695+- Size: 0x4
3696+
3697+<p>Counts Recovery Interface unsupported command errors. Saturates at 255. Write 0 to clear.</p>
3698+
3699+|Bits|Identifier|Access|Reset|Name|
3700+|----|----------|------|-----|----|
3701+| 7:0| CNT | rw | 0x0 | CNT|
3702+
3703+#### CNT field
3704+
3705+<p>Error count (saturates at 255). Write 0 to clear.</p>
3706+
3707+### TARGET_ERR_CNT_RI_RX_FIFO_OVERFLOW register
3708+
3709+- Absolute Address: 0x268
3710+- Base Offset: 0x68
3711+- Size: 0x4
3712+
3713+<p>Counts Recovery Interface RX FIFO overflow errors. Saturates at 255. Write 0 to clear.</p>
3714+
3715+|Bits|Identifier|Access|Reset|Name|
3716+|----|----------|------|-----|----|
3717+| 7:0| CNT | rw | 0x0 | CNT|
3718+
3719+#### CNT field
3720+
3721+<p>Error count (saturates at 255). Write 0 to clear.</p>
3722+
3723+### TARGET_ERR_CNT_RI_INDIRECT_FIFO_OVERFLOW register
3724+
3725+- Absolute Address: 0x26C
3726+- Base Offset: 0x6C
3727+- Size: 0x4
3728+
3729+<p>Counts Recovery Interface INDIRECT FIFO overflow errors. Saturates at 255. Write 0 to clear.</p>
3730+
3731+|Bits|Identifier|Access|Reset|Name|
3732+|----|----------|------|-----|----|
3733+| 7:0| CNT | rw | 0x0 | CNT|
3734+
3735+#### CNT field
3736+
3737+<p>Error count (saturates at 255). Write 0 to clear.</p>
3738+
30513739 ### RX_DESC_QUEUE_PORT register
30523740
3053-- Absolute Address: 0x1DC
3054-- Base Offset: 0x1C
3741+- Absolute Address: 0x270
3742+- Base Offset: 0x70
30553743 - Size: 0x4
30563744
30573745 <p>RX Descriptor Queue Port</p>
@@ -3066,8 +3754,8 @@
30663754
30673755 ### RX_DATA_PORT register
30683756
3069-- Absolute Address: 0x1E0
3070-- Base Offset: 0x20
3757+- Absolute Address: 0x274
3758+- Base Offset: 0x74
30713759 - Size: 0x4
30723760
30733761 <p>RX Data Port</p>
@@ -3082,8 +3770,8 @@
30823770
30833771 ### TX_DESC_QUEUE_PORT register
30843772
3085-- Absolute Address: 0x1E4
3086-- Base Offset: 0x24
3773+- Absolute Address: 0x278
3774+- Base Offset: 0x78
30873775 - Size: 0x4
30883776
30893777 <p>TX Descriptor Queue Port</p>
@@ -3098,8 +3786,8 @@
30983786
30993787 ### TX_DATA_PORT register
31003788
3101-- Absolute Address: 0x1E8
3102-- Base Offset: 0x28
3789+- Absolute Address: 0x27C
3790+- Base Offset: 0x7C
31033791 - Size: 0x4
31043792
31053793 <p>TX Data Port</p>
@@ -3114,8 +3802,8 @@
31143802
31153803 ### IBI_PORT register
31163804
3117-- Absolute Address: 0x1EC
3118-- Base Offset: 0x2C
3805+- Absolute Address: 0x280
3806+- Base Offset: 0x80
31193807 - Size: 0x4
31203808
31213809 <p>IBI Data Port</p>
@@ -3130,8 +3818,8 @@
31303818
31313819 ### QUEUE_SIZE register
31323820
3133-- Absolute Address: 0x1F0
3134-- Base Offset: 0x30
3821+- Absolute Address: 0x284
3822+- Base Offset: 0x84
31353823 - Size: 0x4
31363824
31373825 <p>Queue Size</p>
@@ -3161,8 +3849,8 @@
31613849
31623850 ### IBI_QUEUE_SIZE register
31633851
3164-- Absolute Address: 0x1F4
3165-- Base Offset: 0x34
3852+- Absolute Address: 0x288
3853+- Base Offset: 0x88
31663854 - Size: 0x4
31673855
31683856 <p>IBI Queue Size</p>
@@ -3177,8 +3865,8 @@
31773865
31783866 ### QUEUE_THLD_CTRL register
31793867
3180-- Absolute Address: 0x1F8
3181-- Base Offset: 0x38
3868+- Absolute Address: 0x28C
3869+- Base Offset: 0x8C
31823870 - Size: 0x4
31833871
31843872 <p>Queue Threshold Control</p>
@@ -3203,8 +3891,8 @@
32033891
32043892 ### DATA_BUFFER_THLD_CTRL register
32053893
3206-- Absolute Address: 0x1FC
3207-- Base Offset: 0x3C
3894+- Absolute Address: 0x290
3895+- Base Offset: 0x90
32083896 - Size: 0x4
32093897
32103898 <p>IBI Queue Threshold Control</p>
@@ -3234,9 +3922,9 @@
32343922
32353923 ## SoCMgmtIf register file
32363924
3237-- Absolute Address: 0x200
3238-- Base Offset: 0x100
3239-- Size: 0x5C
3925+- Absolute Address: 0x300
3926+- Base Offset: 0x200
3927+- Size: 0x64
32403928
32413929 |Offset| Identifier | Name |
32423930 |------|-----------------------|----------------------------------------|
@@ -3263,17 +3951,19 @@
32633951 | 0x50 | T_FREE_REG | |
32643952 | 0x54 | T_AVAL_REG | |
32653953 | 0x58 | T_IDLE_REG | |
3954+| 0x5C | HDR_TIMEOUT_EN_REG | |
3955+| 0x60 | T_HDR_TIMEOUT_REG | |
32663956
32673957 ### EXTCAP_HEADER register
32683958
3269-- Absolute Address: 0x200
3959+- Absolute Address: 0x300
32703960 - Base Offset: 0x0
32713961 - Size: 0x4
32723962
32733963 |Bits|Identifier|Access|Reset| Name |
32743964 |----|----------|------|-----|----------|
32753965 | 7:0| CAP_ID | r | 0xC1| CAP_ID |
3276-|23:8|CAP_LENGTH| r | 0x18|CAP_LENGTH|
3966+|23:8|CAP_LENGTH| r | 0x1A|CAP_LENGTH|
32773967
32783968 #### CAP_ID field
32793969
@@ -3285,7 +3975,7 @@
32853975
32863976 ### SOC_MGMT_CONTROL register
32873977
3288-- Absolute Address: 0x204
3978+- Absolute Address: 0x304
32893979 - Base Offset: 0x4
32903980 - Size: 0x4
32913981
@@ -3299,7 +3989,7 @@
32993989
33003990 ### SOC_MGMT_STATUS register
33013991
3302-- Absolute Address: 0x208
3992+- Absolute Address: 0x308
33033993 - Base Offset: 0x8
33043994 - Size: 0x4
33053995
@@ -3313,7 +4003,7 @@
33134003
33144004 ### REC_INTF_CFG register
33154005
3316-- Absolute Address: 0x20C
4006+- Absolute Address: 0x30C
33174007 - Base Offset: 0xC
33184008 - Size: 0x4
33194009
@@ -3340,7 +4030,7 @@
33404030
33414031 ### REC_INTF_REG_W1C_ACCESS register
33424032
3343-- Absolute Address: 0x210
4033+- Absolute Address: 0x310
33444034 - Base Offset: 0x10
33454035 - Size: 0x4
33464036
@@ -3364,7 +4054,7 @@
33644054
33654055 ### SOC_MGMT_RSVD_2 register
33664056
3367-- Absolute Address: 0x214
4057+- Absolute Address: 0x314
33684058 - Base Offset: 0x14
33694059 - Size: 0x4
33704060
@@ -3378,7 +4068,7 @@
33784068
33794069 ### SOC_MGMT_RSVD_3 register
33804070
3381-- Absolute Address: 0x218
4071+- Absolute Address: 0x318
33824072 - Base Offset: 0x18
33834073 - Size: 0x4
33844074
@@ -3392,7 +4082,7 @@
33924082
33934083 ### SOC_PAD_CONF register
33944084
3395-- Absolute Address: 0x21C
4085+- Absolute Address: 0x31C
33964086 - Base Offset: 0x1C
33974087 - Size: 0x4
33984088
@@ -3466,7 +4156,7 @@
34664156
34674157 ### SOC_PAD_ATTR register
34684158
3469-- Absolute Address: 0x220
4159+- Absolute Address: 0x320
34704160 - Base Offset: 0x20
34714161 - Size: 0x4
34724162
@@ -3489,7 +4179,7 @@
34894179
34904180 ### SOC_MGMT_FEATURE_2 register
34914181
3492-- Absolute Address: 0x224
4182+- Absolute Address: 0x324
34934183 - Base Offset: 0x24
34944184 - Size: 0x4
34954185
@@ -3503,7 +4193,7 @@
35034193
35044194 ### SOC_MGMT_FEATURE_3 register
35054195
3506-- Absolute Address: 0x228
4196+- Absolute Address: 0x328
35074197 - Base Offset: 0x28
35084198 - Size: 0x4
35094199
@@ -3517,7 +4207,7 @@
35174207
35184208 ### T_R_REG register
35194209
3520-- Absolute Address: 0x22C
4210+- Absolute Address: 0x32C
35214211 - Base Offset: 0x2C
35224212 - Size: 0x4
35234213
@@ -3531,7 +4221,7 @@
35314221
35324222 ### T_F_REG register
35334223
3534-- Absolute Address: 0x230
4224+- Absolute Address: 0x330
35354225 - Base Offset: 0x30
35364226 - Size: 0x4
35374227
@@ -3545,7 +4235,7 @@
35454235
35464236 ### T_SU_DAT_REG register
35474237
3548-- Absolute Address: 0x234
4238+- Absolute Address: 0x334
35494239 - Base Offset: 0x34
35504240 - Size: 0x4
35514241
@@ -3559,7 +4249,7 @@
35594249
35604250 ### T_HD_DAT_REG register
35614251
3562-- Absolute Address: 0x238
4252+- Absolute Address: 0x338
35634253 - Base Offset: 0x38
35644254 - Size: 0x4
35654255
@@ -3573,7 +4263,7 @@
35734263
35744264 ### T_HIGH_REG register
35754265
3576-- Absolute Address: 0x23C
4266+- Absolute Address: 0x33C
35774267 - Base Offset: 0x3C
35784268 - Size: 0x4
35794269
@@ -3587,7 +4277,7 @@
35874277
35884278 ### T_LOW_REG register
35894279
3590-- Absolute Address: 0x240
4280+- Absolute Address: 0x340
35914281 - Base Offset: 0x40
35924282 - Size: 0x4
35934283
@@ -3601,7 +4291,7 @@
36014291
36024292 ### T_HD_STA_REG register
36034293
3604-- Absolute Address: 0x244
4294+- Absolute Address: 0x344
36054295 - Base Offset: 0x44
36064296 - Size: 0x4
36074297
@@ -3615,7 +4305,7 @@
36154305
36164306 ### T_SU_STA_REG register
36174307
3618-- Absolute Address: 0x248
4308+- Absolute Address: 0x348
36194309 - Base Offset: 0x48
36204310 - Size: 0x4
36214311
@@ -3629,7 +4319,7 @@
36294319
36304320 ### T_SU_STO_REG register
36314321
3632-- Absolute Address: 0x24C
4322+- Absolute Address: 0x34C
36334323 - Base Offset: 0x4C
36344324 - Size: 0x4
36354325
@@ -3643,7 +4333,7 @@
36434333
36444334 ### T_FREE_REG register
36454335
3646-- Absolute Address: 0x250
4336+- Absolute Address: 0x350
36474337 - Base Offset: 0x50
36484338 - Size: 0x4
36494339
@@ -3653,11 +4343,11 @@
36534343
36544344 #### T_FREE field
36554345
3656-
4346+<p>Time in clock cycles from STOP detection until Bus Free Condition (tBUF/tCAS). Configure based on System Clock.</p>
36574347
36584348 ### T_AVAL_REG register
36594349
3660-- Absolute Address: 0x254
4350+- Absolute Address: 0x354
36614351 - Base Offset: 0x54
36624352 - Size: 0x4
36634353
@@ -3667,11 +4357,11 @@
36674357
36684358 #### T_AVAL field
36694359
3670-
4360+<p>Time in clock cycles from STOP detection until Bus Available Condition (tAVAL). Configure based on System Clock. NOTE: I3C spec v1.1.1 Figure 24 shows the time from STOP, and 5.1.3.2.2 describes it as 'a period during which the Bus Free Condition is sustained continuously for a duration of at least tAVAL.' The timer starts at a bus STOP condition and FW can take into account the tBUF if needed.</p>
36714361
36724362 ### T_IDLE_REG register
36734363
3674-- Absolute Address: 0x258
4364+- Absolute Address: 0x358
36754365 - Base Offset: 0x58
36764366 - Size: 0x4
36774367
@@ -3681,12 +4371,40 @@
36814371
36824372 #### T_IDLE field
36834373
3684-
4374+<p>Time in clock cycles from STOP detection until Bus Idle Condition (tIDLE). Configure based on System Clock</p>
4375+
4376+### HDR_TIMEOUT_EN_REG register
4377+
4378+- Absolute Address: 0x35C
4379+- Base Offset: 0x5C
4380+- Size: 0x4
4381+
4382+|Bits| Identifier |Access|Reset|Name|
4383+|----|--------------|------|-----|----|
4384+| 0 |HDR_TIMEOUT_EN| rw | 0x0 | |
4385+
4386+#### HDR_TIMEOUT_EN field
4387+
4388+<p>Enable bit for the optional 60us HDR error recovery timer (I3C spec 5.1.10.1.9). When enabled, the Target can recover from TE0/TE1 errors if both SCL and SDA stay High for a period exceeding the configured threshold. Disabled on reset.</p>
4389+
4390+### T_HDR_TIMEOUT_REG register
4391+
4392+- Absolute Address: 0x360
4393+- Base Offset: 0x60
4394+- Size: 0x4
4395+
4396+|Bits| Identifier |Access| Reset|Name|
4397+|----|-------------|------|------|----|
4398+|19:0|T_HDR_TIMEOUT| rw |0xEA60| |
4399+
4400+#### T_HDR_TIMEOUT field
4401+
4402+<p>Timer threshold in clock cycles for the optional HDR error recovery (I3C spec 5.1.10.1.9). If both SCL and SDA stay High for this many clock cycles during a TE0/TE1 error-induced HDR mode, the Target exits HDR mode and returns to Idle. Configure based on System Clock to achieve 60us.</p>
36854403
36864404 ## CtrlCfg register file
36874405
3688-- Absolute Address: 0x260
3689-- Base Offset: 0x160
4406+- Absolute Address: 0x368
4407+- Base Offset: 0x268
36904408 - Size: 0x8
36914409
36924410 |Offset| Identifier | Name |
@@ -3696,7 +4414,7 @@
36964414
36974415 ### EXTCAP_HEADER register
36984416
3699-- Absolute Address: 0x260
4417+- Absolute Address: 0x368
37004418 - Base Offset: 0x0
37014419 - Size: 0x4
37024420
@@ -3715,7 +4433,7 @@
37154433
37164434 ### CONTROLLER_CONFIG register
37174435
3718-- Absolute Address: 0x264
4436+- Absolute Address: 0x36C
37194437 - Base Offset: 0x4
37204438 - Size: 0x4
37214439
@@ -3729,8 +4447,8 @@
37294447
37304448 ### TERMINATION_EXTCAP_HEADER register
37314449
3732-- Absolute Address: 0x268
3733-- Base Offset: 0x168
4450+- Absolute Address: 0x370
4451+- Base Offset: 0x270
37344452 - Size: 0x4
37354453
37364454 <p>Register after the last EC must advertise ID == 0.