| @@ -1,5 +1,5 @@ |
| 1 | 1 | <div style="font-size: 0.85em; color: #656d76; margin-bottom: 1em; padding: 0.5em; background: #f6f8fa; border-radius: 4px;"> |
| 2 | | -📄 Source: <a href="https://github.com/chipsalliance/i3c-core/blob/aae3424a8ecbd4edb7a60e23f76421de2d891712/doc/source/overview.md" target="_blank">chipsalliance/i3c-core/doc/source/overview.md</a> @ <code>aae3424</code> |
| 2 | +📄 Source: <a href="https://github.com/chipsalliance/i3c-core/blob/bb79ebd9b487c61cd1bea1aec2574ae4740f104d/doc/source/overview.md" target="_blank">chipsalliance/i3c-core/doc/source/overview.md</a> @ <code>bb79ebd</code> |
| 3 | 3 | </div> |
| 4 | 4 | |
| 5 | 5 | # I3C core overview |
| @@ -62,6 +62,44 @@ |
| 62 | 62 | * `recovery_payload_available_o` |
| 63 | 63 | * `recovery_image_activated_o` |
| 64 | 64 | |
| 65 | +## Address Behavior |
| 66 | + |
| 67 | +### Dynamic and Static Address Priority |
| 68 | + |
| 69 | +Per the I3C specification, once a Target has been assigned a Dynamic Address (via ENTDAA, |
| 70 | +SETDASA, SETAASA, or SETNEWDA), it shall stop responding to its Static Address. The |
| 71 | +core implements this as follows: |
| 72 | + |
| 73 | +- If `DYNAMIC_ADDR_VALID = 1`, the Target matches only on `DYNAMIC_ADDR` |
| 74 | +- If `DYNAMIC_ADDR_VALID = 0` and `STATIC_ADDR_VALID = 1`, the Target matches on `STATIC_ADDR` |
| 75 | + |
| 76 | +This rule applies independently to both the main target and the virtual target. |
| 77 | + |
| 78 | +### IBI Address |
| 79 | + |
| 80 | +When sending In-Band Interrupts, the Target uses a separate IBI address derived from the |
| 81 | +main (non-virtual) target's address with dynamic-over-static priority: |
| 82 | + |
| 83 | +- If the Dynamic Address is valid, the IBI address is the Dynamic Address. |
| 84 | +- Otherwise, the IBI address falls back to the Static Address. |
| 85 | + |
| 86 | +This is implemented in `configuration.sv`: |
| 87 | + |
| 88 | + assign target_ibi_addr_o = target_dyn_addr_valid_o ? target_dyn_addr_o : target_sta_addr_o; |
| 89 | + assign target_ibi_addr_valid_o = target_sta_addr_valid_o || target_dyn_addr_valid_o; |
| 90 | + |
| 91 | +IBI transmission is gated on `target_ibi_addr_valid`. If neither address is valid, |
| 92 | +`target_ibi_addr_valid` is deasserted and any pending IBI requests are effectively masked |
| 93 | +(the `ibi_pending` signal in `i3c_target_fsm.sv` requires `target_ibi_addr_valid_i`). |
| 94 | + |
| 95 | +### Virtual Target Addressing |
| 96 | + |
| 97 | +The virtual target (used for recovery) has its own independent address pair |
| 98 | +(`VIRT_STATIC_ADDR`, `VIRT_DYNAMIC_ADDR`) with the same dynamic-over-static priority rule. |
| 99 | +Both the main and virtual target addresses are checked in parallel on every incoming |
| 100 | +transaction. When the virtual target address matches, the `virtual_device_sel` signal |
| 101 | +routes the data path to the recovery handler, and TTI queue interrupts are gated. |
| 102 | + |
| 65 | 103 | ## Private reads and writes |
| 66 | 104 | |
| 67 | 105 | * The core handles I3C private reads and writes |
| @@ -89,39 +127,9 @@ |
| 89 | 127 | |
| 90 | 128 | ## I3C Common Command Codes (CCC) |
| 91 | 129 | |
| 92 | | -The I3C core supports all CCCs required by the I3C Basic spec, please see "Table 16 I3C Common Command Codes" for a full reference. |
| 93 | | - |
| 94 | | -All CCCs are exercised with Cocotb tests. |
| 95 | | - |
| 96 | | -### Broadcast CCCs |
| 97 | | - |
| 98 | | -The following Broadcast CCCs are currently supported by the core (all required Broadcast CCCs as per the errata, and one optional Broadcast CCC): |
| 99 | | - |
| 100 | | -* ENEC (R) - Enable Events Command |
| 101 | | -* DISEC (R) - Disable Events Command |
| 102 | | -* SETMWL (R) - Set Max Write Length |
| 103 | | -* SETMRL (R) - Set Max Read Length |
| 104 | | -* SETAASA (O) - Set All Addresses to Static Adresses |
| 105 | | -* RSTACT (R) - Target Reset Action |
| 106 | | - |
| 107 | | -### Direct CCCs |
| 108 | | - |
| 109 | | -The following Direct CCCs are currently supported by the core (all required Direct CCCs, plus several optional/conditional ones): |
| 110 | | - |
| 111 | | -* ENEC (R) - Enable Events Command |
| 112 | | -* DISEC (R) - Disable Events Command |
| 113 | | -* RSTDAA (R) - Direct Reset Dynamic Address Assignment - this direct CCC is deprecated, the core NACKs this command as per the spec |
| 114 | | -* SETDASA (O) - Set Dynamic Address from Static Address |
| 115 | | -* SETMWL (R) - Set Max Write Length |
| 116 | | -* SETMRL (R) - Set Max Read Length |
| 117 | | -* GETMWL (R) - Get Max Write Length |
| 118 | | -* GETMRL (R) - Set Max Read Length |
| 119 | | -* GETPID (C) - Get Provisioned ID |
| 120 | | -* GETBCR (C) - Get Bus Characteristics Register |
| 121 | | -* GETDCR (C) - Get Device Characteristics Register |
| 122 | | -* GETSTATUS (R) - Get Device Status |
| 123 | | -* RSTACT (R) - Target Reset Action |
| 124 | | - |
| 130 | +The I3C core supports all CCCs required by the I3C Basic spec. |
| 131 | +See [ccc](ccc.md) for the full list of supported CCCs, CCCs that update registers |
| 132 | +without firmware notification, and CCC error handling. |
| 125 | 133 | |
| 126 | 134 | ## Other features |
| 127 | 135 | |
| @@ -131,3 +139,5 @@ |
| 131 | 139 | * `escalated_reset_o` |
| 132 | 140 | |
| 133 | 141 | * The core correctly detects HDR-Exit Pattern |
| 142 | +* Optional 60 us HDR error recovery timer for TE0/TE1 error recovery (see [error_handling](error_handling.md)) |
| 143 | +* Target error detection (TE0-TE5) with interrupt reporting and saturating counters (see [error_handling](error_handling.md)) |