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| 1 | 1 | <div style="font-size: 0.85em; color: #656d76; margin-bottom: 1em; padding: 0.5em; background: #f6f8fa; border-radius: 4px;"> |
| 2 | | -📄 Source: <a href="https://github.com/chipsalliance/i3c-core/blob/aae3424a8ecbd4edb7a60e23f76421de2d891712/doc/source/ext_cap.md" target="_blank">chipsalliance/i3c-core/doc/source/ext_cap.md</a> @ <code>aae3424</code> |
| 2 | +📄 Source: <a href="https://github.com/chipsalliance/i3c-core/blob/bb79ebd9b487c61cd1bea1aec2574ae4740f104d/doc/source/ext_cap.md" target="_blank">chipsalliance/i3c-core/doc/source/ext_cap.md</a> @ <code>bb79ebd</code> |
| 3 | 3 | </div> |
| 4 | 4 | |
| 5 | 5 | # Specification for I3C Vendor-Specific Extended Capabilities |
| @@ -232,8 +232,8 @@ |
| 232 | 232 | Private Write timing diagram: Parity bit error or RX Queue overrun scenario |
| 233 | 233 | ::: |
| 234 | 234 | |
| 235 | | -If an Active Controller writes more data to the Target Device than it is capable to handle (even with triggering interrupts on threshold), the generated TTI RX Descriptor will indicate an error status and the Target Device should not ACK data on the bus. |
| 236 | | -The Active Controller can attempt mitigating such a situation by reading Target queue size from the `TTI_QUEUE_SIZE` register before sending a big chunk of data. |
| 235 | +If an Controller writes more data to the Target Device than it is capable to handle (even with triggering interrupts on threshold), the generated TTI RX Descriptor will indicate an error status and the Target Device should not ACK data on the bus. |
| 236 | +The Controller can attempt mitigating such a situation by reading Target queue size from the `TTI_QUEUE_SIZE` register before sending a big chunk of data. |
| 237 | 237 | |
| 238 | 238 | ##### In-Band Interrupts |
| 239 | 239 | |