Changes to Additional Resources

Comparing version 2.0 to 1.2
+53 additions -55 deletions
@@ -8,58 +8,56 @@
88
99
1010 - [VeeR EL2 Programmer's Reference Manual](https://chipsalliance.github.io/Cores-VeeR-EL2/html/main/docs_rendered/html/index.html) — Latest documentation for the VeeR EL2 core
11-- [Caliptra Subsystem Overview](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/README.md) — Required dependencies, env variables, repository overview, simulation flow and regression tests
12-- [TileLink-UL Bus Specification](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/tlul/README.md) — Bus specification for comportable devices
13-- [TileLink-UL Protocol Checker](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/tlul/doc/TlulProtocolChecker.md) — Protocol checked description for the TileLink-UL bus
14-- [TileLink-UL XBAR DV](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/tlul/doc/dv/README.md) — TileLink-UL bus testing overview
15-- [Power Manager Theory of Operation](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/pwrmgr/doc/theory_of_operation.md) — Overview of Power Manager's functionality
16-- [Power Manager Programmer's Guide](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/pwrmgr/doc/programmers_guide.md)
17-- [OTP Controller Field Descriptions](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/fuse_ctrl/doc/otp_ctrl_field_descriptions.md) — Description of fields stored in the OTP memory
18-- [OTP Controller Memory Map](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/fuse_ctrl/doc/otp_ctrl_mmap.md)
19-- [OTP Controller Registers](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/fuse_ctrl/doc/registers.md)
20-- [OTP Controller Partitions](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/fuse_ctrl/doc/otp_ctrl_partitions.md) — Description of OTP partition attributes
21-- [OTP Controller Digests](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/fuse_ctrl/doc/otp_ctrl_digests.md)
22-- [Analog Sensor Top Technical Specification](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/ast/README.md)
23-- [Analog Sensor Top Interface Signals](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/ast/doc/interfaces.md)
24-- [Caliptra Hands-On Guide](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/README.md) — Required dependencies, env variables, repository overview, simulation flow and regression tests for caliptra-rtl
25-- [UART HWIP Technical Specification](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/uart/doc/_index.md) — Specification, overview of the functionality and a programmer's guide
11+- [Caliptra Subsystem Overview](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/README.md) — Required dependencies, env variables, repository overview, simulation flow and regression tests
12+- [TileLink-UL Bus Specification](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/tlul/README.md) — Bus specification for comportable devices
13+- [TileLink-UL Protocol Checker](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/tlul/doc/TlulProtocolChecker.md) — Protocol checked description for the TileLink-UL bus
14+- [TileLink-UL XBAR DV](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/tlul/doc/dv/README.md) — TileLink-UL bus testing overview
15+- [Power Manager Theory of Operation](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/pwrmgr/doc/theory_of_operation.md) — Overview of Power Manager's functionality
16+- [Power Manager Programmer's Guide](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/pwrmgr/doc/programmers_guide.md)
17+- [OTP Controller Field Descriptions](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/fuse_ctrl/doc/otp_ctrl_field_descriptions.md) — Description of fields stored in the OTP memory
18+- [OTP Controller Registers](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/fuse_ctrl/doc/registers.md)
19+- [OTP Controller Partitions](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/fuse_ctrl/doc/otp_ctrl_partitions.md) — Description of OTP partition attributes
20+- [OTP Controller Digests](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/fuse_ctrl/doc/otp_ctrl_digests.md)
21+- [Analog Sensor Top Technical Specification](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/ast/README.md)
22+- [Analog Sensor Top Interface Signals](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/ast/doc/interfaces.md)
23+- [Caliptra Hands-On Guide](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/README.md) — Required dependencies, env variables, repository overview, simulation flow and regression tests for caliptra-rtl
24+- [UART HWIP Technical Specification](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/uart/doc/_index.md) — Specification, overview of the functionality and a programmer's guide
2625 - [Internal Registers for caliptra-rtl](https://chipsalliance.github.io/caliptra-rtl/main/internal-regs/?p=) — Latest register description for caliptra-rtl components
27-- [FV ECC Block Overview](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/ecc/formal/fv_ecc_block_overview.pdf)
28-- [JTAG DPI module for OpenOCD remote_bitbang driver](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/integration/test_suites/libs/jtagdpi/README.md) — Overview of a JTAG over DPI library
29-- [UART DV](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/uart/doc/dv/index.md) — UART testing overview
30-- [ECC](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/ecc/formal/readme.md) — ECC proofs
31-- [SHA256](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/sha256/formal/readme.md) — SHA256 testing overview
32-- [SHA512](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/sha512/formal/readme.md) — SHA512 testing overview
33-- [SHA512_MASKED](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/sha512_masked/formal/readme.md) — SHA512_MASKED testing overview
34-- [HMAC](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/hmac/formal/readme.md) — HMAC testing overview
35-- [DOE](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/doe/readme.md) — DOE testing overview
36-- [HMAC DRBG](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/hmac_drbg/formal/readme.md) — HMAC DRGB testing overview
37-- [Adam's Bridge Hardware Specification](https://github.com/chipsalliance/adams-bridge/blob/a2c404af8c2fe8facfc1193055019b08a7b1a474/docs/AdamsBridgeHardwareSpecification.md)
38-- [Adam's Bridge Hands-On Guide](https://github.com/chipsalliance/adams-bridge/blob/a2c404af8c2fe8facfc1193055019b08a7b1a474/README.md) — Required dependencies, env variables, repository overview, simulation flow and regression tests
39-- [Threat Model for Securing Adams Bridge Against Side-Channel Attacks](https://github.com/chipsalliance/adams-bridge/blob/a2c404af8c2fe8facfc1193055019b08a7b1a474/docs/AdamsBridgeSCA.md)
26+- [FV ECC Block Overview](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/ecc/formal/fv_ecc_block_overview.pdf)
27+- [JTAG DPI module for OpenOCD remote_bitbang driver](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/integration/test_suites/libs/jtagdpi/README.md) — Overview of a JTAG over DPI library
28+- [UART DV](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/uart/doc/dv/index.md) — UART testing overview
29+- [ECC](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/ecc/formal/readme.md) — ECC proofs
30+- [SHA256](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/sha256/formal/readme.md) — SHA256 testing overview
31+- [SHA512](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/sha512/formal/readme.md) — SHA512 testing overview
32+- [SHA512_MASKED](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/sha512_masked/formal/readme.md) — SHA512_MASKED testing overview
33+- [HMAC](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/hmac/formal/readme.md) — HMAC testing overview
34+- [DOE](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/doe/readme.md) — DOE testing overview
35+- [HMAC DRBG](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/hmac_drbg/formal/readme.md) — HMAC DRGB testing overview
36+- [Adam's Bridge Hands-On Guide](https://github.com/chipsalliance/adams-bridge/blob/c6eacc84c4466348950d7a6a449efb913596795c/README.md) — Required dependencies, env variables, repository overview, simulation flow and regression tests
37+- [Threat Model for Securing Adams Bridge Against Side-Channel Attacks](https://github.com/chipsalliance/adams-bridge/blob/c6eacc84c4466348950d7a6a449efb913596795c/docs/AdamsBridgeSCA.md)
4038 - [Caliptra](https://github.com/chipsalliance/Caliptra/blob/64ed6c378cc955014f8ed7823d0a24d0b9f4a5d2/README.md) — Readme of the Caliptra project
4139 - [Hardware Release Process](https://github.com/chipsalliance/Caliptra/blob/64ed6c378cc955014f8ed7823d0a24d0b9f4a5d2/doc/HWReleaseProcess.md)
4240
4341 ## Software
4442
4543
46-- [Caliptra firmware and software](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/README.md) — Directory structure, building and testing for caliptra-sw
47-- [Caliptra FMC Test Coverage](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/fmc/doc/diagrams/test-coverage.md) — Description of FMC test cases
48-- [Caliptra Runtime Firmware Test Coverage](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/runtime/doc/test-coverage.md) — Describes test cases
49-- [Caliptra ROM Errors](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/rom/dev/doc/error-attribution.md) — Fatal and non-fatal error codes description
50-- [Caliptra ROM Thread Model](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/rom/dev/doc/threat-model.md) — Overview of rules to ensure minimal possibility of security issues
51-- [Caliptra ROM Test Coverage](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/rom/dev/doc/test-coverage/test-coverage.md) — Describes test cases
52-- [Generating Register Definitions](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/registers/README.md) — Instructions for generating register definitions from caliptra-rtl
53-- [Emulator for Caliptra](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/sw-emulator/README.md) — Emulator's class and state diagrams
54-- [Caliptra C API - libcaliptra](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/libcaliptra/README.md)
55-- [Caliptra C API Examples](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/libcaliptra/examples/README.md) — Example on how to interact with the Caliptra API and adapt it to the desired target
56-- [Caliptra C API Examples - hwmodel](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/libcaliptra/examples/hwmodel/README.md) — Example implementation of libcaliptra's hardware interface
57-- [Caliptra Error Codes](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/error/README.md) — Describes where Caliptra error codes are defined
58-- [C and Rust bindings for Caliptra RTL (verilated)](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/hw/verilated/README.md) — Building and running C and Rust bindings for a verilated model of caliptra-rtl
59-- [Caliptra Core FPGA Guide](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/hw/fpga/README.md) — Guide for building and running caliptra-rtl on an FPGA
44+- [Caliptra firmware and software](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/README.md) — Directory structure, building and testing for caliptra-sw
45+- [Caliptra FMC Test Coverage](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/fmc/doc/diagrams/test-coverage.md) — Description of FMC test cases
46+- [Caliptra Runtime Firmware Test Coverage](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/runtime/doc/test-coverage.md) — Describes test cases
47+- [Caliptra ROM Errors](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/rom/dev/doc/error-attribution.md) — Fatal and non-fatal error codes description
48+- [Caliptra ROM Thread Model](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/rom/dev/doc/threat-model.md) — Overview of rules to ensure minimal possibility of security issues
49+- [Caliptra ROM Test Coverage](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/rom/dev/doc/test-coverage/test-coverage.md) — Describes test cases
50+- [Generating Register Definitions](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/registers/README.md) — Instructions for generating register definitions from caliptra-rtl
51+- [Emulator for Caliptra](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/sw-emulator/README.md) — Emulator's class and state diagrams
52+- [Caliptra C API - libcaliptra](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/libcaliptra/README.md)
53+- [Caliptra C API Examples](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/libcaliptra/examples/README.md) — Example on how to interact with the Caliptra API and adapt it to the desired target
54+- [Caliptra C API Examples - hwmodel](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/libcaliptra/examples/hwmodel/README.md) — Example implementation of libcaliptra's hardware interface
55+- [Caliptra Error Codes](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/error/README.md) — Describes where Caliptra error codes are defined
56+- [C and Rust bindings for Caliptra RTL (verilated)](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/hw/verilated/README.md) — Building and running C and Rust bindings for a verilated model of caliptra-rtl
57+- [Caliptra Core FPGA Guide](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/hw/fpga/README.md) — Guide for building and running caliptra-rtl on an FPGA
6058 - [Caliptra Subsystem FPGA Guide](https://github.com/chipsalliance/caliptra-mcu-sw/blob/a6784b633b2400d91c271929eb2e62584b04e685/hw/fpga/README.md) — Guide for building and running caliptra-ss on an FPGA
61-- [Caliptra SW Tests](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/test/README.md)
62-- [FIPS Functional Test Suite](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/test/tests/fips_test_suite/README.md) — Overview of the test suite and available test cases
59+- [Caliptra SW Tests](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/test/README.md)
60+- [FIPS Functional Test Suite](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/test/tests/fips_test_suite/README.md) — Overview of the test suite and available test cases
6361 - [Caliptra DPE](https://github.com/chipsalliance/caliptra-dpe/blob/337f7e4151f60add8e97445f71fc1393afc661a8/README.md) — General overview of Caliptra DPE
6462 - [Caliptra DPE Verification Tests](https://github.com/chipsalliance/caliptra-dpe/blob/337f7e4151f60add8e97445f71fc1393afc661a8/verification/README.md) — Description of DPE tests
6563 - [Caliptra DPE Simulator](https://github.com/chipsalliance/caliptra-dpe/blob/337f7e4151f60add8e97445f71fc1393afc661a8/simulator/README.md) — Overview of the DPE simulator
@@ -69,24 +67,24 @@
6967
7068
7169 - [Caliptra Checklist and Evaluation Methodology](https://github.com/chipsalliance/Caliptra/blob/64ed6c378cc955014f8ed7823d0a24d0b9f4a5d2/CaliptraChecklistAndEvaluationMethodology.md)
72-- [Power Manager Checklist](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/src/pwrmgr/doc/checklist.md)
73-- [UART Checklist](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/src/uart/doc/checklist.md)
70+- [Power Manager Checklist](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/src/pwrmgr/doc/checklist.md)
71+- [UART Checklist](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/src/uart/doc/checklist.md)
7472
7573 ## Release Notes
7674
7775
78-- [Release Notes - Caliptra Subsystem](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/Release_Notes.md)
79-- [Release Notes - Caliptra RTL](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/Release_Notes.md)
80-- [Release Notes - Adam's Bridge](https://github.com/chipsalliance/adams-bridge/blob/a2c404af8c2fe8facfc1193055019b08a7b1a474/Release_Notes.md)
76+- [Release Notes - Caliptra Subsystem](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/Release_Notes.md)
77+- [Release Notes - Caliptra RTL](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/Release_Notes.md)
78+- [Release Notes - Adam's Bridge](https://github.com/chipsalliance/adams-bridge/blob/c6eacc84c4466348950d7a6a449efb913596795c/Release_Notes.md)
8179 - [Release Notes - VeeR EL2](https://github.com/chipsalliance/Cores-VeeR-EL2/blob/ab93a36eb4fd7825845f92da797761dbfef29320/release-notes.md)
8280
8381 ## Tools
8482
8583
86-- [fuse_ctrl Partitions Generator](https://github.com/chipsalliance/caliptra-ss/blob/2041523f977f5b24453464eda02008b1bd0f4f66/tools/scripts/fuse_ctrl_script/gen_fuse_ctrl_partitions.md) — A script for generation of configurable blocks for the fuse_ctrl instantiation
87-- [Caliptra fpga-boss](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/ci-tools/fpga-boss/README.md) — Helper utility used for running Caliptra firmware on ZCU104 FPGA
88-- [Caliptra GitHub GCP Runner Infrastructure](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/ci-tools/github-runner/README.md) — Overview of the CI runner architecture
89-- [file-header-fix](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/ci-tools/file-header-fix/README.md) — Utility used to ensure that all files have proper copyright headers
84+- [fuse_ctrl Partitions Generator](https://github.com/chipsalliance/caliptra-ss/blob/9022fc2a57bb9af2f3ebc2376b98a807812e2e0f/tools/scripts/fuse_ctrl_script/gen_fuse_ctrl_partitions.md) — A script for generation of configurable blocks for the fuse_ctrl instantiation
85+- [Caliptra fpga-boss](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/ci-tools/fpga-boss/README.md) — Helper utility used for running Caliptra firmware on ZCU104 FPGA
86+- [Caliptra GitHub GCP Runner Infrastructure](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/ci-tools/github-runner/README.md) — Overview of the CI runner architecture
87+- [file-header-fix](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/ci-tools/file-header-fix/README.md) — Utility used to ensure that all files have proper copyright headers
9088
9189 ## Governance
9290
@@ -100,5 +98,5 @@
10098 - [Caliptra Trademark Audit Process](https://github.com/chipsalliance/Caliptra/blob/64ed6c378cc955014f8ed7823d0a24d0b9f4a5d2/CaliptraTrademarkAuditProcess.md)
10199 - [Caliptra Compliant Brand Guidelines](https://github.com/chipsalliance/Caliptra/blob/64ed6c378cc955014f8ed7823d0a24d0b9f4a5d2/doc/branding_guide/Caliptra_Compliant_Brand_Guidelines_2025-02-17.pdf)
102100 - [GitHub Rules](https://github.com/chipsalliance/Caliptra/blob/64ed6c378cc955014f8ed7823d0a24d0b9f4a5d2/GitHubRules.md)
103-- [Caliptra Release Checklist](https://github.com/chipsalliance/caliptra-rtl/blob/5f85fb4bc95b753a2f7d042db7dc2644ca1e8c49/docs/CaliptraReleaseChecklist.md) — Describes the release creation process
104-- [Caliptra 2.0 Branching Strategy](https://github.com/chipsalliance/caliptra-sw/blob/e6e5db26702ee88d530d2789ac87749472a6641c/BRANCHING_STRATEGY.md) — Branch naming convention
101+- [Caliptra Release Checklist](https://github.com/chipsalliance/caliptra-rtl/blob/35b0bc5691b2bd0fc180403914cfabe207379089/docs/CaliptraReleaseChecklist.md) — Describes the release creation process
102+- [Caliptra 2.0 Branching Strategy](https://github.com/chipsalliance/caliptra-sw/blob/e56467181b5313e53cf6cdc92f705a4127480fc2/BRANCHING_STRATEGY.md) — Branch naming convention