Project Full coverage report
Current view: Cores-VeeR-EL2—Cores-VeeR-EL2—design—lib—mem_lib.sv Coverage Hit Total
Test Date: 14-11-2024 Toggle 85.7% 6 7
Test: all Branch 100.0% 6 6

            Line data    Source code
       1              : // SPDX-License-Identifier: Apache-2.0
       2              : // Copyright 2020 Western Digital Corporation or it's affiliates.
       3              : //
       4              : // Licensed under the Apache License, Version 2.0 (the "License");
       5              : // you may not use this file except in compliance with the License.
       6              : // You may obtain a copy of the License at
       7              : //
       8              : // http://www.apache.org/licenses/LICENSE-2.0
       9              : //
      10              : // Unless required by applicable law or agreed to in writing, software
      11              : // distributed under the License is distributed on an "AS IS" BASIS,
      12              : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      13              : // See the License for the specific language governing permissions and
      14              : // limitations under the License.
      15              : 
      16              : `define EL2_LOCAL_RAM_TEST_IO          \
      17              : input logic WE,              \
      18              : input logic ME,              \
      19              : input logic CLK,             \
      20              : input logic TEST1,           \
      21              : input logic RME,             \
      22              : input logic  [3:0] RM,       \
      23              : input logic LS,              \
      24              : input logic DS,              \
      25              : input logic SD,              \
      26              : input logic TEST_RNM,        \
      27              : input logic BC1,             \
      28              : input logic BC2,             \
      29              : output logic ROP
      30              : 
      31              : `define EL2_RAM(depth, width)              \
      32              : module ram_``depth``x``width(               \
      33              :    input logic [$clog2(depth)-1:0] ADR,     \
      34              :    input logic [(width-1):0] D,             \
      35              :    output logic [(width-1):0] Q,            \
      36              :     `EL2_LOCAL_RAM_TEST_IO                 \
      37              : );                                          \
      38              : reg [(width-1):0] ram_core [(depth-1):0];   \
      39              : `ifdef GTLSIM                               \
      40              : integer i;                                  \
      41              : initial begin                               \
      42              :    for (i=0; i<depth; i=i+1)                \
      43              :      ram_core[i] = '0;                      \
      44              : end                                         \
      45              : `endif                                      \
      46              : always @(posedge CLK) begin                 \
      47              : `ifdef GTLSIM                               \
      48              :    if (ME && WE) ram_core[ADR] <= D;        \
      49              : `else                                       \
      50              :    if (ME && WE) begin ram_core[ADR] <= D; Q <= 'x; end  \
      51              : `endif                                      \
      52              :    if (ME && ~WE) Q <= ram_core[ADR];       \
      53              : end                                         \
      54              : assign ROP = ME;                            \
      55              :                                             \
      56              : endmodule
      57              : 
      58              : `define EL2_RAM_BE(depth, width)           \
      59              : module ram_be_``depth``x``width(            \
      60              :    input logic [$clog2(depth)-1:0] ADR,     \
      61              :    input logic [(width-1):0] D, WEM,        \
      62              :    output logic [(width-1):0] Q,            \
      63              :     `EL2_LOCAL_RAM_TEST_IO                 \
      64              : );                                          \
      65              : reg [(width-1):0] ram_core [(depth-1):0];   \
      66              : `ifdef GTLSIM                               \
      67              : integer i;                                  \
      68              : initial begin                               \
      69              :    for (i=0; i<depth; i=i+1)                \
      70              :      ram_core[i] = '0;                      \
      71              : end                                         \
      72              : `endif                                      \
      73              : always @(posedge CLK) begin                 \
      74              : `ifdef GTLSIM                               \
      75              :    if (ME && WE)       ram_core[ADR] <= D & WEM | ~WEM & ram_core[ADR];      \
      76              : `else                                       \
      77              :    if (ME && WE) begin ram_core[ADR] <= D & WEM | ~WEM & ram_core[ADR]; Q <= 'x; end  \
      78              : `endif                                      \
      79              :    if (ME && ~WE) Q <= ram_core[ADR];          \
      80              : end                                         \
      81              : assign ROP = ME;                            \
      82              :                                             \
      83              : endmodule
      84              : 
      85              : // parameterizable RAM for verilator sims
      86              : module el2_ram #(depth=4096, width=39) (
      87         2376 : input logic [$clog2(depth)-1:0] ADR,
      88         1428 : input logic [(width-1):0] D,
      89          572 : output logic [(width-1):0] Q,
      90            0 :  `EL2_LOCAL_RAM_TEST_IO
      91              : );
      92              : reg [(width-1):0] ram_core [(depth-1):0];
      93              : 
      94        16112 : always @(posedge CLK) begin
      95              : `ifdef GTLSIM
      96              :    if (ME && WE)       ram_core[ADR] <= D;
      97              : `else
      98         1500 :    if (ME && WE) begin ram_core[ADR] <= D; Q <= 'x; end
      99              : `endif
     100         1500 :    if (ME && ~WE) Q <= ram_core[ADR];
     101              : end
     102              : endmodule
     103              : 
     104              : //=========================================================================================================================
     105              : //=================================== START OF CCM  =======================================================================
     106              : //============= Possible sram sizes for a 39 bit wide memory ( 4 bytes + 7 bits ECC ) =====================================
     107              : //-------------------------------------------------------------------------------------------------------------------------
     108              : `EL2_RAM(32768, 39)
     109              : `EL2_RAM(16384, 39)
     110              : `EL2_RAM(8192, 39)
     111    423586777 : `EL2_RAM(4096, 39)
     112              : `EL2_RAM(3072, 39)
     113              : `EL2_RAM(2048, 39)
     114              : `EL2_RAM(1536, 39)     // need this for the 48KB DCCM option)
     115              : `EL2_RAM(1024, 39)
     116              : `EL2_RAM(768, 39)
     117              : `EL2_RAM(512, 39)
     118              : `EL2_RAM(256, 39)
     119              : `EL2_RAM(128, 39)
     120              : `EL2_RAM(1024, 20)
     121              : `EL2_RAM(512, 20)
     122              : `EL2_RAM(256, 20)
     123              : `EL2_RAM(128, 20)
     124              : `EL2_RAM(64, 20)
     125              : `EL2_RAM(4096, 34)
     126              : `EL2_RAM(2048, 34)
     127              : `EL2_RAM(1024, 34)
     128              : `EL2_RAM(512, 34)
     129              : `EL2_RAM(256, 34)
     130              : `EL2_RAM(128, 34)
     131              : `EL2_RAM(64, 34)
     132              : `EL2_RAM(8192, 68)
     133              : `EL2_RAM(4096, 68)
     134              : `EL2_RAM(2048, 68)
     135              : `EL2_RAM(1024, 68)
     136              : `EL2_RAM(512, 68)
     137              : `EL2_RAM(256, 68)
     138              : `EL2_RAM(128, 68)
     139              : `EL2_RAM(64, 68)
     140              : `EL2_RAM(8192, 71)
     141              : `EL2_RAM(4096, 71)
     142              : `EL2_RAM(2048, 71)
     143              : `EL2_RAM(1024, 71)
     144              : `EL2_RAM(512, 71)
     145              : `EL2_RAM(256, 71)
     146              : `EL2_RAM(128, 71)
     147              : `EL2_RAM(64, 71)
     148              : `EL2_RAM(4096, 42)
     149              : `EL2_RAM(2048, 42)
     150              : `EL2_RAM(1024, 42)
     151              : `EL2_RAM(512, 42)
     152              : `EL2_RAM(256, 42)
     153              : `EL2_RAM(128, 42)
     154              : `EL2_RAM(64, 42)
     155              : `EL2_RAM(4096, 22)
     156              : `EL2_RAM(2048, 22)
     157              : `EL2_RAM(1024, 22)
     158              : `EL2_RAM(512, 22)
     159              : `EL2_RAM(256, 22)
     160              : `EL2_RAM(128, 22)
     161              : `EL2_RAM(64, 22)
     162              : `EL2_RAM(1024, 26)
     163              : `EL2_RAM(4096, 26)
     164              : `EL2_RAM(2048, 26)
     165              : `EL2_RAM(512, 26)
     166              : `EL2_RAM(256, 26)
     167              : `EL2_RAM(128, 26)
     168              : `EL2_RAM(64, 26)
     169              : `EL2_RAM(32, 26)
     170              : `EL2_RAM(32, 22)
     171              : `EL2_RAM_BE(8192, 142)
     172              : `EL2_RAM_BE(4096, 142)
     173              : `EL2_RAM_BE(2048, 142)
     174              : `EL2_RAM_BE(1024, 142)
     175     79528872 : `EL2_RAM_BE(512, 142)
     176              : `EL2_RAM_BE(256, 142)
     177              : `EL2_RAM_BE(128, 142)
     178              : `EL2_RAM_BE(64, 142)
     179              : `EL2_RAM_BE(8192, 284)
     180              : `EL2_RAM_BE(4096, 284)
     181              : `EL2_RAM_BE(2048, 284)
     182              : `EL2_RAM_BE(1024, 284)
     183              : `EL2_RAM_BE(512, 284)
     184              : `EL2_RAM_BE(256, 284)
     185              : `EL2_RAM_BE(128, 284)
     186              : `EL2_RAM_BE(64, 284)
     187              : `EL2_RAM_BE(8192, 136)
     188              : `EL2_RAM_BE(4096, 136)
     189              : `EL2_RAM_BE(2048, 136)
     190              : `EL2_RAM_BE(1024, 136)
     191              : `EL2_RAM_BE(512, 136)
     192              : `EL2_RAM_BE(256, 136)
     193              : `EL2_RAM_BE(128, 136)
     194              : `EL2_RAM_BE(64, 136)
     195              : `EL2_RAM_BE(8192, 272)
     196              : `EL2_RAM_BE(4096, 272)
     197              : `EL2_RAM_BE(2048, 272)
     198              : `EL2_RAM_BE(1024, 272)
     199              : `EL2_RAM_BE(512, 272)
     200              : `EL2_RAM_BE(256, 272)
     201              : `EL2_RAM_BE(128, 272)
     202              : `EL2_RAM_BE(64, 272)
     203              : `EL2_RAM_BE(4096, 52)
     204              : `EL2_RAM_BE(2048, 52)
     205              : `EL2_RAM_BE(1024, 52)
     206              : `EL2_RAM_BE(512, 52)
     207              : `EL2_RAM_BE(256, 52)
     208     39591436 : `EL2_RAM_BE(128, 52)
     209              : `EL2_RAM_BE(64, 52)
     210              : `EL2_RAM_BE(32, 52)
     211              : `EL2_RAM_BE(4096, 104)
     212              : `EL2_RAM_BE(2048, 104)
     213              : `EL2_RAM_BE(1024, 104)
     214              : `EL2_RAM_BE(512, 104)
     215              : `EL2_RAM_BE(256, 104)
     216              : `EL2_RAM_BE(128, 104)
     217              : `EL2_RAM_BE(64, 104)
     218              : `EL2_RAM_BE(32, 104)
     219              : `EL2_RAM_BE(4096, 44)
     220              : `EL2_RAM_BE(2048, 44)
     221              : `EL2_RAM_BE(1024, 44)
     222              : `EL2_RAM_BE(512, 44)
     223              : `EL2_RAM_BE(256, 44)
     224              : `EL2_RAM_BE(128, 44)
     225              : `EL2_RAM_BE(64, 44)
     226              : `EL2_RAM_BE(32, 44)
     227              : `EL2_RAM_BE(4096, 88)
     228              : `EL2_RAM_BE(2048, 88)
     229              : `EL2_RAM_BE(1024, 88)
     230              : `EL2_RAM_BE(512, 88)
     231              : `EL2_RAM_BE(256, 88)
     232              : `EL2_RAM_BE(128, 88)
     233              : `EL2_RAM_BE(64, 88)
     234              : `EL2_RAM_BE(32, 88)
     235              : `EL2_RAM(64, 39)
     236              : 
     237              : 
     238              : `undef EL2_RAM
     239              : `undef EL2_RAM_BE
     240              : `undef EL2_LOCAL_RAM_TEST_IO
     241              : 
     242              :