Project Full coverage report
Current view: Cores-VeeR-EL2—Cores-VeeR-EL2—design—el2_veer_wrapper.sv Coverage Hit Total
Test Date: 14-11-2024 Toggle 73.8% 163 221
Test: all Branch 100.0% 1 1

            Line data    Source code
       1              : // SPDX-License-Identifier: Apache-2.0
       2              : // Copyright 2020 Western Digital Corporation or its affiliates.
       3              : // Copyright (c) 2023 Antmicro <www.antmicro.com>
       4              : //
       5              : // Licensed under the Apache License, Version 2.0 (the "License");
       6              : // you may not use this file except in compliance with the License.
       7              : // You may obtain a copy of the License at
       8              : //
       9              : // http://www.apache.org/licenses/LICENSE-2.0
      10              : //
      11              : // Unless required by applicable law or agreed to in writing, software
      12              : // distributed under the License is distributed on an "AS IS" BASIS,
      13              : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      14              : // See the License for the specific language governing permissions and
      15              : // limitations under the License.
      16              : 
      17              : //********************************************************************************
      18              : // $Id$
      19              : //
      20              : // Function: Top wrapper file with el2_veer/mem instantiated inside
      21              : // Comments:
      22              : //
      23              : //********************************************************************************
      24              : module el2_veer_wrapper
      25              : import el2_pkg::*;
      26              :  #(
      27              : `include "el2_param.vh"
      28              : )
      29              : (
      30     69830461 :    input logic                             clk,
      31          338 :    input logic                             rst_l,
      32          338 :    input logic                             dbg_rst_l,
      33            0 :    input logic [31:1]                      rst_vec,
      34            4 :    input logic                             nmi_int,
      35           16 :    input logic [31:1]                      nmi_vec,
      36            0 :    input logic [31:1]                      jtag_id,
      37              : 
      38              : 
      39       579000 :    output logic [31:0]                     trace_rv_i_insn_ip,
      40          339 :    output logic [31:0]                     trace_rv_i_address_ip,
      41      6169519 :    output logic                            trace_rv_i_valid_ip,
      42         5204 :    output logic                            trace_rv_i_exception_ip,
      43            4 :    output logic [4:0]                      trace_rv_i_ecause_ip,
      44           24 :    output logic                            trace_rv_i_interrupt_ip,
      45           62 :    output logic [31:0]                     trace_rv_i_tval_ip,
      46              : 
      47              :    // Bus signals
      48              : `ifdef RV_BUILD_AXI4
      49              :    //-------------------------- LSU AXI signals--------------------------
      50              :    // AXI Write Channels
      51       659446 :    output logic                            lsu_axi_awvalid,
      52       669068 :    input  logic                            lsu_axi_awready,
      53            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid,
      54          282 :    output logic [31:0]                     lsu_axi_awaddr,
      55          318 :    output logic [3:0]                      lsu_axi_awregion,
      56              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
      57              :    /*verilator coverage_off*/
      58              :    output logic [7:0]                      lsu_axi_awlen,
      59              :    /*verilator coverage_on*/
      60            0 :    output logic [2:0]                      lsu_axi_awsize,
      61              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
      62              :    /*verilator coverage_off*/
      63              :    output logic [1:0]                      lsu_axi_awburst,
      64              :    output logic                            lsu_axi_awlock,
      65              :    /*verilator coverage_on*/
      66         1773 :    output logic [3:0]                      lsu_axi_awcache,
      67              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
      68              :    /*verilator coverage_off*/
      69              :    output logic [2:0]                      lsu_axi_awprot,
      70              :    output logic [3:0]                      lsu_axi_awqos,
      71              :    /*verilator coverage_on*/
      72              : 
      73       659446 :    output logic                            lsu_axi_wvalid,
      74       669068 :    input  logic                            lsu_axi_wready,
      75        29795 :    output logic [63:0]                     lsu_axi_wdata,
      76       185761 :    output logic [7:0]                      lsu_axi_wstrb,
      77          319 :    output logic                            lsu_axi_wlast,
      78              : 
      79       668810 :    input  logic                            lsu_axi_bvalid,
      80              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
      81              :    /*verilator coverage_off*/
      82              :    output logic                            lsu_axi_bready,
      83              :    /*verilator coverage_on*/
      84            2 :    input  logic [1:0]                      lsu_axi_bresp,
      85            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid,
      86              : 
      87              :    // AXI Read Channels
      88       630888 :    output logic                            lsu_axi_arvalid,
      89       673312 :    input  logic                            lsu_axi_arready,
      90            0 :    output logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid,
      91          282 :    output logic [31:0]                     lsu_axi_araddr,
      92          318 :    output logic [3:0]                      lsu_axi_arregion,
      93              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
      94              :    /*verilator coverage_off*/
      95              :    output logic [7:0]                      lsu_axi_arlen,
      96              :    /*verilator coverage_on*/
      97            0 :    output logic [2:0]                      lsu_axi_arsize,
      98              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
      99              :    /*verilator coverage_off*/
     100              :    output logic [1:0]                      lsu_axi_arburst,
     101              :    output logic                            lsu_axi_arlock,
     102              :    /*verilator coverage_on*/
     103         1773 :    output logic [3:0]                      lsu_axi_arcache,
     104              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
     105              :    /*verilator coverage_off*/
     106              :    output logic [2:0]                      lsu_axi_arprot,
     107              :    output logic [3:0]                      lsu_axi_arqos,
     108              :    /*verilator coverage_on*/
     109              : 
     110       672996 :    input  logic                            lsu_axi_rvalid,
     111              :    /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
     112              :    /*verilator coverage_off*/
     113              :    output logic                            lsu_axi_rready,
     114              :    /*verilator coverage_on*/
     115            0 :    input  logic [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid,
     116        26503 :    input  logic [63:0]                     lsu_axi_rdata,
     117            2 :    input  logic [1:0]                      lsu_axi_rresp,
     118       673616 :    input  logic                            lsu_axi_rlast,
     119              : 
     120              :    //-------------------------- IFU AXI signals--------------------------
     121              :    // AXI Write Channels
     122              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     123              :    /*verilator coverage_off*/
     124              :    output logic                            ifu_axi_awvalid,
     125              :    /*verilator coverage_on*/
     126            0 :    input  logic                            ifu_axi_awready,
     127              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     128              :    /*verilator coverage_off*/
     129              :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_awid,
     130              :    output logic [31:0]                     ifu_axi_awaddr,
     131              :    output logic [3:0]                      ifu_axi_awregion,
     132              :    output logic [7:0]                      ifu_axi_awlen,
     133              :    output logic [2:0]                      ifu_axi_awsize,
     134              :    output logic [1:0]                      ifu_axi_awburst,
     135              :    output logic                            ifu_axi_awlock,
     136              :    output logic [3:0]                      ifu_axi_awcache,
     137              :    output logic [2:0]                      ifu_axi_awprot,
     138              :    output logic [3:0]                      ifu_axi_awqos,
     139              : 
     140              :    output logic                            ifu_axi_wvalid,
     141              :    /*verilator coverage_on*/
     142            0 :    input  logic                            ifu_axi_wready,
     143              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     144              :    /*verilator coverage_off*/
     145              :    output logic [63:0]                     ifu_axi_wdata,
     146              :    output logic [7:0]                      ifu_axi_wstrb,
     147              :    output logic                            ifu_axi_wlast,
     148              :    /*verilator coverage_on*/
     149              : 
     150            0 :    input  logic                            ifu_axi_bvalid,
     151              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     152              :    /*verilator coverage_off*/
     153              :    output logic                            ifu_axi_bready,
     154              :    /*verilator coverage_on*/
     155            0 :    input  logic [1:0]                      ifu_axi_bresp,
     156            0 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_bid,
     157              : 
     158              :    // AXI Read Channels
     159      4449495 :    output logic                            ifu_axi_arvalid,
     160      8918851 :    input  logic                            ifu_axi_arready,
     161      2739036 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
     162      1937946 :    output logic [31:0]                     ifu_axi_araddr,
     163          456 :    output logic [3:0]                      ifu_axi_arregion,
     164              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     165              :    /*verilator coverage_off*/
     166              :    output logic [7:0]                      ifu_axi_arlen,
     167              :    output logic [2:0]                      ifu_axi_arsize,
     168              :    output logic [1:0]                      ifu_axi_arburst,
     169              :    output logic                            ifu_axi_arlock,
     170              :    output logic [3:0]                      ifu_axi_arcache,
     171              :    output logic [2:0]                      ifu_axi_arprot,
     172              :    output logic [3:0]                      ifu_axi_arqos,
     173              :    /*verilator coverage_on*/
     174              : 
     175      8918533 :    input  logic                            ifu_axi_rvalid,
     176              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
     177              :    /*verilator coverage_off*/
     178              :    output logic                            ifu_axi_rready,
     179              :    /*verilator coverage_on*/
     180       897578 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
     181       744653 :    input  logic [63:0]                     ifu_axi_rdata,
     182           20 :    input  logic [1:0]                      ifu_axi_rresp,
     183      8918533 :    input  logic                            ifu_axi_rlast,
     184              : 
     185              :    //-------------------------- SB AXI signals--------------------------
     186              :    // AXI Write Channels
     187          122 :    output logic                            sb_axi_awvalid,
     188          122 :    input  logic                            sb_axi_awready,
     189              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     190              :    /*verilator coverage_off*/
     191              :    output logic [pt.SB_BUS_TAG-1:0]        sb_axi_awid,
     192              :    /*verilator coverage_on*/
     193            2 :    output logic [31:0]                     sb_axi_awaddr,
     194           98 :    output logic [3:0]                      sb_axi_awregion,
     195              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     196              :    /*verilator coverage_off*/
     197              :    output logic [7:0]                      sb_axi_awlen,
     198              :    /*verilator coverage_on*/
     199            0 :    output logic [2:0]                      sb_axi_awsize,
     200              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     201              :    /*verilator coverage_off*/
     202              :    output logic [1:0]                      sb_axi_awburst,
     203              :    output logic                            sb_axi_awlock,
     204              :    output logic [3:0]                      sb_axi_awcache,
     205              :    output logic [2:0]                      sb_axi_awprot,
     206              :    output logic [3:0]                      sb_axi_awqos,
     207              :    /*verilator coverage_on*/
     208              : 
     209          122 :    output logic                            sb_axi_wvalid,
     210          122 :    input  logic                            sb_axi_wready,
     211           31 :    output logic [63:0]                     sb_axi_wdata,
     212          260 :    output logic [7:0]                      sb_axi_wstrb,
     213          319 :    output logic                            sb_axi_wlast,
     214              : 
     215          122 :    input  logic                            sb_axi_bvalid,
     216          319 :    output logic                            sb_axi_bready,
     217            0 :    input  logic [1:0]                      sb_axi_bresp,
     218            0 :    input  logic [pt.SB_BUS_TAG-1:0]        sb_axi_bid,
     219              : 
     220              :    // AXI Read Channels
     221          620 :    output logic                            sb_axi_arvalid,
     222          620 :    input  logic                            sb_axi_arready,
     223              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     224              :    /*verilator coverage_off*/
     225              :    output logic [pt.SB_BUS_TAG-1:0]        sb_axi_arid,
     226              :    /*verilator coverage_on*/
     227            2 :    output logic [31:0]                     sb_axi_araddr,
     228           98 :    output logic [3:0]                      sb_axi_arregion,
     229              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     230              :    /*verilator coverage_off*/
     231              :    output logic [7:0]                      sb_axi_arlen,
     232              :    /*verilator coverage_on*/
     233            0 :    output logic [2:0]                      sb_axi_arsize,
     234              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     235              :    /*verilator coverage_off*/
     236              :    output logic [1:0]                      sb_axi_arburst,
     237              :    output logic                            sb_axi_arlock,
     238              :    output logic [3:0]                      sb_axi_arcache,
     239              :    output logic [2:0]                      sb_axi_arprot,
     240              :    output logic [3:0]                      sb_axi_arqos,
     241              :    /*verilator coverage_on*/
     242              : 
     243          620 :    input  logic                            sb_axi_rvalid,
     244              :    /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
     245              :    /*verilator coverage_off*/
     246              :    output logic                            sb_axi_rready,
     247              :    /*verilator coverage_on*/
     248            0 :    input  logic [pt.SB_BUS_TAG-1:0]        sb_axi_rid,
     249            3 :    input  logic [63:0]                     sb_axi_rdata,
     250            0 :    input  logic [1:0]                      sb_axi_rresp,
     251          620 :    input  logic                            sb_axi_rlast,
     252              : 
     253              :    //-------------------------- DMA AXI signals--------------------------
     254              :    // AXI Write Channels
     255           66 :    input  logic                            dma_axi_awvalid,
     256          319 :    output logic                            dma_axi_awready,
     257              :    /* exclude signals that are tied to constant value in tb_top.sv */
     258              :    /*verilator coverage_off*/
     259              :    input  logic [pt.DMA_BUS_TAG-1:0]       dma_axi_awid,
     260              :    /*verilator coverage_on*/
     261          282 :    input  logic [31:0]                     dma_axi_awaddr,
     262            0 :    input  logic [2:0]                      dma_axi_awsize,
     263            0 :    input  logic [2:0]                      dma_axi_awprot,
     264            0 :    input  logic [7:0]                      dma_axi_awlen,
     265            0 :    input  logic [1:0]                      dma_axi_awburst,
     266              : 
     267              : 
     268           66 :    input  logic                            dma_axi_wvalid,
     269          319 :    output logic                            dma_axi_wready,
     270        29795 :    input  logic [63:0]                     dma_axi_wdata,
     271       185761 :    input  logic [7:0]                      dma_axi_wstrb,
     272          318 :    input  logic                            dma_axi_wlast,
     273              : 
     274           66 :    output logic                            dma_axi_bvalid,
     275           66 :    input  logic                            dma_axi_bready,
     276            2 :    output logic [1:0]                      dma_axi_bresp,
     277            0 :    output logic [pt.DMA_BUS_TAG-1:0]       dma_axi_bid,
     278              : 
     279              :    // AXI Read Channels
     280            0 :    input  logic                            dma_axi_arvalid,
     281          319 :    output logic                            dma_axi_arready,
     282              :    /* exclude signals that are tied to constant value in tb_top.sv */
     283              :    /*verilator coverage_off*/
     284              :    input  logic [pt.DMA_BUS_TAG-1:0]       dma_axi_arid,
     285              :    /*verilator coverage_on*/
     286          282 :    input  logic [31:0]                     dma_axi_araddr,
     287            0 :    input  logic [2:0]                      dma_axi_arsize,
     288            0 :    input  logic [2:0]                      dma_axi_arprot,
     289            0 :    input  logic [7:0]                      dma_axi_arlen,
     290            0 :    input  logic [1:0]                      dma_axi_arburst,
     291              : 
     292            0 :    output logic                            dma_axi_rvalid,
     293            0 :    input  logic                            dma_axi_rready,
     294            0 :    output logic [pt.DMA_BUS_TAG-1:0]       dma_axi_rid,
     295           12 :    output logic [63:0]                     dma_axi_rdata,
     296            2 :    output logic [1:0]                      dma_axi_rresp,
     297          319 :    output logic                            dma_axi_rlast,
     298              : `endif
     299              : 
     300              : `ifdef RV_BUILD_AHB_LITE
     301              :  //// AHB LITE BUS
     302           17 :    output logic [31:0]                     haddr,
     303              :    /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
     304              :    /*verilator coverage_off*/
     305              :    output logic [2:0]                      hburst,
     306              :    output logic                            hmastlock,
     307              :    /*verilator coverage_on*/
     308            0 :    output logic [3:0]                      hprot,
     309            0 :    output logic [2:0]                      hsize,
     310      1442217 :    output logic [1:0]                      htrans,
     311            0 :    output logic                            hwrite,
     312              : 
     313              :    /* exclude signals that are tied to constant value in this file */
     314              :    /*verilator coverage_off*/
     315              :    input logic [63:0]                      hrdata,
     316              :    input logic                             hready,
     317              :    input logic                             hresp,
     318              :    /*verilator coverage_on*/
     319              : 
     320              :    // LSU AHB Master
     321          119 :    output logic [31:0]                     lsu_haddr,
     322              :    /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
     323              :    /*verilator coverage_off*/
     324              :    output logic [2:0]                      lsu_hburst,
     325              :    output logic                            lsu_hmastlock,
     326              :    /*verilator coverage_on*/
     327            0 :    output logic [3:0]                      lsu_hprot,
     328            0 :    output logic [2:0]                      lsu_hsize,
     329       444236 :    output logic [1:0]                      lsu_htrans,
     330        88982 :    output logic                            lsu_hwrite,
     331         5363 :    output logic [63:0]                     lsu_hwdata,
     332              : 
     333              :    /* exclude signals that are tied to constant value in this file */
     334              :    /*verilator coverage_off*/
     335              :    input logic [63:0]                      lsu_hrdata,
     336              :    input logic                             lsu_hready,
     337              :    input logic                             lsu_hresp,
     338              :    /*verilator coverage_on*/
     339              :    // Debug Syster Bus AHB
     340            2 :    output logic [31:0]                     sb_haddr,
     341              :    /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
     342              :    /*verilator coverage_off*/
     343              :    output logic [2:0]                      sb_hburst,
     344              :    output logic                            sb_hmastlock,
     345              :    /*verilator coverage_on*/
     346            0 :    output logic [3:0]                      sb_hprot,
     347            0 :    output logic [2:0]                      sb_hsize,
     348         1006 :    output logic [1:0]                      sb_htrans,
     349          119 :    output logic                            sb_hwrite,
     350           39 :    output logic [63:0]                     sb_hwdata,
     351              : 
     352              :    /* exclude signals that are tied to constant value in this file */
     353              :    /*verilator coverage_off*/
     354              :    input  logic [63:0]                     sb_hrdata,
     355              :    input  logic                            sb_hready,
     356              :    input  logic                            sb_hresp,
     357              :    /*verilator coverage_on*/
     358              : 
     359              :    // DMA Slave
     360              :    /* exclude signals that are tied to constant value in tb_top.sv */
     361              :    /*verilator coverage_off*/
     362              :    input logic                             dma_hsel,
     363              :    input logic [31:0]                      dma_haddr,
     364              :    input logic [2:0]                       dma_hburst,
     365              :    input logic                             dma_hmastlock,
     366              :    input logic [3:0]                       dma_hprot,
     367              :    input logic [2:0]                       dma_hsize,
     368              :    input logic [1:0]                       dma_htrans,
     369              :    input logic                             dma_hwrite,
     370              :    input logic [63:0]                      dma_hwdata,
     371              :    /*verilator coverage_on*/
     372           20 :    input logic                             dma_hreadyin,
     373              : 
     374            0 :    output logic [63:0]                     dma_hrdata,
     375           20 :    output logic                            dma_hreadyout,
     376            0 :    output logic                            dma_hresp,
     377              : `endif
     378              :    // clk ratio signals
     379          338 :    input logic                             lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
     380          338 :    input logic                             ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
     381          338 :    input logic                             dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
     382          338 :    input logic                             dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface
     383              : 
     384              :    // ICCM/DCCM ECC status
     385            8 :    output logic                            iccm_ecc_single_error,
     386            4 :    output logic                            iccm_ecc_double_error,
     387            4 :    output logic                            dccm_ecc_single_error,
     388            4 :    output logic                            dccm_ecc_double_error,
     389              : 
     390              :  // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not)
     391              : 
     392            0 :    input                                   el2_ic_data_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
     393            0 :    input                                   el2_ic_tag_ext_in_pkt_t  [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
     394              : 
     395           12 :    input logic                             timer_int,
     396           17 :    input logic                             soft_int,
     397            0 :    input logic [pt.PIC_TOTAL_INT:1]        extintsrc_req,
     398              : 
     399       340148 :    output logic                            dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
     400       514626 :    output logic                            dec_tlu_perfcnt1,
     401       312914 :    output logic                            dec_tlu_perfcnt2,
     402        48468 :    output logic                            dec_tlu_perfcnt3,
     403              : 
     404              :    // ports added by the soc team
     405      1500298 :    input logic                             jtag_tck,    // JTAG clk
     406        89912 :    input logic                             jtag_tms,    // JTAG TMS
     407       115668 :    input logic                             jtag_tdi,    // JTAG tdi
     408            4 :    input logic                             jtag_trst_n, // JTAG Reset
     409       113796 :    output logic                            jtag_tdo,    // JTAG TDO
     410        44948 :    output logic                            jtag_tdoEn,  // JTAG Test Data Output enable
     411              : 
     412            0 :    input logic [31:4] core_id,
     413              : 
     414              :    // Memory Export Interface
     415              :    el2_mem_if.veer_sram_src                el2_mem_export,
     416              : 
     417              :    // external MPC halt/run interface
     418          108 :    input logic                             mpc_debug_halt_req, // Async halt request
     419          108 :    input logic                             mpc_debug_run_req,  // Async run request
     420          338 :    input logic                             mpc_reset_run_req,  // Run/halt after reset
     421          108 :    output logic                            mpc_debug_halt_ack, // Halt ack
     422          108 :    output logic                            mpc_debug_run_ack,  // Run ack
     423            2 :    output logic                            debug_brkpt_status, // debug breakpoint
     424              : 
     425          108 :    input logic                             i_cpu_halt_req,      // Async halt req to CPU
     426          108 :    output logic                            o_cpu_halt_ack,      // core response to halt
     427          108 :    output logic                            o_cpu_halt_status,   // 1'b1 indicates core is halted
     428          118 :    output logic                            o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
     429          108 :    input logic                             i_cpu_run_req, // Async restart req to CPU
     430          108 :    output logic                            o_cpu_run_ack, // Core response to run req
     431              : 
     432              :    // Excluding scan_mode and mbist_mode from coverage as their usage is determined by the integrator of the VeeR core.
     433              :    /* verilator coverage_off */
     434              :    input logic                             scan_mode,     // To enable scan mode
     435              :    input logic                             mbist_mode,    // to enable mbist
     436              : 
     437              :    // DMI port for uncore
     438              :    input logic                             dmi_core_enable,
     439              :    input logic                             dmi_uncore_enable,
     440              :    output logic                            dmi_uncore_en,
     441              :    output logic                            dmi_uncore_wr_en,
     442              :    output logic                     [ 6:0] dmi_uncore_addr,
     443              :    output logic                     [31:0] dmi_uncore_wdata,
     444              :    input logic                      [31:0] dmi_uncore_rdata,
     445              :    output logic                            dmi_active
     446              :    /* verilator coverage_on */
     447              : );
     448              : 
     449     69830461 :    logic                             active_l2clk;
     450     69830461 :    logic                             free_l2clk;
     451              : 
     452              :    // DCCM ports
     453       262894 :    logic         dccm_wren;
     454       561000 :    logic         dccm_rden;
     455        18811 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_lo;
     456        18811 :    logic [pt.DCCM_BITS-1:0]         dccm_wr_addr_hi;
     457       471434 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_lo;
     458       677829 :    logic [pt.DCCM_BITS-1:0]         dccm_rd_addr_hi;
     459         5376 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo;
     460         5376 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi;
     461              : 
     462        47176 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_lo;
     463        47176 :    logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_hi;
     464              : 
     465              :    // PIC ports
     466              : 
     467              :    // Icache & Itag ports
     468          486 :    logic [31:1]  ic_rw_addr;
     469        10432 :    logic [pt.ICACHE_NUM_WAYS-1:0]   ic_wr_en  ;     // Which way to write
     470       680950 :    logic         ic_rd_en ;
     471              : 
     472              : 
     473       255918 :    logic [pt.ICACHE_NUM_WAYS-1:0]   ic_tag_valid;   // Valid from the I$ tag valid outside (in flops).
     474              : 
     475       109586 :    logic [pt.ICACHE_NUM_WAYS-1:0]   ic_rd_hit;      // ic_rd_hit[3:0]
     476            0 :    logic         ic_tag_perr;                       // Ic tag parity error
     477              : 
     478            0 :    logic [pt.ICACHE_INDEX_HI:3]  ic_debug_addr;     // Read/Write addresss to the Icache.
     479            0 :    logic         ic_debug_rd_en;                    // Icache debug rd
     480            0 :    logic         ic_debug_wr_en;                    // Icache debug wr
     481            0 :    logic         ic_debug_tag_array;                // Debug tag array
     482            0 :    logic [pt.ICACHE_NUM_WAYS-1:0]   ic_debug_way;   // Debug way. Rd or Wr.
     483              : 
     484            0 :    logic [25:0]  ictag_debug_rd_data;               // Debug icache tag.
     485       560509 :    logic [pt.ICACHE_BANKS_WAY-1:0][70:0]  ic_wr_data;
     486      2136178 :    logic [63:0]  ic_rd_data;
     487       231593 :    logic [70:0]  ic_debug_rd_data;                  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
     488            0 :    logic [70:0]  ic_debug_wr_data;                  // Debug wr cache.
     489              : 
     490            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr;       // ecc error per bank
     491            0 :    logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr;       // parity error per bank
     492              : 
     493      1737756 :    logic [63:0]  ic_premux_data;
     494      5602688 :    logic         ic_sel_premux_data;
     495              : 
     496              :    // ICCM ports
     497       160252 :    logic [pt.ICCM_BITS-1:1]    iccm_rw_addr;
     498           74 :    logic           iccm_wren;
     499       133206 :    logic           iccm_rden;
     500            0 :    logic [2:0]     iccm_wr_size;
     501           14 :    logic [77:0]    iccm_wr_data;
     502            8 :    logic           iccm_buf_correct_ecc;
     503            8 :    logic           iccm_correction_state;
     504              : 
     505       136532 :    logic [63:0]    iccm_rd_data;
     506       161264 :    logic [77:0]    iccm_rd_data_ecc;
     507              : 
     508          338 :    logic        core_rst_l;                         // Core reset including rst_l and dbg_rst_l
     509              : 
     510            2 :    logic        dccm_clk_override;
     511            2 :    logic        icm_clk_override;
     512            8 :    logic        dec_tlu_core_ecc_disable;
     513              : 
     514              : 
     515              :    // zero out the signals not presented at the wrapper instantiation level
     516              : `ifdef RV_BUILD_AXI4
     517              :    // Since all the signals in this block are tied to constant, we exclude this from coverage analysis
     518              :    /*verilator coverage_off*/
     519              : 
     520              :  //// AHB LITE BUS
     521              :    logic [31:0]              haddr;
     522              :    logic [2:0]               hburst;
     523              :    logic                     hmastlock;
     524              :    logic [3:0]               hprot;
     525              :    logic [2:0]               hsize;
     526              :    logic [1:0]               htrans;
     527              :    logic                     hwrite;
     528              : 
     529              :    logic [63:0]              hrdata;
     530              :    logic                     hready;
     531              :    logic                     hresp;
     532              : 
     533              :    // LSU AHB Master
     534              :    logic [31:0]              lsu_haddr;
     535              :    logic [2:0]               lsu_hburst;
     536              :    logic                     lsu_hmastlock;
     537              :    logic [3:0]               lsu_hprot;
     538              :    logic [2:0]               lsu_hsize;
     539              :    logic [1:0]               lsu_htrans;
     540              :    logic                     lsu_hwrite;
     541              :    logic [63:0]              lsu_hwdata;
     542              : 
     543              :    logic [63:0]              lsu_hrdata;
     544              :    logic                     lsu_hready;
     545              :    logic                     lsu_hresp;
     546              :    // Debug Syster Bus AHB
     547              :    logic [31:0]              sb_haddr;
     548              :    logic [2:0]               sb_hburst;
     549              :    logic                     sb_hmastlock;
     550              :    logic [3:0]               sb_hprot;
     551              :    logic [2:0]               sb_hsize;
     552              :    logic [1:0]               sb_htrans;
     553              :    logic                     sb_hwrite;
     554              :    logic [63:0]              sb_hwdata;
     555              : 
     556              :     logic [63:0]             sb_hrdata;
     557              :     logic                    sb_hready;
     558              :     logic                    sb_hresp;
     559              : 
     560              :    // DMA Slave
     561              :    logic                     dma_hsel;
     562              :    logic [31:0]              dma_haddr;
     563              :    logic [2:0]               dma_hburst;
     564              :    logic                     dma_hmastlock;
     565              :    logic [3:0]               dma_hprot;
     566              :    logic [2:0]               dma_hsize;
     567              :    logic [1:0]               dma_htrans;
     568              :    logic                     dma_hwrite;
     569              :    logic [63:0]              dma_hwdata;
     570              :    logic                     dma_hreadyin;
     571              : 
     572              :    logic [63:0]              dma_hrdata;
     573              :    logic                     dma_hreadyout;
     574              :    logic                     dma_hresp;
     575              : 
     576              : 
     577              : 
     578              :    // AHB
     579              :    assign  hrdata[63:0]                           = '0;
     580              :    assign  hready                                 = '0;
     581              :    assign  hresp                                  = '0;
     582              :    // LSU
     583              :    assign  lsu_hrdata[63:0]                       = '0;
     584              :    assign  lsu_hready                             = '0;
     585              :    assign  lsu_hresp                              = '0;
     586              :    // Debu
     587              :    assign  sb_hrdata[63:0]                        = '0;
     588              :    assign  sb_hready                              = '0;
     589              :    assign  sb_hresp                               = '0;
     590              : 
     591              :    // DMA
     592              :    assign  dma_hsel                               = '0;
     593              :    assign  dma_haddr[31:0]                        = '0;
     594              :    assign  dma_hburst[2:0]                        = '0;
     595              :    assign  dma_hmastlock                          = '0;
     596              :    assign  dma_hprot[3:0]                         = '0;
     597              :    assign  dma_hsize[2:0]                         = '0;
     598              :    assign  dma_htrans[1:0]                        = '0;
     599              :    assign  dma_hwrite                             = '0;
     600              :    assign  dma_hwdata[63:0]                       = '0;
     601              :    assign  dma_hreadyin                           = '0;
     602              : 
     603              :    /*verilator coverage_on*/
     604              : 
     605              : `endif //  `ifdef RV_BUILD_AXI4
     606              : 
     607              : 
     608              : `ifdef RV_BUILD_AHB_LITE
     609              :    // Since all the signals in this block are tied to constant, we exclude this from coverage analysis
     610              :    /*verilator coverage_off*/
     611              :    wire                            lsu_axi_awvalid;
     612              :    wire                            lsu_axi_awready;
     613              :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_awid;
     614              :    wire [31:0]                     lsu_axi_awaddr;
     615              :    wire [3:0]                      lsu_axi_awregion;
     616              :    wire [7:0]                      lsu_axi_awlen;
     617              :    wire [2:0]                      lsu_axi_awsize;
     618              :    wire [1:0]                      lsu_axi_awburst;
     619              :    wire                            lsu_axi_awlock;
     620              :    wire [3:0]                      lsu_axi_awcache;
     621              :    wire [2:0]                      lsu_axi_awprot;
     622              :    wire [3:0]                      lsu_axi_awqos;
     623              : 
     624              : 
     625              :    wire                            lsu_axi_wvalid;
     626              :    wire                            lsu_axi_wready;
     627              :    wire [63:0]                     lsu_axi_wdata;
     628              :    wire [7:0]                      lsu_axi_wstrb;
     629              :    wire                            lsu_axi_wlast;
     630              : 
     631              :    wire                            lsu_axi_bvalid;
     632              :    wire                            lsu_axi_bready;
     633              :    wire [1:0]                      lsu_axi_bresp;
     634              :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_bid;
     635              : 
     636              :    // AXI Read Channels
     637              :    wire                            lsu_axi_arvalid;
     638              :    wire                            lsu_axi_arready;
     639              :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_arid;
     640              :    wire [31:0]                     lsu_axi_araddr;
     641              :    wire [3:0]                      lsu_axi_arregion;
     642              :    wire [7:0]                      lsu_axi_arlen;
     643              :    wire [2:0]                      lsu_axi_arsize;
     644              :    wire [1:0]                      lsu_axi_arburst;
     645              :    wire                            lsu_axi_arlock;
     646              :    wire [3:0]                      lsu_axi_arcache;
     647              :    wire [2:0]                      lsu_axi_arprot;
     648              :    wire [3:0]                      lsu_axi_arqos;
     649              : 
     650              :    wire                            lsu_axi_rvalid;
     651              :    wire                            lsu_axi_rready;
     652              :    wire [pt.LSU_BUS_TAG-1:0]       lsu_axi_rid;
     653              :    wire [63:0]                     lsu_axi_rdata;
     654              :    wire [1:0]                      lsu_axi_rresp;
     655              :    wire                            lsu_axi_rlast;
     656              : 
     657              :    assign                          lsu_axi_awready = '0;
     658              :    assign                          lsu_axi_wready = '0;
     659              :    assign                          lsu_axi_bvalid = '0;
     660              :    assign                          lsu_axi_bresp = '0;
     661              :    assign                          lsu_axi_bid = {pt.LSU_BUS_TAG{1'b0}};
     662              :    assign                          lsu_axi_arready = '0;
     663              :    assign                          lsu_axi_rvalid = '0;
     664              :    assign                          lsu_axi_rid = {pt.LSU_BUS_TAG{1'b0}};
     665              :    assign                          lsu_axi_rdata = '0;
     666              :    assign                          lsu_axi_rresp = '0;
     667              :    assign                          lsu_axi_rlast = '0;
     668              :    //-------------------------- IFU AXI signals--------------------------
     669              :    // AXI Write Channels
     670              :    wire                            ifu_axi_awvalid;
     671              :    wire                            ifu_axi_awready;
     672              :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_awid;
     673              :    wire [31:0]                     ifu_axi_awaddr;
     674              :    wire [3:0]                      ifu_axi_awregion;
     675              :    wire [7:0]                      ifu_axi_awlen;
     676              :    wire [2:0]                      ifu_axi_awsize;
     677              :    wire [1:0]                      ifu_axi_awburst;
     678              :    wire                            ifu_axi_awlock;
     679              :    wire [3:0]                      ifu_axi_awcache;
     680              :    wire [2:0]                      ifu_axi_awprot;
     681              :    wire [3:0]                      ifu_axi_awqos;
     682              : 
     683              :    wire                            ifu_axi_wvalid;
     684              :    wire                            ifu_axi_wready;
     685              :    wire [63:0]                     ifu_axi_wdata;
     686              :    wire [7:0]                      ifu_axi_wstrb;
     687              :    wire                            ifu_axi_wlast;
     688              : 
     689              :    wire                            ifu_axi_bvalid;
     690              :    wire                            ifu_axi_bready;
     691              :    wire [1:0]                      ifu_axi_bresp;
     692              :    wire [pt.IFU_BUS_TAG-1:0]      ifu_axi_bid;
     693              : 
     694              :    // AXI Read Channels
     695              :    wire                            ifu_axi_arvalid;
     696              :    wire                            ifu_axi_arready;
     697              :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid;
     698              :    wire [31:0]                     ifu_axi_araddr;
     699              :    wire [3:0]                      ifu_axi_arregion;
     700              :    wire [7:0]                      ifu_axi_arlen;
     701              :    wire [2:0]                      ifu_axi_arsize;
     702              :    wire [1:0]                      ifu_axi_arburst;
     703              :    wire                            ifu_axi_arlock;
     704              :    wire [3:0]                      ifu_axi_arcache;
     705              :    wire [2:0]                      ifu_axi_arprot;
     706              :    wire [3:0]                      ifu_axi_arqos;
     707              : 
     708              :    wire                            ifu_axi_rvalid;
     709              :    wire                            ifu_axi_rready;
     710              :    wire [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid;
     711              :    wire [63:0]                     ifu_axi_rdata;
     712              :    wire [1:0]                      ifu_axi_rresp;
     713              :    wire                            ifu_axi_rlast;
     714              : 
     715              :    assign                          ifu_axi_bvalid = '0;
     716              :    assign                          ifu_axi_bresp = '0;
     717              :    assign                          ifu_axi_bid = {pt.IFU_BUS_TAG{1'b0}};
     718              :    assign                          ifu_axi_arready = '0;
     719              :    assign                          ifu_axi_rvalid = '0;
     720              :    assign                          ifu_axi_rid = {pt.IFU_BUS_TAG{1'b0}};
     721              :    assign                          ifu_axi_rdata = 0;
     722              :    assign                          ifu_axi_rresp = '0;
     723              :    assign                          ifu_axi_rlast = '0;
     724              :    //-------------------------- SB AXI signals--------------------------
     725              :    // AXI Write Channels
     726              :    wire                            sb_axi_awvalid;
     727              :    wire                            sb_axi_awready;
     728              :    wire [pt.SB_BUS_TAG-1:0]        sb_axi_awid;
     729              :    wire [31:0]                     sb_axi_awaddr;
     730              :    wire [3:0]                      sb_axi_awregion;
     731              :    wire [7:0]                      sb_axi_awlen;
     732              :    wire [2:0]                      sb_axi_awsize;
     733              :    wire [1:0]                      sb_axi_awburst;
     734              :    wire                            sb_axi_awlock;
     735              :    wire [3:0]                      sb_axi_awcache;
     736              :    wire [2:0]                      sb_axi_awprot;
     737              :    wire [3:0]                      sb_axi_awqos;
     738              : 
     739              :    wire                            sb_axi_wvalid;
     740              :    wire                            sb_axi_wready;
     741              :    wire [63:0]                     sb_axi_wdata;
     742              :    wire [7:0]                      sb_axi_wstrb;
     743              :    wire                            sb_axi_wlast;
     744              : 
     745              :    wire                            sb_axi_bvalid;
     746              :    wire                            sb_axi_bready;
     747              :    wire [1:0]                      sb_axi_bresp;
     748              :    wire [pt.SB_BUS_TAG-1:0]        sb_axi_bid;
     749              : 
     750              :    // AXI Read Channels
     751              :    wire                            sb_axi_arvalid;
     752              :    wire                            sb_axi_arready;
     753              :    wire [pt.SB_BUS_TAG-1:0]        sb_axi_arid;
     754              :    wire [31:0]                     sb_axi_araddr;
     755              :    wire [3:0]                      sb_axi_arregion;
     756              :    wire [7:0]                      sb_axi_arlen;
     757              :    wire [2:0]                      sb_axi_arsize;
     758              :    wire [1:0]                      sb_axi_arburst;
     759              :    wire                            sb_axi_arlock;
     760              :    wire [3:0]                      sb_axi_arcache;
     761              :    wire [2:0]                      sb_axi_arprot;
     762              :    wire [3:0]                      sb_axi_arqos;
     763              : 
     764              :    wire                            sb_axi_rvalid;
     765              :    wire                            sb_axi_rready;
     766              :    wire [pt.SB_BUS_TAG-1:0]        sb_axi_rid;
     767              :    wire [63:0]                     sb_axi_rdata;
     768              :    wire [1:0]                      sb_axi_rresp;
     769              :    wire                            sb_axi_rlast;
     770              : 
     771              :    assign                          sb_axi_awready = '0;
     772              :    assign                          sb_axi_wready = '0;
     773              :    assign                          sb_axi_bvalid = '0;
     774              :    assign                          sb_axi_bresp = '0;
     775              :    assign                          sb_axi_bid = {pt.SB_BUS_TAG{1'b0}};
     776              :    assign                          sb_axi_arready = '0;
     777              :    assign                          sb_axi_rvalid = '0;
     778              :    assign                          sb_axi_rid = {pt.SB_BUS_TAG{1'b0}};
     779              :    assign                          sb_axi_rdata = '0;
     780              :    assign                          sb_axi_rresp = '0;
     781              :    assign                          sb_axi_rlast = '0;
     782              :    //-------------------------- DMA AXI signals--------------------------
     783              :    // AXI Write Channels
     784              :    wire                         dma_axi_awvalid;
     785              :    wire                         dma_axi_awready;
     786              :    wire [pt.DMA_BUS_TAG-1:0]    dma_axi_awid;
     787              :    wire [31:0]                  dma_axi_awaddr;
     788              :    wire [2:0]                   dma_axi_awsize;
     789              :    wire [2:0]                   dma_axi_awprot;
     790              :    wire [7:0]                   dma_axi_awlen;
     791              :    wire [1:0]                   dma_axi_awburst;
     792              : 
     793              : 
     794              :    wire                         dma_axi_wvalid;
     795              :    wire                         dma_axi_wready;
     796              :    wire [63:0]                  dma_axi_wdata;
     797              :    wire [7:0]                   dma_axi_wstrb;
     798              :    wire                         dma_axi_wlast;
     799              : 
     800              :    assign                       dma_axi_awvalid = 1'b0;
     801              :    assign                       dma_axi_awid = {pt.DMA_BUS_TAG{1'b0}};
     802              :    assign                       dma_axi_awaddr = 32'd0;
     803              :    assign                       dma_axi_awsize = 3'd0;
     804              :    assign                       dma_axi_awprot = 3'd0;
     805              :    assign                       dma_axi_awlen = 8'd0;
     806              :    assign                       dma_axi_awburst = 2'd0;
     807              : 
     808              : 
     809              :    assign                       dma_axi_wvalid = 1'b0;
     810              :    assign                       dma_axi_wdata = 64'd0;
     811              :    assign                       dma_axi_wstrb = 8'd0;
     812              :    assign                       dma_axi_wlast = 1'b0;
     813              : 
     814              : 
     815              :    wire                         dma_axi_bvalid;
     816              :    wire                         dma_axi_bready;
     817              :    wire [1:0]                   dma_axi_bresp;
     818              :    wire [pt.DMA_BUS_TAG-1:0]    dma_axi_bid;
     819              : 
     820              :    assign                       dma_axi_bready = 1'b0;
     821              :    // AXI Read Channels
     822              :    wire                         dma_axi_arvalid;
     823              :    wire                         dma_axi_arready;
     824              :    wire [pt.DMA_BUS_TAG-1:0]    dma_axi_arid;
     825              :    wire [31:0]                  dma_axi_araddr;
     826              :    wire [2:0]                   dma_axi_arsize;
     827              :    wire [2:0]                   dma_axi_arprot;
     828              :    wire [7:0]                   dma_axi_arlen;
     829              :    wire [1:0]                   dma_axi_arburst;
     830              : 
     831              :    assign                       dma_axi_arvalid = 1'b0;
     832              :    assign                       dma_axi_arid = {pt.DMA_BUS_TAG{1'b0}};
     833              :    assign                       dma_axi_araddr = 32'd0;
     834              :    assign                       dma_axi_arsize = 3'd0;
     835              :    assign                       dma_axi_arprot = 3'd0;
     836              :    assign                       dma_axi_arlen = 8'd0;
     837              :    assign                       dma_axi_arburst = 2'd0;
     838              : 
     839              : 
     840              : 
     841              :    wire                         dma_axi_rvalid;
     842              :    wire                         dma_axi_rready;
     843              :    wire [pt.DMA_BUS_TAG-1:0]    dma_axi_rid;
     844              :    wire [63:0]                  dma_axi_rdata;
     845              :    wire [1:0]                   dma_axi_rresp;
     846              :    wire                         dma_axi_rlast;
     847              : 
     848              :    assign                       dma_axi_rready = 1'b0;
     849              :    // AXI
     850              :    assign ifu_axi_awready = 1'b1;
     851              :    assign ifu_axi_wready = 1'b1;
     852              :    assign ifu_axi_bvalid = '0;
     853              :    assign ifu_axi_bresp[1:0] = '0;
     854              :    assign ifu_axi_bid[pt.IFU_BUS_TAG-1:0] = '0;
     855              :  
     856              :    /*verilator coverage_on*/
     857              : 
     858              : `endif //  `ifdef RV_BUILD_AHB_LITE
     859              : 
     860              :    // DMI (core)
     861        16334 :    logic                   dmi_en;
     862            0 :    logic [6:0]             dmi_addr;
     863         6018 :    logic                   dmi_wr_en;
     864           80 :    logic [31:0]            dmi_wdata;
     865          108 :    logic [31:0]            dmi_rdata;
     866              : 
     867              :    // DMI (core)
     868        16334 :    logic                   dmi_reg_en;
     869            0 :    logic [6:0]             dmi_reg_addr;
     870         6018 :    logic                   dmi_reg_wr_en;
     871           80 :    logic [31:0]            dmi_reg_wdata;
     872          108 :    logic [31:0]            dmi_reg_rdata;
     873              : 
     874              :    // Instantiate the el2_veer core
     875              :    el2_veer #(.pt(pt)) veer (
     876              :                                 .clk(clk),
     877              :                                 .*
     878              :                                 );
     879              : 
     880              :    // Instantiate the mem
     881              :    el2_mem  #(.pt(pt)) mem (
     882              :                              .clk(active_l2clk),
     883              :                              .rst_l(core_rst_l),
     884              :                              .mem_export(el2_mem_export),
     885              :                              .*
     886              :                              );
     887              : 
     888              : 
     889              :    //  JTAG/DMI instance
     890              :    dmi_wrapper  dmi_wrapper (
     891              :     // JTAG signals
     892              :     .trst_n      (jtag_trst_n),     // JTAG reset
     893              :     .tck         (jtag_tck),        // JTAG clock
     894              :     .tms         (jtag_tms),        // Test mode select
     895              :     .tdi         (jtag_tdi),        // Test Data Input
     896              :     .tdo         (jtag_tdo),        // Test Data Output
     897              :     .tdoEnable   (jtag_tdoEn),      // Test Data Output enable
     898              :     // Processor Signals
     899              :     .core_rst_n  (dbg_rst_l),       // Debug reset, active low
     900              :     .core_clk    (clk),             // Core clock
     901              :     .jtag_id     (jtag_id),         // JTAG ID
     902              :     .rd_data     (dmi_rdata),       // Read data from  Processor
     903              :     .reg_wr_data (dmi_wdata),       // Write data to Processor
     904              :     .reg_wr_addr (dmi_addr),        // Write address to Processor
     905              :     .reg_en      (dmi_en),          // Write interface bit to Processor
     906              :     .reg_wr_en   (dmi_wr_en),       // Write enable to Processor
     907              :     .dmi_hard_reset   ()
     908              :    );
     909              : 
     910              :    // DMI core/uncore mux
     911              :    dmi_mux dmi_mux (
     912              :     .core_enable        (dmi_core_enable),
     913              :     .uncore_enable      (dmi_uncore_enable),
     914              : 
     915              :     .dmi_en             (dmi_en),
     916              :     .dmi_wr_en          (dmi_wr_en),
     917              :     .dmi_addr           (dmi_addr),
     918              :     .dmi_wdata          (dmi_wdata),
     919              :     .dmi_rdata          (dmi_rdata),
     920              : 
     921              :     .dmi_core_en        (dmi_reg_en),
     922              :     .dmi_core_wr_en     (dmi_reg_wr_en),
     923              :     .dmi_core_addr      (dmi_reg_addr),
     924              :     .dmi_core_wdata     (dmi_reg_wdata),
     925              :     .dmi_core_rdata     (dmi_reg_rdata),
     926              : 
     927              :     .dmi_uncore_en      (dmi_uncore_en),
     928              :     .dmi_uncore_wr_en   (dmi_uncore_wr_en),
     929              :     .dmi_uncore_addr    (dmi_uncore_addr),
     930              :     .dmi_uncore_wdata   (dmi_uncore_wdata),
     931              :     .dmi_uncore_rdata   (dmi_uncore_rdata)
     932              :    );
     933              : 
     934          339 :    always_comb dmi_active = dmi_en;
     935              : 
     936              : `ifdef RV_ASSERT_ON
     937              :   // to avoid internal assertions failure at time 0
     938              :   initial begin
     939              :     $assertoff(0, veer);
     940              :     @(negedge clk) $asserton(0, veer);
     941              :   end
     942              : `endif
     943              : 
     944              : endmodule