Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : // Copyright (c) 2023 Antmicro <www.antmicro.com>
4 : //
5 : // Licensed under the Apache License, Version 2.0 (the "License");
6 : // you may not use this file except in compliance with the License.
7 : // You may obtain a copy of the License at
8 : //
9 : // http://www.apache.org/licenses/LICENSE-2.0
10 : //
11 : // Unless required by applicable law or agreed to in writing, software
12 : // distributed under the License is distributed on an "AS IS" BASIS,
13 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 : // See the License for the specific language governing permissions and
15 : // limitations under the License.
16 :
17 : //********************************************************************************
18 : // $Id$
19 : //
20 : // Function: Top wrapper file with el2_veer/mem instantiated inside
21 : // Comments:
22 : //
23 : //********************************************************************************
24 : module el2_veer_wrapper
25 : import el2_pkg::*;
26 : #(
27 : `include "el2_param.vh"
28 : )
29 : (
30 115884880 : input logic clk,
31 299 : input logic rst_l,
32 297 : input logic dbg_rst_l,
33 297 : input logic [31:1] rst_vec,
34 4 : input logic nmi_int,
35 313 : input logic [31:1] nmi_vec,
36 297 : input logic [31:1] jtag_id,
37 :
38 :
39 5753684 : output logic [31:0] trace_rv_i_insn_ip,
40 6907440 : output logic [31:0] trace_rv_i_address_ip,
41 9539750 : output logic trace_rv_i_valid_ip,
42 1231182 : output logic trace_rv_i_exception_ip,
43 1231144 : output logic [4:0] trace_rv_i_ecause_ip,
44 8 : output logic trace_rv_i_interrupt_ip,
45 114615 : output logic [31:0] trace_rv_i_tval_ip,
46 :
47 : // Bus signals
48 : `ifdef RV_BUILD_AXI4
49 : //-------------------------- LSU AXI signals--------------------------
50 : // AXI Write Channels
51 574450 : output logic lsu_axi_awvalid,
52 581774 : input logic lsu_axi_awready,
53 267362 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
54 276908 : output logic [31:0] lsu_axi_awaddr,
55 49868 : output logic [3:0] lsu_axi_awregion,
56 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
57 : /*pragma coverage off*/
58 : output logic [7:0] lsu_axi_awlen,
59 : /*pragma coverage on*/
60 2244 : output logic [2:0] lsu_axi_awsize,
61 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
62 : /*pragma coverage off*/
63 : output logic [1:0] lsu_axi_awburst,
64 : output logic lsu_axi_awlock,
65 : /*pragma coverage on*/
66 1732 : output logic [3:0] lsu_axi_awcache,
67 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
68 : /*pragma coverage off*/
69 : output logic [2:0] lsu_axi_awprot,
70 : output logic [3:0] lsu_axi_awqos,
71 : /*pragma coverage on*/
72 :
73 574450 : output logic lsu_axi_wvalid,
74 581774 : input logic lsu_axi_wready,
75 119820 : output logic [63:0] lsu_axi_wdata,
76 228231 : output logic [7:0] lsu_axi_wstrb,
77 277 : output logic lsu_axi_wlast,
78 :
79 581564 : input logic lsu_axi_bvalid,
80 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
81 : /*pragma coverage off*/
82 : output logic lsu_axi_bready,
83 : /*pragma coverage on*/
84 2 : input logic [1:0] lsu_axi_bresp,
85 151608 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
86 :
87 : // AXI Read Channels
88 567944 : output logic lsu_axi_arvalid,
89 599132 : input logic lsu_axi_arready,
90 267362 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
91 276908 : output logic [31:0] lsu_axi_araddr,
92 49868 : output logic [3:0] lsu_axi_arregion,
93 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
94 : /*pragma coverage off*/
95 : output logic [7:0] lsu_axi_arlen,
96 : /*pragma coverage on*/
97 2244 : output logic [2:0] lsu_axi_arsize,
98 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
99 : /*pragma coverage off*/
100 : output logic [1:0] lsu_axi_arburst,
101 : output logic lsu_axi_arlock,
102 : /*pragma coverage on*/
103 1732 : output logic [3:0] lsu_axi_arcache,
104 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
105 : /*pragma coverage off*/
106 : output logic [2:0] lsu_axi_arprot,
107 : output logic [3:0] lsu_axi_arqos,
108 : /*pragma coverage on*/
109 :
110 598858 : input logic lsu_axi_rvalid,
111 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
112 : /*pragma coverage off*/
113 : output logic lsu_axi_rready,
114 : /*pragma coverage on*/
115 77400 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
116 82905 : input logic [63:0] lsu_axi_rdata,
117 2 : input logic [1:0] lsu_axi_rresp,
118 599478 : input logic lsu_axi_rlast,
119 :
120 : //-------------------------- IFU AXI signals--------------------------
121 : // AXI Write Channels
122 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv
123 : IFU does not use AXI write channel */
124 : /*pragma coverage off*/
125 : output logic ifu_axi_awvalid,
126 : input logic ifu_axi_awready,
127 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
128 : output logic [31:0] ifu_axi_awaddr,
129 : output logic [3:0] ifu_axi_awregion,
130 : output logic [7:0] ifu_axi_awlen,
131 : output logic [2:0] ifu_axi_awsize,
132 : output logic [1:0] ifu_axi_awburst,
133 : output logic ifu_axi_awlock,
134 : output logic [3:0] ifu_axi_awcache,
135 : output logic [2:0] ifu_axi_awprot,
136 : output logic [3:0] ifu_axi_awqos,
137 :
138 : output logic ifu_axi_wvalid,
139 : input logic ifu_axi_wready,
140 : output logic [63:0] ifu_axi_wdata,
141 : output logic [7:0] ifu_axi_wstrb,
142 : output logic ifu_axi_wlast,
143 :
144 : input logic ifu_axi_bvalid,
145 : output logic ifu_axi_bready,
146 : input logic [1:0] ifu_axi_bresp,
147 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,
148 : /*pragma coverage on*/
149 :
150 : // AXI Read Channels
151 4455953 : output logic ifu_axi_arvalid,
152 10910617 : input logic ifu_axi_arready,
153 5455279 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
154 5455279 : output logic [31:0] ifu_axi_araddr,
155 462 : output logic [3:0] ifu_axi_arregion,
156 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
157 : /*pragma coverage off*/
158 : output logic [7:0] ifu_axi_arlen,
159 : output logic [2:0] ifu_axi_arsize,
160 : output logic [1:0] ifu_axi_arburst,
161 : output logic ifu_axi_arlock,
162 : output logic [3:0] ifu_axi_arcache,
163 : output logic [2:0] ifu_axi_arprot,
164 : output logic [3:0] ifu_axi_arqos,
165 : /*pragma coverage on*/
166 :
167 10910341 : input logic ifu_axi_rvalid,
168 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
169 : /*pragma coverage off*/
170 : output logic ifu_axi_rready,
171 : /*pragma coverage on*/
172 4352722 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
173 2391184 : input logic [63:0] ifu_axi_rdata,
174 20 : input logic [1:0] ifu_axi_rresp,
175 10910341 : input logic ifu_axi_rlast,
176 :
177 : //-------------------------- SB AXI signals--------------------------
178 : // AXI Write Channels
179 122 : output logic sb_axi_awvalid,
180 122 : input logic sb_axi_awready,
181 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
182 : /*pragma coverage off*/
183 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
184 : /*pragma coverage on*/
185 378 : output logic [31:0] sb_axi_awaddr,
186 99 : output logic [3:0] sb_axi_awregion,
187 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
188 : /*pragma coverage off*/
189 : output logic [7:0] sb_axi_awlen,
190 : /*pragma coverage on*/
191 742 : output logic [2:0] sb_axi_awsize,
192 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
193 : /*pragma coverage off*/
194 : output logic [1:0] sb_axi_awburst,
195 : output logic sb_axi_awlock,
196 : output logic [3:0] sb_axi_awcache,
197 : output logic [2:0] sb_axi_awprot,
198 : output logic [3:0] sb_axi_awqos,
199 : /*pragma coverage on*/
200 :
201 122 : output logic sb_axi_wvalid,
202 122 : input logic sb_axi_wready,
203 89 : output logic [63:0] sb_axi_wdata,
204 772 : output logic [7:0] sb_axi_wstrb,
205 277 : output logic sb_axi_wlast,
206 :
207 122 : input logic sb_axi_bvalid,
208 277 : output logic sb_axi_bready,
209 0 : input logic [1:0] sb_axi_bresp,
210 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,
211 :
212 : // AXI Read Channels
213 620 : output logic sb_axi_arvalid,
214 620 : input logic sb_axi_arready,
215 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
216 : /*pragma coverage off*/
217 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
218 : /*pragma coverage on*/
219 378 : output logic [31:0] sb_axi_araddr,
220 99 : output logic [3:0] sb_axi_arregion,
221 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
222 : /*pragma coverage off*/
223 : output logic [7:0] sb_axi_arlen,
224 : /*pragma coverage on*/
225 742 : output logic [2:0] sb_axi_arsize,
226 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
227 : /*pragma coverage off*/
228 : output logic [1:0] sb_axi_arburst,
229 : output logic sb_axi_arlock,
230 : output logic [3:0] sb_axi_arcache,
231 : output logic [2:0] sb_axi_arprot,
232 : output logic [3:0] sb_axi_arqos,
233 : /*pragma coverage on*/
234 :
235 620 : input logic sb_axi_rvalid,
236 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
237 : /*pragma coverage off*/
238 : output logic sb_axi_rready,
239 : /*pragma coverage on*/
240 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,
241 290 : input logic [63:0] sb_axi_rdata,
242 0 : input logic [1:0] sb_axi_rresp,
243 620 : input logic sb_axi_rlast,
244 :
245 : //-------------------------- DMA AXI signals--------------------------
246 : // AXI Write Channels
247 68 : input logic dma_axi_awvalid,
248 277 : output logic dma_axi_awready,
249 : /* exclude signals that are tied to constant value in tb_top.sv */
250 : /*pragma coverage off*/
251 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
252 : /*pragma coverage on*/
253 276908 : input logic [31:0] dma_axi_awaddr,
254 2243 : input logic [2:0] dma_axi_awsize,
255 276 : input logic [2:0] dma_axi_awprot,
256 0 : input logic [7:0] dma_axi_awlen,
257 276 : input logic [1:0] dma_axi_awburst,
258 :
259 :
260 68 : input logic dma_axi_wvalid,
261 277 : output logic dma_axi_wready,
262 119820 : input logic [63:0] dma_axi_wdata,
263 228231 : input logic [7:0] dma_axi_wstrb,
264 276 : input logic dma_axi_wlast,
265 :
266 68 : output logic dma_axi_bvalid,
267 68 : input logic dma_axi_bready,
268 2 : output logic [1:0] dma_axi_bresp,
269 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
270 :
271 : // AXI Read Channels
272 0 : input logic dma_axi_arvalid,
273 277 : output logic dma_axi_arready,
274 : /* exclude signals that are tied to constant value in tb_top.sv */
275 : /*pragma coverage off*/
276 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
277 : /*pragma coverage on*/
278 276908 : input logic [31:0] dma_axi_araddr,
279 2243 : input logic [2:0] dma_axi_arsize,
280 276 : input logic [2:0] dma_axi_arprot,
281 0 : input logic [7:0] dma_axi_arlen,
282 276 : input logic [1:0] dma_axi_arburst,
283 :
284 0 : output logic dma_axi_rvalid,
285 0 : input logic dma_axi_rready,
286 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
287 33 : output logic [63:0] dma_axi_rdata,
288 2 : output logic [1:0] dma_axi_rresp,
289 277 : output logic dma_axi_rlast,
290 : `endif
291 :
292 : `ifdef RV_BUILD_AHB_LITE
293 : //// AHB LITE BUS
294 5122207 : output logic [31:0] haddr,
295 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
296 : /*pragma coverage off*/
297 : output logic [2:0] hburst,
298 : output logic hmastlock,
299 : /*pragma coverage on*/
300 21 : output logic [3:0] hprot,
301 21 : output logic [2:0] hsize,
302 4952924 : output logic [1:0] htrans,
303 0 : output logic hwrite,
304 :
305 : /* exclude signals that are tied to constant value in this file */
306 : /*pragma coverage off*/
307 : input logic [63:0] hrdata,
308 : input logic hready,
309 : input logic hresp,
310 : /*pragma coverage on*/
311 :
312 : // LSU AHB Master
313 338617 : output logic [31:0] lsu_haddr,
314 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
315 : /*pragma coverage off*/
316 : output logic [2:0] lsu_hburst,
317 : output logic lsu_hmastlock,
318 : /*pragma coverage on*/
319 21 : output logic [3:0] lsu_hprot,
320 185785 : output logic [2:0] lsu_hsize,
321 782073 : output logic [1:0] lsu_htrans,
322 185124 : output logic lsu_hwrite,
323 130699 : output logic [63:0] lsu_hwdata,
324 :
325 : /* exclude signals that are tied to constant value in this file */
326 : /*pragma coverage off*/
327 : input logic [63:0] lsu_hrdata,
328 : input logic lsu_hready,
329 : input logic lsu_hresp,
330 : /*pragma coverage on*/
331 : // Debug Syster Bus AHB
332 384 : output logic [31:0] sb_haddr,
333 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
334 : /*pragma coverage off*/
335 : output logic [2:0] sb_hburst,
336 : output logic sb_hmastlock,
337 : /*pragma coverage on*/
338 21 : output logic [3:0] sb_hprot,
339 117 : output logic [2:0] sb_hsize,
340 774 : output logic [1:0] sb_htrans,
341 119 : output logic sb_hwrite,
342 302 : output logic [63:0] sb_hwdata,
343 :
344 : /* exclude signals that are tied to constant value in this file */
345 : /*pragma coverage off*/
346 : input logic [63:0] sb_hrdata,
347 : input logic sb_hready,
348 : input logic sb_hresp,
349 : /*pragma coverage on*/
350 :
351 : // DMA Slave
352 : /* exclude signals that are tied to constant value in tb_top.sv */
353 : /*pragma coverage off*/
354 : input logic dma_hsel,
355 : input logic [31:0] dma_haddr,
356 : input logic [2:0] dma_hburst,
357 : input logic dma_hmastlock,
358 : input logic [3:0] dma_hprot,
359 : input logic [2:0] dma_hsize,
360 : input logic [1:0] dma_htrans,
361 : input logic dma_hwrite,
362 : input logic [63:0] dma_hwdata,
363 : /*pragma coverage on*/
364 21 : input logic dma_hreadyin,
365 :
366 0 : output logic [63:0] dma_hrdata,
367 21 : output logic dma_hreadyout,
368 0 : output logic dma_hresp,
369 : `endif
370 : // clk ratio signals
371 327 : input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
372 297 : input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
373 297 : input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface
374 297 : input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface
375 :
376 : // ICCM/DCCM ECC status
377 16 : output logic iccm_ecc_single_error,
378 4 : output logic iccm_ecc_double_error,
379 4 : output logic dccm_ecc_single_error,
380 4 : output logic dccm_ecc_double_error,
381 :
382 : // ICache export interface
383 : el2_mem_if.veer_icache_src el2_icache_export,
384 :
385 2 : input logic timer_int,
386 4 : input logic soft_int,
387 21 : input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,
388 :
389 170342 : output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
390 257346 : output logic dec_tlu_perfcnt1,
391 156466 : output logic dec_tlu_perfcnt2,
392 24234 : output logic dec_tlu_perfcnt3,
393 :
394 : // ports added by the soc team
395 1472906 : input logic jtag_tck, // JTAG clk
396 88368 : input logic jtag_tms, // JTAG TMS
397 115250 : input logic jtag_tdi, // JTAG tdi
398 4 : input logic jtag_trst_n, // JTAG Reset
399 111374 : output logic jtag_tdo, // JTAG TDO
400 44176 : output logic jtag_tdoEn, // JTAG Test Data Output enable
401 :
402 0 : input logic [31:4] core_id,
403 :
404 : // Memory Export Interface
405 : el2_mem_if.veer_sram_src el2_mem_export,
406 :
407 : // external MPC halt/run interface
408 114 : input logic mpc_debug_halt_req, // Async halt request
409 114 : input logic mpc_debug_run_req, // Async run request
410 297 : input logic mpc_reset_run_req, // Run/halt after reset
411 114 : output logic mpc_debug_halt_ack, // Halt ack
412 114 : output logic mpc_debug_run_ack, // Run ack
413 2 : output logic debug_brkpt_status, // debug breakpoint
414 :
415 114 : input logic i_cpu_halt_req, // Async halt req to CPU
416 114 : output logic o_cpu_halt_ack, // core response to halt
417 114 : output logic o_cpu_halt_status, // 1'b1 indicates core is halted
418 124 : output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
419 114 : input logic i_cpu_run_req, // Async restart req to CPU
420 114 : output logic o_cpu_run_ack, // Core response to run req
421 :
422 : // Excluding scan_mode and mbist_mode from coverage as their usage is determined by the integrator of the VeeR core.
423 : /* pragma coverage off */
424 : input logic scan_mode, // To enable scan mode
425 : input logic mbist_mode, // to enable mbist
426 :
427 : // DMI port for uncore
428 : input logic dmi_core_enable,
429 : input logic dmi_uncore_enable,
430 : output logic dmi_uncore_en,
431 : output logic dmi_uncore_wr_en,
432 : output logic [ 6:0] dmi_uncore_addr,
433 : output logic [31:0] dmi_uncore_wdata,
434 : input logic [31:0] dmi_uncore_rdata,
435 : output logic dmi_active
436 : /* pragma coverage on */
437 : );
438 :
439 115884880 : logic active_l2clk;
440 115884880 : logic free_l2clk;
441 :
442 : // DCCM ports
443 273904 : logic dccm_wren;
444 620164 : logic dccm_rden;
445 173860 : logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo;
446 173860 : logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi;
447 2097926 : logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo;
448 2365941 : logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi;
449 174952 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo;
450 174952 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi;
451 :
452 429168 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo;
453 429168 : logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi;
454 :
455 : // PIC ports
456 :
457 : // Icache & Itag ports
458 9485644 : logic [31:1] ic_rw_addr;
459 1181806 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en ; // Which way to write
460 1801295 : logic ic_rd_en ;
461 :
462 :
463 1835828 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid; // Valid from the I$ tag valid outside (in flops).
464 :
465 16001 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit; // ic_rd_hit[3:0]
466 0 : logic ic_tag_perr; // Ic tag parity error
467 :
468 50 : logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr; // Read/Write addresss to the Icache.
469 20 : logic ic_debug_rd_en; // Icache debug rd
470 100 : logic ic_debug_wr_en; // Icache debug wr
471 8 : logic ic_debug_tag_array; // Debug tag array
472 300 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way; // Debug way. Rd or Wr.
473 :
474 0 : logic [25:0] ictag_debug_rd_data; // Debug icache tag.
475 3573862 : logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data;
476 10156594 : logic [63:0] ic_rd_data;
477 29199 : logic [70:0] ic_debug_rd_data; // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
478 10 : logic [70:0] ic_debug_wr_data; // Debug wr cache.
479 :
480 6 : logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr; // ecc error per bank
481 0 : logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr; // parity error per bank
482 :
483 8541488 : logic [63:0] ic_premux_data;
484 9154391 : logic ic_sel_premux_data;
485 :
486 : // ICCM ports
487 8827177 : logic [pt.ICCM_BITS-1:1] iccm_rw_addr;
488 124 : logic iccm_wren;
489 133336 : logic iccm_rden;
490 108 : logic [2:0] iccm_wr_size;
491 66 : logic [77:0] iccm_wr_data;
492 16 : logic iccm_buf_correct_ecc;
493 16 : logic iccm_correction_state;
494 :
495 311643 : logic [63:0] iccm_rd_data;
496 319384 : logic [77:0] iccm_rd_data_ecc;
497 :
498 299 : logic core_rst_l; // Core reset including rst_l and dbg_rst_l
499 :
500 2 : logic dccm_clk_override;
501 2 : logic icm_clk_override;
502 8 : logic dec_tlu_core_ecc_disable;
503 :
504 :
505 : // zero out the signals not presented at the wrapper instantiation level
506 : `ifdef RV_BUILD_AXI4
507 : // Since all the signals in this block are tied to constant, we exclude this from coverage analysis
508 : /*pragma coverage off*/
509 :
510 : //// AHB LITE BUS
511 : logic [31:0] haddr;
512 : logic [2:0] hburst;
513 : logic hmastlock;
514 : logic [3:0] hprot;
515 : logic [2:0] hsize;
516 : logic [1:0] htrans;
517 : logic hwrite;
518 :
519 : logic [63:0] hrdata;
520 : logic hready;
521 : logic hresp;
522 :
523 : // LSU AHB Master
524 : logic [31:0] lsu_haddr;
525 : logic [2:0] lsu_hburst;
526 : logic lsu_hmastlock;
527 : logic [3:0] lsu_hprot;
528 : logic [2:0] lsu_hsize;
529 : logic [1:0] lsu_htrans;
530 : logic lsu_hwrite;
531 : logic [63:0] lsu_hwdata;
532 :
533 : logic [63:0] lsu_hrdata;
534 : logic lsu_hready;
535 : logic lsu_hresp;
536 : // Debug Syster Bus AHB
537 : logic [31:0] sb_haddr;
538 : logic [2:0] sb_hburst;
539 : logic sb_hmastlock;
540 : logic [3:0] sb_hprot;
541 : logic [2:0] sb_hsize;
542 : logic [1:0] sb_htrans;
543 : logic sb_hwrite;
544 : logic [63:0] sb_hwdata;
545 :
546 : logic [63:0] sb_hrdata;
547 : logic sb_hready;
548 : logic sb_hresp;
549 :
550 : // DMA Slave
551 : logic dma_hsel;
552 : logic [31:0] dma_haddr;
553 : logic [2:0] dma_hburst;
554 : logic dma_hmastlock;
555 : logic [3:0] dma_hprot;
556 : logic [2:0] dma_hsize;
557 : logic [1:0] dma_htrans;
558 : logic dma_hwrite;
559 : logic [63:0] dma_hwdata;
560 : logic dma_hreadyin;
561 :
562 : logic [63:0] dma_hrdata;
563 : logic dma_hreadyout;
564 : logic dma_hresp;
565 :
566 :
567 :
568 : // AHB
569 : assign hrdata[63:0] = '0;
570 : assign hready = '0;
571 : assign hresp = '0;
572 : // LSU
573 : assign lsu_hrdata[63:0] = '0;
574 : assign lsu_hready = '0;
575 : assign lsu_hresp = '0;
576 : // Debu
577 : assign sb_hrdata[63:0] = '0;
578 : assign sb_hready = '0;
579 : assign sb_hresp = '0;
580 :
581 : // DMA
582 : assign dma_hsel = '0;
583 : assign dma_haddr[31:0] = '0;
584 : assign dma_hburst[2:0] = '0;
585 : assign dma_hmastlock = '0;
586 : assign dma_hprot[3:0] = '0;
587 : assign dma_hsize[2:0] = '0;
588 : assign dma_htrans[1:0] = '0;
589 : assign dma_hwrite = '0;
590 : assign dma_hwdata[63:0] = '0;
591 : assign dma_hreadyin = '0;
592 :
593 : /*pragma coverage on*/
594 :
595 : `endif // `ifdef RV_BUILD_AXI4
596 :
597 :
598 : `ifdef RV_BUILD_AHB_LITE
599 : // Since all the signals in this block are tied to constant, we exclude this from coverage analysis
600 : /*pragma coverage off*/
601 : wire lsu_axi_awvalid;
602 : wire lsu_axi_awready;
603 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid;
604 : wire [31:0] lsu_axi_awaddr;
605 : wire [3:0] lsu_axi_awregion;
606 : wire [7:0] lsu_axi_awlen;
607 : wire [2:0] lsu_axi_awsize;
608 : wire [1:0] lsu_axi_awburst;
609 : wire lsu_axi_awlock;
610 : wire [3:0] lsu_axi_awcache;
611 : wire [2:0] lsu_axi_awprot;
612 : wire [3:0] lsu_axi_awqos;
613 :
614 :
615 : wire lsu_axi_wvalid;
616 : wire lsu_axi_wready;
617 : wire [63:0] lsu_axi_wdata;
618 : wire [7:0] lsu_axi_wstrb;
619 : wire lsu_axi_wlast;
620 :
621 : wire lsu_axi_bvalid;
622 : wire lsu_axi_bready;
623 : wire [1:0] lsu_axi_bresp;
624 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid;
625 :
626 : // AXI Read Channels
627 : wire lsu_axi_arvalid;
628 : wire lsu_axi_arready;
629 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid;
630 : wire [31:0] lsu_axi_araddr;
631 : wire [3:0] lsu_axi_arregion;
632 : wire [7:0] lsu_axi_arlen;
633 : wire [2:0] lsu_axi_arsize;
634 : wire [1:0] lsu_axi_arburst;
635 : wire lsu_axi_arlock;
636 : wire [3:0] lsu_axi_arcache;
637 : wire [2:0] lsu_axi_arprot;
638 : wire [3:0] lsu_axi_arqos;
639 :
640 : wire lsu_axi_rvalid;
641 : wire lsu_axi_rready;
642 : wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid;
643 : wire [63:0] lsu_axi_rdata;
644 : wire [1:0] lsu_axi_rresp;
645 : wire lsu_axi_rlast;
646 :
647 : assign lsu_axi_awready = '0;
648 : assign lsu_axi_wready = '0;
649 : assign lsu_axi_bvalid = '0;
650 : assign lsu_axi_bresp = '0;
651 : assign lsu_axi_bid = {pt.LSU_BUS_TAG{1'b0}};
652 : assign lsu_axi_arready = '0;
653 : assign lsu_axi_rvalid = '0;
654 : assign lsu_axi_rid = {pt.LSU_BUS_TAG{1'b0}};
655 : assign lsu_axi_rdata = '0;
656 : assign lsu_axi_rresp = '0;
657 : assign lsu_axi_rlast = '0;
658 : //-------------------------- IFU AXI signals--------------------------
659 : // AXI Write Channels
660 : wire ifu_axi_awvalid;
661 : wire ifu_axi_awready;
662 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_awid;
663 : wire [31:0] ifu_axi_awaddr;
664 : wire [3:0] ifu_axi_awregion;
665 : wire [7:0] ifu_axi_awlen;
666 : wire [2:0] ifu_axi_awsize;
667 : wire [1:0] ifu_axi_awburst;
668 : wire ifu_axi_awlock;
669 : wire [3:0] ifu_axi_awcache;
670 : wire [2:0] ifu_axi_awprot;
671 : wire [3:0] ifu_axi_awqos;
672 :
673 : wire ifu_axi_wvalid;
674 : wire ifu_axi_wready;
675 : wire [63:0] ifu_axi_wdata;
676 : wire [7:0] ifu_axi_wstrb;
677 : wire ifu_axi_wlast;
678 :
679 : wire ifu_axi_bvalid;
680 : wire ifu_axi_bready;
681 : wire [1:0] ifu_axi_bresp;
682 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_bid;
683 :
684 : // AXI Read Channels
685 : wire ifu_axi_arvalid;
686 : wire ifu_axi_arready;
687 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_arid;
688 : wire [31:0] ifu_axi_araddr;
689 : wire [3:0] ifu_axi_arregion;
690 : wire [7:0] ifu_axi_arlen;
691 : wire [2:0] ifu_axi_arsize;
692 : wire [1:0] ifu_axi_arburst;
693 : wire ifu_axi_arlock;
694 : wire [3:0] ifu_axi_arcache;
695 : wire [2:0] ifu_axi_arprot;
696 : wire [3:0] ifu_axi_arqos;
697 :
698 : wire ifu_axi_rvalid;
699 : wire ifu_axi_rready;
700 : wire [pt.IFU_BUS_TAG-1:0] ifu_axi_rid;
701 : wire [63:0] ifu_axi_rdata;
702 : wire [1:0] ifu_axi_rresp;
703 : wire ifu_axi_rlast;
704 :
705 : assign ifu_axi_bvalid = '0;
706 : assign ifu_axi_bresp = '0;
707 : assign ifu_axi_bid = {pt.IFU_BUS_TAG{1'b0}};
708 : assign ifu_axi_arready = '0;
709 : assign ifu_axi_rvalid = '0;
710 : assign ifu_axi_rid = {pt.IFU_BUS_TAG{1'b0}};
711 : assign ifu_axi_rdata = 0;
712 : assign ifu_axi_rresp = '0;
713 : assign ifu_axi_rlast = '0;
714 : //-------------------------- SB AXI signals--------------------------
715 : // AXI Write Channels
716 : wire sb_axi_awvalid;
717 : wire sb_axi_awready;
718 : wire [pt.SB_BUS_TAG-1:0] sb_axi_awid;
719 : wire [31:0] sb_axi_awaddr;
720 : wire [3:0] sb_axi_awregion;
721 : wire [7:0] sb_axi_awlen;
722 : wire [2:0] sb_axi_awsize;
723 : wire [1:0] sb_axi_awburst;
724 : wire sb_axi_awlock;
725 : wire [3:0] sb_axi_awcache;
726 : wire [2:0] sb_axi_awprot;
727 : wire [3:0] sb_axi_awqos;
728 :
729 : wire sb_axi_wvalid;
730 : wire sb_axi_wready;
731 : wire [63:0] sb_axi_wdata;
732 : wire [7:0] sb_axi_wstrb;
733 : wire sb_axi_wlast;
734 :
735 : wire sb_axi_bvalid;
736 : wire sb_axi_bready;
737 : wire [1:0] sb_axi_bresp;
738 : wire [pt.SB_BUS_TAG-1:0] sb_axi_bid;
739 :
740 : // AXI Read Channels
741 : wire sb_axi_arvalid;
742 : wire sb_axi_arready;
743 : wire [pt.SB_BUS_TAG-1:0] sb_axi_arid;
744 : wire [31:0] sb_axi_araddr;
745 : wire [3:0] sb_axi_arregion;
746 : wire [7:0] sb_axi_arlen;
747 : wire [2:0] sb_axi_arsize;
748 : wire [1:0] sb_axi_arburst;
749 : wire sb_axi_arlock;
750 : wire [3:0] sb_axi_arcache;
751 : wire [2:0] sb_axi_arprot;
752 : wire [3:0] sb_axi_arqos;
753 :
754 : wire sb_axi_rvalid;
755 : wire sb_axi_rready;
756 : wire [pt.SB_BUS_TAG-1:0] sb_axi_rid;
757 : wire [63:0] sb_axi_rdata;
758 : wire [1:0] sb_axi_rresp;
759 : wire sb_axi_rlast;
760 :
761 : assign sb_axi_awready = '0;
762 : assign sb_axi_wready = '0;
763 : assign sb_axi_bvalid = '0;
764 : assign sb_axi_bresp = '0;
765 : assign sb_axi_bid = {pt.SB_BUS_TAG{1'b0}};
766 : assign sb_axi_arready = '0;
767 : assign sb_axi_rvalid = '0;
768 : assign sb_axi_rid = {pt.SB_BUS_TAG{1'b0}};
769 : assign sb_axi_rdata = '0;
770 : assign sb_axi_rresp = '0;
771 : assign sb_axi_rlast = '0;
772 : //-------------------------- DMA AXI signals--------------------------
773 : // AXI Write Channels
774 : wire dma_axi_awvalid;
775 : wire dma_axi_awready;
776 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_awid;
777 : wire [31:0] dma_axi_awaddr;
778 : wire [2:0] dma_axi_awsize;
779 : wire [2:0] dma_axi_awprot;
780 : wire [7:0] dma_axi_awlen;
781 : wire [1:0] dma_axi_awburst;
782 :
783 :
784 : wire dma_axi_wvalid;
785 : wire dma_axi_wready;
786 : wire [63:0] dma_axi_wdata;
787 : wire [7:0] dma_axi_wstrb;
788 : wire dma_axi_wlast;
789 :
790 : assign dma_axi_awvalid = 1'b0;
791 : assign dma_axi_awid = {pt.DMA_BUS_TAG{1'b0}};
792 : assign dma_axi_awaddr = 32'd0;
793 : assign dma_axi_awsize = 3'd0;
794 : assign dma_axi_awprot = 3'd0;
795 : assign dma_axi_awlen = 8'd0;
796 : assign dma_axi_awburst = 2'd0;
797 :
798 :
799 : assign dma_axi_wvalid = 1'b0;
800 : assign dma_axi_wdata = 64'd0;
801 : assign dma_axi_wstrb = 8'd0;
802 : assign dma_axi_wlast = 1'b0;
803 :
804 :
805 : wire dma_axi_bvalid;
806 : wire dma_axi_bready;
807 : wire [1:0] dma_axi_bresp;
808 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_bid;
809 :
810 : assign dma_axi_bready = 1'b0;
811 : // AXI Read Channels
812 : wire dma_axi_arvalid;
813 : wire dma_axi_arready;
814 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_arid;
815 : wire [31:0] dma_axi_araddr;
816 : wire [2:0] dma_axi_arsize;
817 : wire [2:0] dma_axi_arprot;
818 : wire [7:0] dma_axi_arlen;
819 : wire [1:0] dma_axi_arburst;
820 :
821 : assign dma_axi_arvalid = 1'b0;
822 : assign dma_axi_arid = {pt.DMA_BUS_TAG{1'b0}};
823 : assign dma_axi_araddr = 32'd0;
824 : assign dma_axi_arsize = 3'd0;
825 : assign dma_axi_arprot = 3'd0;
826 : assign dma_axi_arlen = 8'd0;
827 : assign dma_axi_arburst = 2'd0;
828 :
829 :
830 :
831 : wire dma_axi_rvalid;
832 : wire dma_axi_rready;
833 : wire [pt.DMA_BUS_TAG-1:0] dma_axi_rid;
834 : wire [63:0] dma_axi_rdata;
835 : wire [1:0] dma_axi_rresp;
836 : wire dma_axi_rlast;
837 :
838 : assign dma_axi_rready = 1'b0;
839 : // AXI
840 : assign ifu_axi_awready = 1'b1;
841 : assign ifu_axi_wready = 1'b1;
842 : assign ifu_axi_bvalid = '0;
843 : assign ifu_axi_bresp[1:0] = '0;
844 : assign ifu_axi_bid[pt.IFU_BUS_TAG-1:0] = '0;
845 :
846 : /*pragma coverage on*/
847 :
848 : `endif // `ifdef RV_BUILD_AHB_LITE
849 :
850 : // DMI (core)
851 16102 : logic dmi_en;
852 4588 : logic [6:0] dmi_addr;
853 6332 : logic dmi_wr_en;
854 3594 : logic [31:0] dmi_wdata;
855 5108 : logic [31:0] dmi_rdata;
856 :
857 : // DMI (core)
858 16102 : logic dmi_reg_en;
859 4588 : logic [6:0] dmi_reg_addr;
860 6332 : logic dmi_reg_wr_en;
861 3594 : logic [31:0] dmi_reg_wdata;
862 5108 : logic [31:0] dmi_reg_rdata;
863 :
864 : // Instantiate the el2_veer core
865 : el2_veer #(.pt(pt)) veer (
866 : .clk(clk),
867 : .*
868 : );
869 :
870 : // Instantiate the mem
871 : el2_mem #(.pt(pt)) mem (
872 : .clk(active_l2clk),
873 : .rst_l(core_rst_l),
874 : .mem_export(el2_mem_export),
875 : .icache_export(el2_icache_export),
876 : .*
877 : );
878 :
879 :
880 : // JTAG/DMI instance
881 : dmi_wrapper dmi_wrapper (
882 : // JTAG signals
883 : .trst_n (jtag_trst_n), // JTAG reset
884 : .tck (jtag_tck), // JTAG clock
885 : .tms (jtag_tms), // Test mode select
886 : .tdi (jtag_tdi), // Test Data Input
887 : .tdo (jtag_tdo), // Test Data Output
888 : .tdoEnable (jtag_tdoEn), // Test Data Output enable
889 : // Processor Signals
890 : .core_rst_n (dbg_rst_l), // Debug reset, active low
891 : .core_clk (clk), // Core clock
892 : .jtag_id (jtag_id), // JTAG ID
893 : .rd_data (dmi_rdata), // Read data from Processor
894 : .reg_wr_data (dmi_wdata), // Write data to Processor
895 : .reg_wr_addr (dmi_addr), // Write address to Processor
896 : .reg_en (dmi_en), // Write interface bit to Processor
897 : .reg_wr_en (dmi_wr_en), // Write enable to Processor
898 : .dmi_hard_reset ()
899 : );
900 :
901 : // DMI core/uncore mux
902 : dmi_mux dmi_mux (
903 : .core_enable (dmi_core_enable),
904 : .uncore_enable (dmi_uncore_enable),
905 :
906 : .dmi_en (dmi_en),
907 : .dmi_wr_en (dmi_wr_en),
908 : .dmi_addr (dmi_addr),
909 : .dmi_wdata (dmi_wdata),
910 : .dmi_rdata (dmi_rdata),
911 :
912 : .dmi_core_en (dmi_reg_en),
913 : .dmi_core_wr_en (dmi_reg_wr_en),
914 : .dmi_core_addr (dmi_reg_addr),
915 : .dmi_core_wdata (dmi_reg_wdata),
916 : .dmi_core_rdata (dmi_reg_rdata),
917 :
918 : .dmi_uncore_en (dmi_uncore_en),
919 : .dmi_uncore_wr_en (dmi_uncore_wr_en),
920 : .dmi_uncore_addr (dmi_uncore_addr),
921 : .dmi_uncore_wdata (dmi_uncore_wdata),
922 : .dmi_uncore_rdata (dmi_uncore_rdata)
923 : );
924 :
925 298 : always_comb dmi_active = dmi_en;
926 :
927 : `ifdef RV_ASSERT_ON
928 : // to avoid internal assertions failure at time 0
929 : initial begin
930 : $assertoff(0, veer);
931 : @(negedge clk) $asserton(0, veer);
932 : end
933 : `endif
934 :
935 : endmodule
|
