Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 : //********************************************************************************
17 : // $Id$
18 : //
19 : // Function: Top level VeeR core file
20 : // Comments:
21 : //
22 : //********************************************************************************
23 : module el2_veer
24 : import el2_pkg::*;
25 : #(
26 : `include "el2_param.vh"
27 : )
28 : (
29 69830461 : input logic clk,
30 338 : input logic rst_l,
31 338 : input logic dbg_rst_l,
32 0 : input logic [31:1] rst_vec,
33 4 : input logic nmi_int,
34 16 : input logic [31:1] nmi_vec,
35 338 : output logic core_rst_l, // This is "rst_l | dbg_rst_l"
36 :
37 69830461 : output logic active_l2clk,
38 69830461 : output logic free_l2clk,
39 :
40 579000 : output logic [31:0] trace_rv_i_insn_ip,
41 339 : output logic [31:0] trace_rv_i_address_ip,
42 6169519 : output logic trace_rv_i_valid_ip,
43 5204 : output logic trace_rv_i_exception_ip,
44 4 : output logic [4:0] trace_rv_i_ecause_ip,
45 24 : output logic trace_rv_i_interrupt_ip,
46 62 : output logic [31:0] trace_rv_i_tval_ip,
47 :
48 :
49 2 : output logic dccm_clk_override,
50 2 : output logic icm_clk_override,
51 8 : output logic dec_tlu_core_ecc_disable,
52 :
53 : // external halt/run interface
54 108 : input logic i_cpu_halt_req, // Asynchronous Halt request to CPU
55 108 : input logic i_cpu_run_req, // Asynchronous Restart request to CPU
56 108 : output logic o_cpu_halt_ack, // Core Acknowledge to Halt request
57 108 : output logic o_cpu_halt_status, // 1'b1 indicates processor is halted
58 108 : output logic o_cpu_run_ack, // Core Acknowledge to run request
59 118 : output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
60 :
61 0 : input logic [31:4] core_id, // CORE ID
62 :
63 : // external MPC halt/run interface
64 108 : input logic mpc_debug_halt_req, // Async halt request
65 108 : input logic mpc_debug_run_req, // Async run request
66 338 : input logic mpc_reset_run_req, // Run/halt after reset
67 108 : output logic mpc_debug_halt_ack, // Halt ack
68 108 : output logic mpc_debug_run_ack, // Run ack
69 2 : output logic debug_brkpt_status, // debug breakpoint
70 :
71 340148 : output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc
72 514626 : output logic dec_tlu_perfcnt1,
73 312914 : output logic dec_tlu_perfcnt2,
74 48468 : output logic dec_tlu_perfcnt3,
75 :
76 : // DCCM ports
77 262894 : output logic dccm_wren,
78 561000 : output logic dccm_rden,
79 18811 : output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo,
80 18811 : output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi,
81 471434 : output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo,
82 677829 : output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi,
83 5376 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
84 5376 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
85 :
86 47176 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
87 47176 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
88 :
89 : // ICCM ports
90 160252 : output logic [pt.ICCM_BITS-1:1] iccm_rw_addr,
91 74 : output logic iccm_wren,
92 133206 : output logic iccm_rden,
93 0 : output logic [2:0] iccm_wr_size,
94 14 : output logic [77:0] iccm_wr_data,
95 8 : output logic iccm_buf_correct_ecc,
96 8 : output logic iccm_correction_state,
97 :
98 136532 : input logic [63:0] iccm_rd_data,
99 161264 : input logic [77:0] iccm_rd_data_ecc,
100 :
101 : // ICache , ITAG ports
102 486 : output logic [31:1] ic_rw_addr,
103 255918 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid,
104 10432 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en,
105 680950 : output logic ic_rd_en,
106 :
107 560509 : output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
108 2136178 : input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
109 231593 : input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
110 0 : input logic [25:0] ictag_debug_rd_data,// Debug icache tag.
111 0 : output logic [70:0] ic_debug_wr_data, // Debug wr cache.
112 :
113 0 : input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,
114 0 : input logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
115 1737756 : output logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
116 5602688 : output logic ic_sel_premux_data, // Select premux data
117 :
118 :
119 0 : output logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
120 0 : output logic ic_debug_rd_en, // Icache debug rd
121 0 : output logic ic_debug_wr_en, // Icache debug wr
122 0 : output logic ic_debug_tag_array, // Debug tag array
123 0 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
124 :
125 :
126 :
127 109586 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,
128 0 : input logic ic_tag_perr, // Icache Tag parity error
129 :
130 : //-------------------------- LSU AXI signals--------------------------
131 : // AXI Write Channels
132 862452 : output logic lsu_axi_awvalid,
133 669068 : input logic lsu_axi_awready,
134 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
135 401 : output logic [31:0] lsu_axi_awaddr,
136 336 : output logic [3:0] lsu_axi_awregion,
137 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
138 : /*verilator coverage_off*/
139 : output logic [7:0] lsu_axi_awlen,
140 : /*verilator coverage_on*/
141 0 : output logic [2:0] lsu_axi_awsize,
142 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
143 : /*verilator coverage_off*/
144 : output logic [1:0] lsu_axi_awburst,
145 : output logic lsu_axi_awlock,
146 : /*verilator coverage_on*/
147 3029 : output logic [3:0] lsu_axi_awcache,
148 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
149 : /*verilator coverage_off*/
150 : output logic [2:0] lsu_axi_awprot,
151 : output logic [3:0] lsu_axi_awqos,
152 : /*verilator coverage_on*/
153 :
154 862452 : output logic lsu_axi_wvalid,
155 669068 : input logic lsu_axi_wready,
156 31437 : output logic [63:0] lsu_axi_wdata,
157 224891 : output logic [7:0] lsu_axi_wstrb,
158 339 : output logic lsu_axi_wlast,
159 :
160 668810 : input logic lsu_axi_bvalid,
161 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
162 : /*verilator coverage_off*/
163 : output logic lsu_axi_bready,
164 : /*verilator coverage_on*/
165 2 : input logic [1:0] lsu_axi_bresp,
166 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
167 :
168 : // AXI Read Channels
169 868564 : output logic lsu_axi_arvalid,
170 673312 : input logic lsu_axi_arready,
171 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
172 401 : output logic [31:0] lsu_axi_araddr,
173 336 : output logic [3:0] lsu_axi_arregion,
174 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
175 : /*verilator coverage_off*/
176 : output logic [7:0] lsu_axi_arlen,
177 : /*verilator coverage_on*/
178 0 : output logic [2:0] lsu_axi_arsize,
179 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
180 : /*verilator coverage_off*/
181 : output logic [1:0] lsu_axi_arburst,
182 : output logic lsu_axi_arlock,
183 : /*verilator coverage_on*/
184 3029 : output logic [3:0] lsu_axi_arcache,
185 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
186 : /*verilator coverage_off*/
187 : output logic [2:0] lsu_axi_arprot,
188 : output logic [3:0] lsu_axi_arqos,
189 : /*verilator coverage_on*/
190 :
191 672996 : input logic lsu_axi_rvalid,
192 : /* exclude signals that are tied to constant value in el2_lsu_bus_buffer.sv */
193 : /*verilator coverage_off*/
194 : output logic lsu_axi_rready,
195 : /*verilator coverage_on*/
196 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
197 26503 : input logic [63:0] lsu_axi_rdata,
198 2 : input logic [1:0] lsu_axi_rresp,
199 673616 : input logic lsu_axi_rlast,
200 :
201 : //-------------------------- IFU AXI signals--------------------------
202 : // AXI Write Channels
203 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
204 : /*verilator coverage_off*/
205 : output logic ifu_axi_awvalid,
206 : /*verilator coverage_on*/
207 20 : input logic ifu_axi_awready,
208 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
209 : /*verilator coverage_off*/
210 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
211 : output logic [31:0] ifu_axi_awaddr,
212 : output logic [3:0] ifu_axi_awregion,
213 : output logic [7:0] ifu_axi_awlen,
214 : output logic [2:0] ifu_axi_awsize,
215 : output logic [1:0] ifu_axi_awburst,
216 : output logic ifu_axi_awlock,
217 : output logic [3:0] ifu_axi_awcache,
218 : output logic [2:0] ifu_axi_awprot,
219 : output logic [3:0] ifu_axi_awqos,
220 :
221 : output logic ifu_axi_wvalid,
222 : /*verilator coverage_on*/
223 20 : input logic ifu_axi_wready,
224 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
225 : /*verilator coverage_off*/
226 : output logic [63:0] ifu_axi_wdata,
227 : output logic [7:0] ifu_axi_wstrb,
228 : output logic ifu_axi_wlast,
229 : /*verilator coverage_on*/
230 :
231 0 : input logic ifu_axi_bvalid,
232 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
233 : /*verilator coverage_off*/
234 : output logic ifu_axi_bready,
235 : /*verilator coverage_on*/
236 0 : input logic [1:0] ifu_axi_bresp,
237 0 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid,
238 :
239 : // AXI Read Channels
240 5891712 : output logic ifu_axi_arvalid,
241 8918851 : input logic ifu_axi_arready,
242 3587996 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
243 2453394 : output logic [31:0] ifu_axi_araddr,
244 545 : output logic [3:0] ifu_axi_arregion,
245 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
246 : /*verilator coverage_off*/
247 : output logic [7:0] ifu_axi_arlen,
248 : output logic [2:0] ifu_axi_arsize,
249 : output logic [1:0] ifu_axi_arburst,
250 : output logic ifu_axi_arlock,
251 : output logic [3:0] ifu_axi_arcache,
252 : output logic [2:0] ifu_axi_arprot,
253 : output logic [3:0] ifu_axi_arqos,
254 : /*verilator coverage_on*/
255 :
256 8918533 : input logic ifu_axi_rvalid,
257 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
258 : /*verilator coverage_off*/
259 : output logic ifu_axi_rready,
260 : /*verilator coverage_on*/
261 897578 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
262 744653 : input logic [63:0] ifu_axi_rdata,
263 20 : input logic [1:0] ifu_axi_rresp,
264 8918533 : input logic ifu_axi_rlast,
265 :
266 : //-------------------------- SB AXI signals--------------------------
267 : // AXI Write Channels
268 244 : output logic sb_axi_awvalid,
269 122 : input logic sb_axi_awready,
270 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
271 : /*verilator coverage_off*/
272 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
273 : /*verilator coverage_on*/
274 4 : output logic [31:0] sb_axi_awaddr,
275 196 : output logic [3:0] sb_axi_awregion,
276 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
277 : /*verilator coverage_off*/
278 : output logic [7:0] sb_axi_awlen,
279 : /*verilator coverage_on*/
280 0 : output logic [2:0] sb_axi_awsize,
281 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
282 : /*verilator coverage_off*/
283 : output logic [1:0] sb_axi_awburst,
284 : output logic sb_axi_awlock,
285 : output logic [3:0] sb_axi_awcache,
286 : output logic [2:0] sb_axi_awprot,
287 : output logic [3:0] sb_axi_awqos,
288 : /*verilator coverage_on*/
289 :
290 244 : output logic sb_axi_wvalid,
291 122 : input logic sb_axi_wready,
292 62 : output logic [63:0] sb_axi_wdata,
293 536 : output logic [7:0] sb_axi_wstrb,
294 339 : output logic sb_axi_wlast,
295 :
296 122 : input logic sb_axi_bvalid,
297 339 : output logic sb_axi_bready,
298 0 : input logic [1:0] sb_axi_bresp,
299 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_bid,
300 :
301 : // AXI Read Channels
302 1504 : output logic sb_axi_arvalid,
303 620 : input logic sb_axi_arready,
304 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
305 : /*verilator coverage_off*/
306 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
307 : /*verilator coverage_on*/
308 4 : output logic [31:0] sb_axi_araddr,
309 196 : output logic [3:0] sb_axi_arregion,
310 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
311 : /*verilator coverage_off*/
312 : output logic [7:0] sb_axi_arlen,
313 : /*verilator coverage_on*/
314 0 : output logic [2:0] sb_axi_arsize,
315 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
316 : /*verilator coverage_off*/
317 : output logic [1:0] sb_axi_arburst,
318 : output logic sb_axi_arlock,
319 : output logic [3:0] sb_axi_arcache,
320 : output logic [2:0] sb_axi_arprot,
321 : output logic [3:0] sb_axi_arqos,
322 : /*verilator coverage_on*/
323 :
324 620 : input logic sb_axi_rvalid,
325 : /* exclude signals that are tied to constant value in dbg/el2_dbg.sv */
326 : /*verilator coverage_off*/
327 : output logic sb_axi_rready,
328 : /*verilator coverage_on*/
329 0 : input logic [pt.SB_BUS_TAG-1:0] sb_axi_rid,
330 3 : input logic [63:0] sb_axi_rdata,
331 0 : input logic [1:0] sb_axi_rresp,
332 620 : input logic sb_axi_rlast,
333 :
334 : //-------------------------- DMA AXI signals--------------------------
335 : // AXI Write Channels
336 66 : input logic dma_axi_awvalid,
337 339 : output logic dma_axi_awready,
338 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid,
339 282 : input logic [31:0] dma_axi_awaddr,
340 0 : input logic [2:0] dma_axi_awsize,
341 0 : input logic [2:0] dma_axi_awprot,
342 0 : input logic [7:0] dma_axi_awlen,
343 0 : input logic [1:0] dma_axi_awburst,
344 :
345 :
346 66 : input logic dma_axi_wvalid,
347 339 : output logic dma_axi_wready,
348 29795 : input logic [63:0] dma_axi_wdata,
349 185761 : input logic [7:0] dma_axi_wstrb,
350 318 : input logic dma_axi_wlast,
351 :
352 66 : output logic dma_axi_bvalid,
353 66 : input logic dma_axi_bready,
354 4 : output logic [1:0] dma_axi_bresp,
355 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_bid,
356 :
357 : // AXI Read Channels
358 0 : input logic dma_axi_arvalid,
359 339 : output logic dma_axi_arready,
360 0 : input logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid,
361 282 : input logic [31:0] dma_axi_araddr,
362 0 : input logic [2:0] dma_axi_arsize,
363 0 : input logic [2:0] dma_axi_arprot,
364 0 : input logic [7:0] dma_axi_arlen,
365 0 : input logic [1:0] dma_axi_arburst,
366 :
367 0 : output logic dma_axi_rvalid,
368 0 : input logic dma_axi_rready,
369 0 : output logic [pt.DMA_BUS_TAG-1:0] dma_axi_rid,
370 12 : output logic [63:0] dma_axi_rdata,
371 4 : output logic [1:0] dma_axi_rresp,
372 339 : output logic dma_axi_rlast,
373 :
374 :
375 : //// AHB LITE BUS
376 17 : output logic [31:0] haddr,
377 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
378 : /*verilator coverage_off*/
379 : output logic [2:0] hburst,
380 : output logic hmastlock,
381 : /*verilator coverage_on*/
382 0 : output logic [3:0] hprot,
383 0 : output logic [2:0] hsize,
384 1442217 : output logic [1:0] htrans,
385 0 : output logic hwrite,
386 :
387 240343 : input logic [63:0] hrdata,
388 20 : input logic hready,
389 0 : input logic hresp,
390 :
391 : // LSU AHB Master
392 119 : output logic [31:0] lsu_haddr,
393 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
394 : /*verilator coverage_off*/
395 : output logic [2:0] lsu_hburst,
396 : output logic lsu_hmastlock,
397 : /*verilator coverage_on*/
398 0 : output logic [3:0] lsu_hprot,
399 0 : output logic [2:0] lsu_hsize,
400 444236 : output logic [1:0] lsu_htrans,
401 88982 : output logic lsu_hwrite,
402 5363 : output logic [63:0] lsu_hwdata,
403 :
404 2309 : input logic [63:0] lsu_hrdata,
405 20 : input logic lsu_hready,
406 0 : input logic lsu_hresp,
407 :
408 : //System Bus Debug Master
409 2 : output logic [31:0] sb_haddr,
410 : /* exclude signals that are tied to constant value in axi4_to_ahb.sv */
411 : /*verilator coverage_off*/
412 : output logic [2:0] sb_hburst,
413 : output logic sb_hmastlock,
414 : /*verilator coverage_on*/
415 0 : output logic [3:0] sb_hprot,
416 0 : output logic [2:0] sb_hsize,
417 1006 : output logic [1:0] sb_htrans,
418 119 : output logic sb_hwrite,
419 39 : output logic [63:0] sb_hwdata,
420 :
421 12 : input logic [63:0] sb_hrdata,
422 2 : input logic sb_hready,
423 0 : input logic sb_hresp,
424 :
425 : // DMA Slave
426 20 : input logic dma_hsel,
427 0 : input logic [31:0] dma_haddr,
428 0 : input logic [2:0] dma_hburst,
429 0 : input logic dma_hmastlock,
430 0 : input logic [3:0] dma_hprot,
431 0 : input logic [2:0] dma_hsize,
432 0 : input logic [1:0] dma_htrans,
433 0 : input logic dma_hwrite,
434 0 : input logic [63:0] dma_hwdata,
435 20 : input logic dma_hreadyin,
436 :
437 0 : output logic [63:0] dma_hrdata,
438 20 : output logic dma_hreadyout,
439 0 : output logic dma_hresp,
440 :
441 338 : input logic lsu_bus_clk_en,
442 338 : input logic ifu_bus_clk_en,
443 338 : input logic dbg_bus_clk_en,
444 338 : input logic dma_bus_clk_en,
445 :
446 16334 : input logic dmi_reg_en, // read or write
447 0 : input logic [6:0] dmi_reg_addr, // address of DM register
448 6018 : input logic dmi_reg_wr_en, // write instruction
449 80 : input logic [31:0] dmi_reg_wdata, // write data
450 108 : output logic [31:0] dmi_reg_rdata,
451 :
452 : // ICCM/DCCM ECC status
453 8 : output logic iccm_ecc_single_error,
454 4 : output logic iccm_ecc_double_error,
455 4 : output logic dccm_ecc_single_error,
456 4 : output logic dccm_ecc_double_error,
457 :
458 0 : input logic [pt.PIC_TOTAL_INT:1] extintsrc_req,
459 12 : input logic timer_int,
460 17 : input logic soft_int,
461 : // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
462 : /*verilator coverage_off*/
463 : input logic scan_mode
464 : /*verilator coverage_on*/
465 : );
466 :
467 :
468 :
469 :
470 192203 : logic [63:0] hwdata_nc;
471 : //----------------------------------------------------------------------
472 : //
473 : //----------------------------------------------------------------------
474 :
475 6199021 : logic ifu_pmu_instr_aligned;
476 0 : logic ifu_ic_error_start;
477 0 : logic ifu_iccm_dma_rd_ecc_single_err;
478 8 : logic ifu_iccm_rd_ecc_single_err;
479 4 : logic ifu_iccm_rd_ecc_double_err;
480 4 : logic lsu_dccm_rd_ecc_single_err;
481 4 : logic lsu_dccm_rd_ecc_double_err;
482 :
483 445118 : logic lsu_axi_awready_ahb;
484 445118 : logic lsu_axi_wready_ahb;
485 206868 : logic lsu_axi_bvalid_ahb;
486 0 : logic lsu_axi_bready_ahb;
487 0 : logic [1:0] lsu_axi_bresp_ahb;
488 0 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_ahb;
489 441056 : logic lsu_axi_arready_ahb;
490 256304 : logic lsu_axi_rvalid_ahb;
491 0 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_ahb;
492 2309 : logic [63:0] lsu_axi_rdata_ahb;
493 0 : logic [1:0] lsu_axi_rresp_ahb;
494 20 : logic lsu_axi_rlast_ahb;
495 :
496 1114186 : logic lsu_axi_awready_int;
497 1114186 : logic lsu_axi_wready_int;
498 875678 : logic lsu_axi_bvalid_int;
499 319 : logic lsu_axi_bready_int;
500 2 : logic [1:0] lsu_axi_bresp_int;
501 0 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_int;
502 1114368 : logic lsu_axi_arready_int;
503 929300 : logic lsu_axi_rvalid_int;
504 0 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid_int;
505 28812 : logic [63:0] lsu_axi_rdata_int;
506 2 : logic [1:0] lsu_axi_rresp_int;
507 673636 : logic lsu_axi_rlast_int;
508 :
509 1442231 : logic ifu_axi_awready_ahb;
510 1442231 : logic ifu_axi_wready_ahb;
511 0 : logic ifu_axi_bvalid_ahb;
512 0 : logic ifu_axi_bready_ahb;
513 0 : logic [1:0] ifu_axi_bresp_ahb;
514 284396 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid_ahb;
515 1442231 : logic ifu_axi_arready_ahb;
516 2884426 : logic ifu_axi_rvalid_ahb;
517 284396 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid_ahb;
518 240342 : logic [63:0] ifu_axi_rdata_ahb;
519 0 : logic [1:0] ifu_axi_rresp_ahb;
520 20 : logic ifu_axi_rlast_ahb;
521 :
522 1442231 : logic ifu_axi_awready_int;
523 1442231 : logic ifu_axi_wready_int;
524 0 : logic ifu_axi_bvalid_int;
525 0 : logic ifu_axi_bready_int;
526 0 : logic [1:0] ifu_axi_bresp_int;
527 284396 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_bid_int;
528 10361082 : logic ifu_axi_arready_int;
529 11802959 : logic ifu_axi_rvalid_int;
530 1181974 : logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid_int;
531 984995 : logic [63:0] ifu_axi_rdata_int;
532 20 : logic [1:0] ifu_axi_rresp_int;
533 8918553 : logic ifu_axi_rlast_int;
534 :
535 1026 : logic sb_axi_awready_ahb;
536 1026 : logic sb_axi_wready_ahb;
537 122 : logic sb_axi_bvalid_ahb;
538 0 : logic sb_axi_bready_ahb;
539 0 : logic [1:0] sb_axi_bresp_ahb;
540 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_bid_ahb;
541 1026 : logic sb_axi_arready_ahb;
542 884 : logic sb_axi_rvalid_ahb;
543 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_rid_ahb;
544 12 : logic [63:0] sb_axi_rdata_ahb;
545 0 : logic [1:0] sb_axi_rresp_ahb;
546 20 : logic sb_axi_rlast_ahb;
547 :
548 1148 : logic sb_axi_awready_int;
549 1148 : logic sb_axi_wready_int;
550 244 : logic sb_axi_bvalid_int;
551 319 : logic sb_axi_bready_int;
552 0 : logic [1:0] sb_axi_bresp_int;
553 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_bid_int;
554 1646 : logic sb_axi_arready_int;
555 1504 : logic sb_axi_rvalid_int;
556 0 : logic [pt.SB_BUS_TAG-1:0] sb_axi_rid_int;
557 15 : logic [63:0] sb_axi_rdata_int;
558 0 : logic [1:0] sb_axi_rresp_int;
559 640 : logic sb_axi_rlast_int;
560 :
561 0 : logic dma_axi_awvalid_ahb;
562 : /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
563 : /*verilator coverage_off*/
564 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_ahb;
565 : /*verilator coverage_on*/
566 0 : logic [31:0] dma_axi_awaddr_ahb;
567 0 : logic [2:0] dma_axi_awsize_ahb;
568 : /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
569 : /*verilator coverage_off*/
570 : logic [2:0] dma_axi_awprot_ahb;
571 : logic [7:0] dma_axi_awlen_ahb;
572 : logic [1:0] dma_axi_awburst_ahb;
573 : /*verilator coverage_on*/
574 0 : logic dma_axi_wvalid_ahb;
575 0 : logic [63:0] dma_axi_wdata_ahb;
576 0 : logic [7:0] dma_axi_wstrb_ahb;
577 : /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
578 : /*verilator coverage_off*/
579 : logic dma_axi_wlast_ahb;
580 : logic dma_axi_bready_ahb;
581 : /*verilator coverage_on*/
582 0 : logic dma_axi_arvalid_ahb;
583 : /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
584 : /*verilator coverage_off*/
585 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid_ahb;
586 : /*verilator coverage_on*/
587 0 : logic [31:0] dma_axi_araddr_ahb;
588 0 : logic [2:0] dma_axi_arsize_ahb;
589 : /* exclude signals that are tied to constant value in ahb_to_axi4.sv */
590 : /*verilator coverage_off*/
591 : logic [2:0] dma_axi_arprot_ahb;
592 : logic [7:0] dma_axi_arlen_ahb;
593 : logic [1:0] dma_axi_arburst_ahb;
594 : logic dma_axi_rready_ahb;
595 : /*verilator coverage_on*/
596 :
597 66 : logic dma_axi_awvalid_int;
598 0 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_awid_int;
599 282 : logic [31:0] dma_axi_awaddr_int;
600 0 : logic [2:0] dma_axi_awsize_int;
601 0 : logic [2:0] dma_axi_awprot_int;
602 0 : logic [7:0] dma_axi_awlen_int;
603 0 : logic [1:0] dma_axi_awburst_int;
604 66 : logic dma_axi_wvalid_int;
605 29795 : logic [63:0] dma_axi_wdata_int;
606 185761 : logic [7:0] dma_axi_wstrb_int;
607 338 : logic dma_axi_wlast_int;
608 86 : logic dma_axi_bready_int;
609 0 : logic dma_axi_arvalid_int;
610 0 : logic [pt.DMA_BUS_TAG-1:0] dma_axi_arid_int;
611 282 : logic [31:0] dma_axi_araddr_int;
612 0 : logic [2:0] dma_axi_arsize_int;
613 0 : logic [2:0] dma_axi_arprot_int;
614 0 : logic [7:0] dma_axi_arlen_int;
615 0 : logic [1:0] dma_axi_arburst_int;
616 20 : logic dma_axi_rready_int;
617 :
618 :
619 : // Icache debug
620 0 : logic [70:0] ifu_ic_debug_rd_data; // diagnostic icache read data
621 0 : logic ifu_ic_debug_rd_data_valid; // diagnostic icache read data valid
622 0 : el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
623 :
624 :
625 5138059 : logic dec_i0_rs1_en_d;
626 3571415 : logic dec_i0_rs2_en_d;
627 407926 : logic [31:0] gpr_i0_rs1_d;
628 598738 : logic [31:0] gpr_i0_rs2_d;
629 :
630 314095 : logic [31:0] dec_i0_result_r;
631 614631 : logic [31:0] exu_i0_result_x;
632 339 : logic [31:1] exu_i0_pc_x;
633 344 : logic [31:1] exu_npc_r;
634 :
635 1460 : el2_alu_pkt_t i0_ap;
636 :
637 : // Trigger signals
638 0 : el2_trigger_pkt_t [3:0] trigger_pkt_any;
639 0 : logic [3:0] lsu_trigger_match_m;
640 :
641 :
642 2171149 : logic [31:0] dec_i0_immed_d;
643 123424 : logic [12:1] dec_i0_br_immed_d;
644 555531 : logic dec_i0_select_pc_d;
645 :
646 1321 : logic [31:1] dec_i0_pc_d;
647 80550 : logic [3:0] dec_i0_rs1_bypass_en_d;
648 8620 : logic [3:0] dec_i0_rs2_bypass_en_d;
649 :
650 5410176 : logic dec_i0_alu_decode_d;
651 3885446 : logic dec_i0_branch_d;
652 :
653 5890925 : logic ifu_miss_state_idle;
654 232 : logic dec_tlu_flush_noredir_r;
655 2 : logic dec_tlu_flush_leak_one_r;
656 8 : logic dec_tlu_flush_err_r;
657 6013735 : logic ifu_i0_valid;
658 468714 : logic [31:0] ifu_i0_instr;
659 1321 : logic [31:1] ifu_i0_pc;
660 :
661 673895 : logic exu_flush_final;
662 :
663 227514 : logic [31:1] exu_flush_path_final;
664 :
665 413533 : logic [31:0] exu_lsu_rs1_d;
666 81504 : logic [31:0] exu_lsu_rs2_d;
667 :
668 :
669 623733 : el2_lsu_pkt_t lsu_p;
670 5492615 : logic dec_qual_lsu_d;
671 :
672 2283261 : logic dec_lsu_valid_raw_d;
673 270454 : logic [11:0] dec_lsu_offset_d;
674 :
675 45313 : logic [31:0] lsu_result_m;
676 36052 : logic [31:0] lsu_result_corr_r; // This is the ECC corrected data going to RF
677 4 : logic lsu_single_ecc_error_incr; // Increment the ecc counter
678 4 : el2_lsu_error_pkt_t lsu_error_pkt_r;
679 2 : logic lsu_imprecise_error_load_any;
680 2 : logic lsu_imprecise_error_store_any;
681 401 : logic [31:0] lsu_imprecise_error_addr_any;
682 48822 : logic lsu_load_stall_any; // This is for blocking loads
683 59146 : logic lsu_store_stall_any; // This is for blocking stores
684 1346584 : logic lsu_idle_any; // doesn't include DMA
685 1346245 : logic lsu_active; // lsu is active. used for clock
686 :
687 :
688 24696 : logic [31:1] lsu_fir_addr; // fast interrupt address
689 0 : logic [1:0] lsu_fir_error; // Error during fast interrupt lookup
690 :
691 : // Non-blocking loads
692 881246 : logic lsu_nonblock_load_valid_m;
693 504987 : logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m;
694 0 : logic lsu_nonblock_load_inv_r;
695 504984 : logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r;
696 920472 : logic lsu_nonblock_load_data_valid;
697 36572 : logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag;
698 71596 : logic [31:0] lsu_nonblock_load_data;
699 :
700 77218 : logic dec_csr_ren_d;
701 9105 : logic [31:0] dec_csr_rddata_d;
702 :
703 3978 : logic [31:0] exu_csr_rs1_x;
704 :
705 6168799 : logic dec_tlu_i0_commit_cmt;
706 59234 : logic dec_tlu_flush_lower_r;
707 59234 : logic dec_tlu_flush_lower_wb;
708 29690 : logic dec_tlu_i0_kill_writeb_r; // I0 is flushed, don't writeback any results to arch state
709 18868 : logic dec_tlu_fence_i_r; // flush is a fence_i rfnpc, flush icache
710 :
711 24762 : logic [31:1] dec_tlu_flush_path_r;
712 0 : logic [31:0] dec_tlu_mrac_ff; // CSR for memory region control
713 :
714 5773026 : logic ifu_i0_pc4;
715 :
716 0 : el2_mul_pkt_t mul_p;
717 :
718 78134 : el2_div_pkt_t div_p;
719 2628 : logic dec_div_cancel;
720 :
721 24784 : logic [31:0] exu_div_result;
722 156860 : logic exu_div_wren;
723 :
724 6199021 : logic dec_i0_decode_d;
725 :
726 :
727 138775 : logic [31:1] pred_correct_npc_x;
728 :
729 782169 : el2_br_tlu_pkt_t dec_tlu_br0_r_pkt;
730 :
731 34480 : el2_predict_pkt_t exu_mp_pkt;
732 300000 : logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr;
733 379001 : logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr;
734 196114 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index;
735 115620 : logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag;
736 :
737 367125 : logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r;
738 2722757 : logic [1:0] exu_i0_br_hist_r;
739 26468 : logic exu_i0_br_error_r;
740 9608 : logic exu_i0_br_start_error_r;
741 3014213 : logic exu_i0_br_valid_r;
742 410449 : logic exu_i0_br_mp_r;
743 2381224 : logic exu_i0_br_middle_r;
744 :
745 2110866 : logic exu_i0_br_way_r;
746 :
747 187568 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r;
748 :
749 0 : logic dma_dccm_req;
750 66 : logic dma_iccm_req;
751 12 : logic [2:0] dma_mem_tag;
752 0 : logic [31:0] dma_mem_addr;
753 0 : logic [2:0] dma_mem_sz;
754 22 : logic dma_mem_write;
755 12 : logic [63:0] dma_mem_wdata;
756 :
757 0 : logic dccm_dma_rvalid;
758 4 : logic dccm_dma_ecc_error;
759 12 : logic [2:0] dccm_dma_rtag;
760 39564 : logic [63:0] dccm_dma_rdata;
761 0 : logic iccm_dma_rvalid;
762 4 : logic iccm_dma_ecc_error;
763 12 : logic [2:0] iccm_dma_rtag;
764 0 : logic [63:0] iccm_dma_rdata;
765 :
766 0 : logic dma_dccm_stall_any; // Stall the ld/st in decode if asserted
767 26 : logic dma_iccm_stall_any; // Stall the fetch
768 2232486 : logic dccm_ready;
769 638035 : logic iccm_ready;
770 :
771 0 : logic dma_pmu_dccm_read;
772 0 : logic dma_pmu_dccm_write;
773 0 : logic dma_pmu_any_read;
774 66 : logic dma_pmu_any_write;
775 :
776 208 : logic ifu_i0_icaf;
777 274 : logic [1:0] ifu_i0_icaf_type;
778 :
779 :
780 86 : logic ifu_i0_icaf_second;
781 2 : logic ifu_i0_dbecc;
782 0 : logic iccm_dma_sb_error;
783 :
784 206047 : el2_br_pkt_t i0_brp;
785 651101 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index;
786 630514 : logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr;
787 21223 : logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag;
788 :
789 0 : logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index;
790 0 : logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index; // Fully associative btb error index
791 :
792 :
793 506276 : el2_predict_pkt_t dec_i0_predict_p_d;
794 :
795 630514 : logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d; // DEC predict fghr
796 651101 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d; // DEC predict index
797 21223 : logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d; // DEC predict branch tag
798 :
799 : // PIC ports
800 8 : logic picm_wren;
801 2 : logic picm_rden;
802 10 : logic picm_mken;
803 435 : logic [31:0] picm_rdaddr;
804 435 : logic [31:0] picm_wraddr;
805 92722 : logic [31:0] picm_wr_data;
806 0 : logic [31:0] picm_rd_data;
807 :
808 : // feature disable from mfdc
809 0 : logic dec_tlu_external_ldfwd_disable; // disable external load forwarding
810 0 : logic dec_tlu_bpred_disable;
811 6 : logic dec_tlu_wb_coalescing_disable;
812 322 : logic dec_tlu_sideeffect_posted_disable;
813 345 : logic [2:0] dec_tlu_dma_qos_prty; // DMA QoS priority coming from MFDC [18:16]
814 :
815 : // clock gating overrides from mcgc
816 2 : logic dec_tlu_misc_clk_override;
817 2 : logic dec_tlu_ifu_clk_override;
818 2 : logic dec_tlu_lsu_clk_override;
819 2 : logic dec_tlu_bus_clk_override;
820 2 : logic dec_tlu_pic_clk_override;
821 2 : logic dec_tlu_dccm_clk_override;
822 2 : logic dec_tlu_icm_clk_override;
823 :
824 341 : logic dec_tlu_picio_clk_override;
825 :
826 : assign dccm_clk_override = dec_tlu_dccm_clk_override; // dccm memory
827 : assign icm_clk_override = dec_tlu_icm_clk_override; // icache/iccm memory
828 :
829 : // PMP Signals
830 0 : el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES];
831 : logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES];
832 593787 : logic [31:0] pmp_chan_addr [3];
833 0 : el2_pmp_type_pkt_t pmp_chan_type [3];
834 137020 : logic pmp_chan_err [3];
835 :
836 440 : logic [31:1] ifu_pmp_addr;
837 110 : logic ifu_pmp_error;
838 593765 : logic [31:0] lsu_pmp_addr_start;
839 166874 : logic lsu_pmp_error_start;
840 593791 : logic [31:0] lsu_pmp_addr_end;
841 166874 : logic lsu_pmp_error_end;
842 1072759 : logic lsu_pmp_we;
843 1423948 : logic lsu_pmp_re;
844 :
845 : // -----------------------DEBUG START -------------------------------
846 :
847 6 : logic [31:0] dbg_cmd_addr; // the address of the debug command to used by the core
848 126 : logic [31:0] dbg_cmd_wrdata; // If the debug command is a write command, this has the data to be written to the CSR/GPR
849 2382 : logic dbg_cmd_valid; // commad is being driven by the dbg module. One pulse. Only dirven when core_halted has been seen
850 272 : logic dbg_cmd_write; // 1: write command; 0: read_command
851 1456 : logic [1:0] dbg_cmd_type; // 0:gpr 1:csr 2: memory
852 1162 : logic [1:0] dbg_cmd_size; // size of the abstract mem access debug command
853 8 : logic dbg_halt_req; // Sticky signal indicating that the debug module wants to start the entering of debug mode ( start the halting sequence )
854 10 : logic dbg_resume_req; // Sticky signal indicating that the debug module wants to resume from debug mode
855 339 : logic dbg_core_rst_l; // Core reset from DM
856 :
857 2382 : logic core_dbg_cmd_done; // Final muxed cmd done to debug
858 4 : logic core_dbg_cmd_fail; // Final muxed cmd done to debug
859 314095 : logic [31:0] core_dbg_rddata; // Final muxed cmd done to debug
860 :
861 4 : logic dma_dbg_cmd_done; // Abstarct memory command sent to dma is done
862 4 : logic dma_dbg_cmd_fail; // Abstarct memory command sent to dma failed
863 0 : logic [31:0] dma_dbg_rddata; // Read data for abstract memory access
864 :
865 2382 : logic dbg_dma_bubble; // Debug needs a bubble to send a valid
866 2382 : logic dma_dbg_ready; // DMA is ready to accept debug request
867 :
868 314095 : logic [31:0] dec_dbg_rddata; // The core drives this data ( intercepts the pipe and sends it here )
869 2378 : logic dec_dbg_cmd_done; // This will be treated like a valid signal
870 0 : logic dec_dbg_cmd_fail; // Abstract command failed
871 108 : logic dec_tlu_mpc_halted_only; // Only halted due to MPC
872 120 : logic dec_tlu_dbg_halted; // The core has finished the queiscing sequence. Sticks this signal high
873 10 : logic dec_tlu_resume_ack;
874 118 : logic dec_tlu_debug_mode; // Core is in debug mode
875 58 : logic dec_debug_wdata_rs1_d;
876 0 : logic dec_tlu_force_halt; // halt has been forced
877 :
878 6198405 : logic [1:0] dec_data_en;
879 5993280 : logic [1:0] dec_ctl_en;
880 :
881 : // PMU Signals
882 410449 : logic exu_pmu_i0_br_misp;
883 2912102 : logic exu_pmu_i0_br_ataken;
884 3496530 : logic exu_pmu_i0_pc4;
885 :
886 891386 : logic lsu_pmu_load_external_m;
887 813400 : logic lsu_pmu_store_external_m;
888 48802 : logic lsu_pmu_misaligned_m;
889 1673968 : logic lsu_pmu_bus_trxn;
890 36422 : logic lsu_pmu_bus_misaligned;
891 4 : logic lsu_pmu_bus_error;
892 67776 : logic lsu_pmu_bus_busy;
893 :
894 614838 : logic ifu_pmu_fetch_stall;
895 5891918 : logic ifu_pmu_ic_miss;
896 745252 : logic ifu_pmu_ic_hit;
897 10 : logic ifu_pmu_bus_error;
898 4468853 : logic ifu_pmu_bus_busy;
899 10360750 : logic ifu_pmu_bus_trxn;
900 :
901 449 : logic active_state;
902 69830461 : logic free_clk;
903 69830461 : logic active_clk;
904 2 : logic dec_pause_state_cg;
905 :
906 2 : logic lsu_nonblock_load_data_error;
907 :
908 1428046 : logic [15:0] ifu_i0_cinst;
909 :
910 : // fast interrupt
911 0 : logic [31:2] dec_tlu_meihap;
912 0 : logic dec_extint_stall;
913 :
914 5521867 : el2_trace_pkt_t trace_rv_trace_pkt;
915 :
916 :
917 4 : logic lsu_fastint_stall_any;
918 :
919 0 : logic [7:0] pic_claimid;
920 0 : logic [3:0] pic_pl, dec_tlu_meicurpl, dec_tlu_meipt;
921 0 : logic mexintpend;
922 0 : logic mhwakeup;
923 :
924 70 : logic dma_active;
925 :
926 :
927 2 : logic pause_state;
928 108 : logic halt_state;
929 :
930 2090832 : logic dec_tlu_core_empty;
931 :
932 : assign pause_state = dec_pause_state_cg & ~(dma_active | lsu_active) & dec_tlu_core_empty;
933 :
934 : assign halt_state = o_cpu_halt_status & ~(dma_active | lsu_active);
935 :
936 :
937 : assign active_state = (~(halt_state | pause_state) | dec_tlu_flush_lower_r | dec_tlu_flush_lower_wb) | dec_tlu_misc_clk_override;
938 :
939 : rvoclkhdr free_cg2 ( .clk(clk), .en(1'b1), .l1clk(free_l2clk), .* );
940 : rvoclkhdr active_cg2 ( .clk(clk), .en(active_state), .l1clk(active_l2clk), .* );
941 :
942 : // all other clock headers are 1st level
943 : rvoclkhdr free_cg1 ( .clk(free_l2clk), .en(1'b1), .l1clk(free_clk), .* );
944 : rvoclkhdr active_cg1 ( .clk(active_l2clk), .en(1'b1), .l1clk(active_clk), .* );
945 :
946 :
947 : assign core_dbg_cmd_done = dma_dbg_cmd_done | dec_dbg_cmd_done;
948 : assign core_dbg_cmd_fail = dma_dbg_cmd_fail | dec_dbg_cmd_fail;
949 : assign core_dbg_rddata[31:0] = dma_dbg_cmd_done ? dma_dbg_rddata[31:0] : dec_dbg_rddata[31:0];
950 :
951 : el2_dbg #(.pt(pt)) dbg (
952 : .rst_l(core_rst_l),
953 : .clk(free_l2clk),
954 : .clk_override(dec_tlu_misc_clk_override),
955 :
956 : // AXI signals
957 : .sb_axi_awready(sb_axi_awready_int),
958 : .sb_axi_wready(sb_axi_wready_int),
959 : .sb_axi_bvalid(sb_axi_bvalid_int),
960 : .sb_axi_bresp(sb_axi_bresp_int[1:0]),
961 :
962 : .sb_axi_arready(sb_axi_arready_int),
963 : .sb_axi_rvalid(sb_axi_rvalid_int),
964 : .sb_axi_rdata(sb_axi_rdata_int[63:0]),
965 : .sb_axi_rresp(sb_axi_rresp_int[1:0]),
966 : .*
967 : );
968 :
969 : `ifdef RV_ASSERT_ON
970 : assert_fetch_indbghalt: assert #0 (~(ifu.ifc_fetch_req_f & dec.tlu.dbg_tlu_halted_f & ~dec.tlu.dcsr_single_step_running)) else $display("ERROR: Fetching in dBG halt!");
971 : `endif
972 :
973 : // ----------------- DEBUG END -----------------------------
974 :
975 : assign core_rst_l = rst_l & (dbg_core_rst_l | scan_mode);
976 :
977 : `ifdef RV_USER_MODE
978 :
979 : // Operating privilege mode, 0 - machine, 1 - user
980 864 : logic priv_mode;
981 : // Effective privilege mode, 0 - machine, 1 - user (driven in el2_dec_tlu_ctl.sv)
982 958 : logic priv_mode_eff;
983 : // Next privilege mode
984 864 : logic priv_mode_ns;
985 :
986 2 : el2_mseccfg_pkt_t mseccfg; // mseccfg CSR for PMP
987 :
988 : `endif
989 :
990 : // fetch
991 : el2_ifu #(.pt(pt)) ifu (
992 : .clk(active_l2clk),
993 : .rst_l(core_rst_l),
994 : .dec_tlu_flush_err_wb (dec_tlu_flush_err_r ),
995 : .dec_tlu_flush_noredir_wb (dec_tlu_flush_noredir_r ),
996 : .dec_tlu_fence_i_wb (dec_tlu_fence_i_r ),
997 : .dec_tlu_flush_leak_one_wb (dec_tlu_flush_leak_one_r ),
998 : .dec_tlu_flush_lower_wb (dec_tlu_flush_lower_r ),
999 :
1000 : // AXI signals
1001 : .ifu_axi_arready(ifu_axi_arready_int),
1002 : .ifu_axi_rvalid(ifu_axi_rvalid_int),
1003 : .ifu_axi_rid(ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0]),
1004 : .ifu_axi_rdata(ifu_axi_rdata_int[63:0]),
1005 : .ifu_axi_rresp(ifu_axi_rresp_int[1:0]),
1006 :
1007 : .*
1008 : );
1009 :
1010 :
1011 : assign iccm_ecc_single_error = ifu_iccm_rd_ecc_single_err || ifu_iccm_dma_rd_ecc_single_err;
1012 : assign iccm_ecc_double_error = ifu_iccm_rd_ecc_double_err;
1013 :
1014 : el2_dec #(.pt(pt)) dec (
1015 : .clk(active_l2clk),
1016 : .dbg_cmd_wrdata(dbg_cmd_wrdata[1:0]),
1017 : .rst_l(core_rst_l),
1018 : .*
1019 : );
1020 :
1021 : el2_exu #(.pt(pt)) exu (
1022 : .clk(active_l2clk),
1023 : .rst_l(core_rst_l),
1024 : .*
1025 : );
1026 :
1027 : el2_lsu #(.pt(pt)) lsu (
1028 : .clk(active_l2clk),
1029 : .rst_l(core_rst_l),
1030 : .clk_override(dec_tlu_lsu_clk_override),
1031 : .dec_tlu_i0_kill_writeb_r(dec_tlu_i0_kill_writeb_r),
1032 :
1033 : // AXI signals
1034 : .lsu_axi_awready(lsu_axi_awready_int),
1035 : .lsu_axi_wready(lsu_axi_wready_int),
1036 : .lsu_axi_bvalid(lsu_axi_bvalid_int),
1037 : .lsu_axi_bid(lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0]),
1038 : .lsu_axi_bresp(lsu_axi_bresp_int[1:0]),
1039 :
1040 : .lsu_axi_arready(lsu_axi_arready_int),
1041 : .lsu_axi_rvalid(lsu_axi_rvalid_int),
1042 : .lsu_axi_rid(lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0]),
1043 : .lsu_axi_rdata(lsu_axi_rdata_int[63:0]),
1044 : .lsu_axi_rresp(lsu_axi_rresp_int[1:0]),
1045 : .lsu_axi_rlast(lsu_axi_rlast_int),
1046 :
1047 : .*
1048 :
1049 : );
1050 :
1051 : assign dccm_ecc_single_error = lsu_dccm_rd_ecc_single_err;
1052 : assign dccm_ecc_double_error = lsu_dccm_rd_ecc_double_err;
1053 :
1054 : el2_pic_ctrl #(.pt(pt)) pic_ctrl_inst (
1055 : .clk(free_l2clk),
1056 : .clk_override(dec_tlu_pic_clk_override),
1057 : .io_clk_override(dec_tlu_picio_clk_override),
1058 : .picm_mken (picm_mken),
1059 : .extintsrc_req({extintsrc_req[pt.PIC_TOTAL_INT:1],1'b0}),
1060 : .pl(pic_pl[3:0]),
1061 : .claimid(pic_claimid[7:0]),
1062 : .meicurpl(dec_tlu_meicurpl[3:0]),
1063 : .meipt(dec_tlu_meipt[3:0]),
1064 : .rst_l(core_rst_l),
1065 : .*);
1066 :
1067 : el2_dma_ctrl #(.pt(pt)) dma_ctrl (
1068 : .clk(free_l2clk),
1069 : .rst_l(core_rst_l),
1070 : .clk_override(dec_tlu_misc_clk_override),
1071 :
1072 : // AXI signals
1073 : .dma_axi_awvalid(dma_axi_awvalid_int),
1074 : .dma_axi_awid(dma_axi_awid_int[pt.DMA_BUS_TAG-1:0]),
1075 : .dma_axi_awaddr(dma_axi_awaddr_int[31:0]),
1076 : .dma_axi_awsize(dma_axi_awsize_int[2:0]),
1077 : .dma_axi_wvalid(dma_axi_wvalid_int),
1078 : .dma_axi_wdata(dma_axi_wdata_int[63:0]),
1079 : .dma_axi_wstrb(dma_axi_wstrb_int[7:0]),
1080 : .dma_axi_bready(dma_axi_bready_int),
1081 :
1082 : .dma_axi_arvalid(dma_axi_arvalid_int),
1083 : .dma_axi_arid(dma_axi_arid_int[pt.DMA_BUS_TAG-1:0]),
1084 : .dma_axi_araddr(dma_axi_araddr_int[31:0]),
1085 : .dma_axi_arsize(dma_axi_arsize_int[2:0]),
1086 : .dma_axi_rready(dma_axi_rready_int),
1087 :
1088 : .*
1089 : );
1090 :
1091 : assign pmp_chan_addr[0] = {ifu_pmp_addr, 1'b0};
1092 : assign pmp_chan_type[0] = EXEC;
1093 : assign ifu_pmp_error = pmp_chan_err[0];
1094 : assign pmp_chan_addr[1] = lsu_pmp_addr_start;
1095 : assign pmp_chan_type[1] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
1096 : assign lsu_pmp_error_start = pmp_chan_err[1];
1097 : assign pmp_chan_addr[2] = lsu_pmp_addr_end;
1098 : assign pmp_chan_type[2] = lsu_pmp_we ? WRITE : (lsu_pmp_re ? READ : NONE);
1099 : assign lsu_pmp_error_end = pmp_chan_err[2];
1100 :
1101 : el2_pmp #(
1102 : .PMP_CHANNELS(3),
1103 : .pt(pt)
1104 : ) pmp (
1105 : .clk (active_l2clk),
1106 : .rst_l(core_rst_l),
1107 : .*
1108 : );
1109 :
1110 : if (pt.BUILD_AHB_LITE == 1) begin: Gen_AXI_To_AHB
1111 :
1112 : // AXI4 -> AHB Gasket for LSU
1113 : axi4_to_ahb #(.pt(pt),
1114 : .TAG(pt.LSU_BUS_TAG)) lsu_axi4_to_ahb (
1115 :
1116 : .clk(free_l2clk),
1117 : .free_clk(free_clk),
1118 : .rst_l(core_rst_l),
1119 : .clk_override(dec_tlu_bus_clk_override),
1120 : .bus_clk_en(lsu_bus_clk_en),
1121 : .dec_tlu_force_halt(dec_tlu_force_halt),
1122 :
1123 : // AXI Write Channels
1124 : .axi_awvalid(lsu_axi_awvalid),
1125 : .axi_awready(lsu_axi_awready_ahb),
1126 : .axi_awid(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]),
1127 : .axi_awaddr(lsu_axi_awaddr[31:0]),
1128 : .axi_awsize(lsu_axi_awsize[2:0]),
1129 : .axi_awprot(lsu_axi_awprot[2:0]),
1130 :
1131 : .axi_wvalid(lsu_axi_wvalid),
1132 : .axi_wready(lsu_axi_wready_ahb),
1133 : .axi_wdata(lsu_axi_wdata[63:0]),
1134 : .axi_wstrb(lsu_axi_wstrb[7:0]),
1135 : .axi_wlast(lsu_axi_wlast),
1136 :
1137 : .axi_bvalid(lsu_axi_bvalid_ahb),
1138 : .axi_bready(lsu_axi_bready),
1139 : .axi_bresp(lsu_axi_bresp_ahb[1:0]),
1140 : .axi_bid(lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0]),
1141 :
1142 : // AXI Read Channels
1143 : .axi_arvalid(lsu_axi_arvalid),
1144 : .axi_arready(lsu_axi_arready_ahb),
1145 : .axi_arid(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]),
1146 : .axi_araddr(lsu_axi_araddr[31:0]),
1147 : .axi_arsize(lsu_axi_arsize[2:0]),
1148 : .axi_arprot(lsu_axi_arprot[2:0]),
1149 :
1150 : .axi_rvalid(lsu_axi_rvalid_ahb),
1151 : .axi_rready(lsu_axi_rready),
1152 : .axi_rid(lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0]),
1153 : .axi_rdata(lsu_axi_rdata_ahb[63:0]),
1154 : .axi_rresp(lsu_axi_rresp_ahb[1:0]),
1155 : .axi_rlast(lsu_axi_rlast_ahb),
1156 :
1157 : // AHB-LITE signals
1158 : .ahb_haddr(lsu_haddr[31:0]),
1159 : .ahb_hburst(lsu_hburst),
1160 : .ahb_hmastlock(lsu_hmastlock),
1161 : .ahb_hprot(lsu_hprot[3:0]),
1162 : .ahb_hsize(lsu_hsize[2:0]),
1163 : .ahb_htrans(lsu_htrans[1:0]),
1164 : .ahb_hwrite(lsu_hwrite),
1165 : .ahb_hwdata(lsu_hwdata[63:0]),
1166 :
1167 : .ahb_hrdata(lsu_hrdata[63:0]),
1168 : .ahb_hready(lsu_hready),
1169 : .ahb_hresp(lsu_hresp),
1170 :
1171 : .*
1172 : );
1173 :
1174 : axi4_to_ahb #(.pt(pt),
1175 : .TAG(pt.IFU_BUS_TAG)) ifu_axi4_to_ahb (
1176 : .clk(free_l2clk),
1177 : .free_clk(free_clk),
1178 : .rst_l(core_rst_l),
1179 : .clk_override(dec_tlu_bus_clk_override),
1180 : .bus_clk_en(ifu_bus_clk_en),
1181 : .dec_tlu_force_halt(dec_tlu_force_halt),
1182 :
1183 : // AHB-Lite signals
1184 : .ahb_haddr(haddr[31:0]),
1185 : .ahb_hburst(hburst),
1186 : .ahb_hmastlock(hmastlock),
1187 : .ahb_hprot(hprot[3:0]),
1188 : .ahb_hsize(hsize[2:0]),
1189 : .ahb_htrans(htrans[1:0]),
1190 : .ahb_hwrite(hwrite),
1191 : .ahb_hwdata(hwdata_nc[63:0]),
1192 :
1193 : .ahb_hrdata(hrdata[63:0]),
1194 : .ahb_hready(hready),
1195 : .ahb_hresp(hresp),
1196 :
1197 : // AXI Write Channels
1198 : .axi_awvalid(ifu_axi_awvalid),
1199 : .axi_awready(ifu_axi_awready_ahb),
1200 : .axi_awid(ifu_axi_awid[pt.IFU_BUS_TAG-1:0]),
1201 : .axi_awaddr(ifu_axi_awaddr[31:0]),
1202 : .axi_awsize(ifu_axi_awsize[2:0]),
1203 : .axi_awprot(ifu_axi_awprot[2:0]),
1204 :
1205 : .axi_wvalid(ifu_axi_wvalid),
1206 : .axi_wready(ifu_axi_wready_ahb),
1207 : .axi_wdata(ifu_axi_wdata[63:0]),
1208 : .axi_wstrb(ifu_axi_wstrb[7:0]),
1209 : .axi_wlast(ifu_axi_wlast),
1210 :
1211 : .axi_bvalid(ifu_axi_bvalid_ahb),
1212 : .axi_bready(1'b1),
1213 : .axi_bresp(ifu_axi_bresp_ahb[1:0]),
1214 : .axi_bid(ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0]),
1215 :
1216 : // AXI Read Channels
1217 : .axi_arvalid(ifu_axi_arvalid),
1218 : .axi_arready(ifu_axi_arready_ahb),
1219 : .axi_arid(ifu_axi_arid[pt.IFU_BUS_TAG-1:0]),
1220 : .axi_araddr(ifu_axi_araddr[31:0]),
1221 : .axi_arsize(ifu_axi_arsize[2:0]),
1222 : .axi_arprot(ifu_axi_arprot[2:0]),
1223 :
1224 : .axi_rvalid(ifu_axi_rvalid_ahb),
1225 : .axi_rready(ifu_axi_rready),
1226 : .axi_rid(ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0]),
1227 : .axi_rdata(ifu_axi_rdata_ahb[63:0]),
1228 : .axi_rresp(ifu_axi_rresp_ahb[1:0]),
1229 : .axi_rlast(ifu_axi_rlast_ahb),
1230 : .*
1231 : );
1232 :
1233 : // AXI4 -> AHB Gasket for System Bus
1234 : axi4_to_ahb #(.pt(pt),
1235 : .TAG(pt.SB_BUS_TAG)) sb_axi4_to_ahb (
1236 : .clk(free_l2clk),
1237 : .free_clk(free_clk),
1238 : .rst_l(dbg_rst_l),
1239 : .clk_override(dec_tlu_bus_clk_override),
1240 : .bus_clk_en(dbg_bus_clk_en),
1241 : .dec_tlu_force_halt(1'b0),
1242 :
1243 : // AXI Write Channels
1244 : .axi_awvalid(sb_axi_awvalid),
1245 : .axi_awready(sb_axi_awready_ahb),
1246 : .axi_awid(sb_axi_awid[pt.SB_BUS_TAG-1:0]),
1247 : .axi_awaddr(sb_axi_awaddr[31:0]),
1248 : .axi_awsize(sb_axi_awsize[2:0]),
1249 : .axi_awprot(sb_axi_awprot[2:0]),
1250 :
1251 : .axi_wvalid(sb_axi_wvalid),
1252 : .axi_wready(sb_axi_wready_ahb),
1253 : .axi_wdata(sb_axi_wdata[63:0]),
1254 : .axi_wstrb(sb_axi_wstrb[7:0]),
1255 : .axi_wlast(sb_axi_wlast),
1256 :
1257 : .axi_bvalid(sb_axi_bvalid_ahb),
1258 : .axi_bready(sb_axi_bready),
1259 : .axi_bresp(sb_axi_bresp_ahb[1:0]),
1260 : .axi_bid(sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0]),
1261 :
1262 : // AXI Read Channels
1263 : .axi_arvalid(sb_axi_arvalid),
1264 : .axi_arready(sb_axi_arready_ahb),
1265 : .axi_arid(sb_axi_arid[pt.SB_BUS_TAG-1:0]),
1266 : .axi_araddr(sb_axi_araddr[31:0]),
1267 : .axi_arsize(sb_axi_arsize[2:0]),
1268 : .axi_arprot(sb_axi_arprot[2:0]),
1269 :
1270 : .axi_rvalid(sb_axi_rvalid_ahb),
1271 : .axi_rready(sb_axi_rready),
1272 : .axi_rid(sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0]),
1273 : .axi_rdata(sb_axi_rdata_ahb[63:0]),
1274 : .axi_rresp(sb_axi_rresp_ahb[1:0]),
1275 : .axi_rlast(sb_axi_rlast_ahb),
1276 : // AHB-LITE signals
1277 : .ahb_haddr(sb_haddr[31:0]),
1278 : .ahb_hburst(sb_hburst),
1279 : .ahb_hmastlock(sb_hmastlock),
1280 : .ahb_hprot(sb_hprot[3:0]),
1281 : .ahb_hsize(sb_hsize[2:0]),
1282 : .ahb_htrans(sb_htrans[1:0]),
1283 : .ahb_hwrite(sb_hwrite),
1284 : .ahb_hwdata(sb_hwdata[63:0]),
1285 :
1286 : .ahb_hrdata(sb_hrdata[63:0]),
1287 : .ahb_hready(sb_hready),
1288 : .ahb_hresp(sb_hresp),
1289 :
1290 : .*
1291 : );
1292 :
1293 : //AHB -> AXI4 Gasket for DMA
1294 : ahb_to_axi4 #(.pt(pt),
1295 : .TAG(pt.DMA_BUS_TAG)) dma_ahb_to_axi4 (
1296 : .clk(free_l2clk),
1297 : .rst_l(core_rst_l),
1298 : .clk_override(dec_tlu_bus_clk_override),
1299 : .bus_clk_en(dma_bus_clk_en),
1300 :
1301 : // AXI Write Channels
1302 : .axi_awvalid(dma_axi_awvalid_ahb),
1303 : .axi_awready(dma_axi_awready),
1304 : .axi_awid(dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0]),
1305 : .axi_awaddr(dma_axi_awaddr_ahb[31:0]),
1306 : .axi_awsize(dma_axi_awsize_ahb[2:0]),
1307 : .axi_awprot(dma_axi_awprot_ahb[2:0]),
1308 : .axi_awlen(dma_axi_awlen_ahb[7:0]),
1309 : .axi_awburst(dma_axi_awburst_ahb[1:0]),
1310 :
1311 : .axi_wvalid(dma_axi_wvalid_ahb),
1312 : .axi_wready(dma_axi_wready),
1313 : .axi_wdata(dma_axi_wdata_ahb[63:0]),
1314 : .axi_wstrb(dma_axi_wstrb_ahb[7:0]),
1315 : .axi_wlast(dma_axi_wlast_ahb),
1316 :
1317 : .axi_bvalid(dma_axi_bvalid),
1318 : .axi_bready(dma_axi_bready_ahb),
1319 : .axi_bresp(dma_axi_bresp[1:0]),
1320 : .axi_bid(dma_axi_bid[pt.DMA_BUS_TAG-1:0]),
1321 :
1322 : // AXI Read Channels
1323 : .axi_arvalid(dma_axi_arvalid_ahb),
1324 : .axi_arready(dma_axi_arready),
1325 : .axi_arid(dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0]),
1326 : .axi_araddr(dma_axi_araddr_ahb[31:0]),
1327 : .axi_arsize(dma_axi_arsize_ahb[2:0]),
1328 : .axi_arprot(dma_axi_arprot_ahb[2:0]),
1329 : .axi_arlen(dma_axi_arlen_ahb[7:0]),
1330 : .axi_arburst(dma_axi_arburst_ahb[1:0]),
1331 :
1332 : .axi_rvalid(dma_axi_rvalid),
1333 : .axi_rready(dma_axi_rready_ahb),
1334 : .axi_rid(dma_axi_rid[pt.DMA_BUS_TAG-1:0]),
1335 : .axi_rdata(dma_axi_rdata[63:0]),
1336 : .axi_rresp(dma_axi_rresp[1:0]),
1337 :
1338 : // AHB signals
1339 : .ahb_haddr(dma_haddr[31:0]),
1340 : .ahb_hburst(dma_hburst),
1341 : .ahb_hmastlock(dma_hmastlock),
1342 : .ahb_hprot(dma_hprot[3:0]),
1343 : .ahb_hsize(dma_hsize[2:0]),
1344 : .ahb_htrans(dma_htrans[1:0]),
1345 : .ahb_hwrite(dma_hwrite),
1346 : .ahb_hwdata(dma_hwdata[63:0]),
1347 :
1348 : .ahb_hrdata(dma_hrdata[63:0]),
1349 : .ahb_hreadyout(dma_hreadyout),
1350 : .ahb_hresp(dma_hresp),
1351 : .ahb_hreadyin(dma_hreadyin),
1352 : .ahb_hsel(dma_hsel),
1353 : .*
1354 : );
1355 :
1356 : end
1357 :
1358 : // Drive the final AXI inputs
1359 : assign lsu_axi_awready_int = pt.BUILD_AHB_LITE ? lsu_axi_awready_ahb : lsu_axi_awready;
1360 : assign lsu_axi_wready_int = pt.BUILD_AHB_LITE ? lsu_axi_wready_ahb : lsu_axi_wready;
1361 : assign lsu_axi_bvalid_int = pt.BUILD_AHB_LITE ? lsu_axi_bvalid_ahb : lsu_axi_bvalid;
1362 : assign lsu_axi_bready_int = pt.BUILD_AHB_LITE ? lsu_axi_bready_ahb : lsu_axi_bready;
1363 : assign lsu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bresp_ahb[1:0] : lsu_axi_bresp[1:0];
1364 : assign lsu_axi_bid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_bid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_bid[pt.LSU_BUS_TAG-1:0];
1365 : assign lsu_axi_arready_int = pt.BUILD_AHB_LITE ? lsu_axi_arready_ahb : lsu_axi_arready;
1366 : assign lsu_axi_rvalid_int = pt.BUILD_AHB_LITE ? lsu_axi_rvalid_ahb : lsu_axi_rvalid;
1367 : assign lsu_axi_rid_int[pt.LSU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? lsu_axi_rid_ahb[pt.LSU_BUS_TAG-1:0] : lsu_axi_rid[pt.LSU_BUS_TAG-1:0];
1368 : assign lsu_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? lsu_axi_rdata_ahb[63:0] : lsu_axi_rdata[63:0];
1369 : assign lsu_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? lsu_axi_rresp_ahb[1:0] : lsu_axi_rresp[1:0];
1370 : assign lsu_axi_rlast_int = pt.BUILD_AHB_LITE ? lsu_axi_rlast_ahb : lsu_axi_rlast;
1371 :
1372 : assign ifu_axi_awready_int = pt.BUILD_AHB_LITE ? ifu_axi_awready_ahb : ifu_axi_awready;
1373 : assign ifu_axi_wready_int = pt.BUILD_AHB_LITE ? ifu_axi_wready_ahb : ifu_axi_wready;
1374 : assign ifu_axi_bvalid_int = pt.BUILD_AHB_LITE ? ifu_axi_bvalid_ahb : ifu_axi_bvalid;
1375 : assign ifu_axi_bready_int = pt.BUILD_AHB_LITE ? ifu_axi_bready_ahb : ifu_axi_bready;
1376 : assign ifu_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bresp_ahb[1:0] : ifu_axi_bresp[1:0];
1377 : assign ifu_axi_bid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_bid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_bid[pt.IFU_BUS_TAG-1:0];
1378 : assign ifu_axi_arready_int = pt.BUILD_AHB_LITE ? ifu_axi_arready_ahb : ifu_axi_arready;
1379 : assign ifu_axi_rvalid_int = pt.BUILD_AHB_LITE ? ifu_axi_rvalid_ahb : ifu_axi_rvalid;
1380 : assign ifu_axi_rid_int[pt.IFU_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? ifu_axi_rid_ahb[pt.IFU_BUS_TAG-1:0] : ifu_axi_rid[pt.IFU_BUS_TAG-1:0];
1381 : assign ifu_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? ifu_axi_rdata_ahb[63:0] : ifu_axi_rdata[63:0];
1382 : assign ifu_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? ifu_axi_rresp_ahb[1:0] : ifu_axi_rresp[1:0];
1383 : assign ifu_axi_rlast_int = pt.BUILD_AHB_LITE ? ifu_axi_rlast_ahb : ifu_axi_rlast;
1384 :
1385 : assign sb_axi_awready_int = pt.BUILD_AHB_LITE ? sb_axi_awready_ahb : sb_axi_awready;
1386 : assign sb_axi_wready_int = pt.BUILD_AHB_LITE ? sb_axi_wready_ahb : sb_axi_wready;
1387 : assign sb_axi_bvalid_int = pt.BUILD_AHB_LITE ? sb_axi_bvalid_ahb : sb_axi_bvalid;
1388 : assign sb_axi_bready_int = pt.BUILD_AHB_LITE ? sb_axi_bready_ahb : sb_axi_bready;
1389 : assign sb_axi_bresp_int[1:0] = pt.BUILD_AHB_LITE ? sb_axi_bresp_ahb[1:0] : sb_axi_bresp[1:0];
1390 : assign sb_axi_bid_int[pt.SB_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? sb_axi_bid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_bid[pt.SB_BUS_TAG-1:0];
1391 : assign sb_axi_arready_int = pt.BUILD_AHB_LITE ? sb_axi_arready_ahb : sb_axi_arready;
1392 : assign sb_axi_rvalid_int = pt.BUILD_AHB_LITE ? sb_axi_rvalid_ahb : sb_axi_rvalid;
1393 : assign sb_axi_rid_int[pt.SB_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? sb_axi_rid_ahb[pt.SB_BUS_TAG-1:0] : sb_axi_rid[pt.SB_BUS_TAG-1:0];
1394 : assign sb_axi_rdata_int[63:0] = pt.BUILD_AHB_LITE ? sb_axi_rdata_ahb[63:0] : sb_axi_rdata[63:0];
1395 : assign sb_axi_rresp_int[1:0] = pt.BUILD_AHB_LITE ? sb_axi_rresp_ahb[1:0] : sb_axi_rresp[1:0];
1396 : assign sb_axi_rlast_int = pt.BUILD_AHB_LITE ? sb_axi_rlast_ahb : sb_axi_rlast;
1397 :
1398 : assign dma_axi_awvalid_int = pt.BUILD_AHB_LITE ? dma_axi_awvalid_ahb : dma_axi_awvalid;
1399 : assign dma_axi_awid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_awid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_awid[pt.DMA_BUS_TAG-1:0];
1400 : assign dma_axi_awaddr_int[31:0] = pt.BUILD_AHB_LITE ? dma_axi_awaddr_ahb[31:0] : dma_axi_awaddr[31:0];
1401 : assign dma_axi_awsize_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_awsize_ahb[2:0] : dma_axi_awsize[2:0];
1402 : assign dma_axi_awprot_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_awprot_ahb[2:0] : dma_axi_awprot[2:0];
1403 : assign dma_axi_awlen_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_awlen_ahb[7:0] : dma_axi_awlen[7:0];
1404 : assign dma_axi_awburst_int[1:0] = pt.BUILD_AHB_LITE ? dma_axi_awburst_ahb[1:0] : dma_axi_awburst[1:0];
1405 : assign dma_axi_wvalid_int = pt.BUILD_AHB_LITE ? dma_axi_wvalid_ahb : dma_axi_wvalid;
1406 : assign dma_axi_wdata_int[63:0] = pt.BUILD_AHB_LITE ? dma_axi_wdata_ahb[63:0] : dma_axi_wdata;
1407 : assign dma_axi_wstrb_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_wstrb_ahb[7:0] : dma_axi_wstrb[7:0];
1408 : assign dma_axi_wlast_int = pt.BUILD_AHB_LITE ? dma_axi_wlast_ahb : dma_axi_wlast;
1409 : assign dma_axi_bready_int = pt.BUILD_AHB_LITE ? dma_axi_bready_ahb : dma_axi_bready;
1410 : assign dma_axi_arvalid_int = pt.BUILD_AHB_LITE ? dma_axi_arvalid_ahb : dma_axi_arvalid;
1411 : assign dma_axi_arid_int[pt.DMA_BUS_TAG-1:0] = pt.BUILD_AHB_LITE ? dma_axi_arid_ahb[pt.DMA_BUS_TAG-1:0] : dma_axi_arid[pt.DMA_BUS_TAG-1:0];
1412 : assign dma_axi_araddr_int[31:0] = pt.BUILD_AHB_LITE ? dma_axi_araddr_ahb[31:0] : dma_axi_araddr[31:0];
1413 : assign dma_axi_arsize_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_arsize_ahb[2:0] : dma_axi_arsize[2:0];
1414 : assign dma_axi_arprot_int[2:0] = pt.BUILD_AHB_LITE ? dma_axi_arprot_ahb[2:0] : dma_axi_arprot[2:0];
1415 : assign dma_axi_arlen_int[7:0] = pt.BUILD_AHB_LITE ? dma_axi_arlen_ahb[7:0] : dma_axi_arlen[7:0];
1416 : assign dma_axi_arburst_int[1:0] = pt.BUILD_AHB_LITE ? dma_axi_arburst_ahb[1:0] : dma_axi_arburst[1:0];
1417 : assign dma_axi_rready_int = pt.BUILD_AHB_LITE ? dma_axi_rready_ahb : dma_axi_rready;
1418 :
1419 :
1420 : if (pt.BUILD_AHB_LITE == 1) begin
1421 : `ifdef RV_ASSERT_ON
1422 : property ahb_trxn_aligned;
1423 : @(posedge clk) disable iff(~rst_l) (lsu_htrans[1:0] != 2'b0) |-> ((lsu_hsize[2:0] == 3'h0) |
1424 : ((lsu_hsize[2:0] == 3'h1) & (lsu_haddr[0] == 1'b0)) |
1425 : ((lsu_hsize[2:0] == 3'h2) & (lsu_haddr[1:0] == 2'b0)) |
1426 : ((lsu_hsize[2:0] == 3'h3) & (lsu_haddr[2:0] == 3'b0)));
1427 : endproperty
1428 : assert_ahb_trxn_aligned: assert property (ahb_trxn_aligned) else
1429 : $display("Assertion ahb_trxn_aligned failed: lsu_htrans=2'h%h, lsu_hsize=3'h%h, lsu_haddr=32'h%h",lsu_htrans[1:0], lsu_hsize[2:0], lsu_haddr[31:0]);
1430 :
1431 : property dma_trxn_aligned;
1432 : @(posedge clk) disable iff(~rst_l) (dma_htrans[1:0] != 2'b0) |-> ((dma_hsize[2:0] == 3'h0) |
1433 : ((dma_hsize[2:0] == 3'h1) & (dma_haddr[0] == 1'b0)) |
1434 : ((dma_hsize[2:0] == 3'h2) & (dma_haddr[1:0] == 2'b0)) |
1435 : ((dma_hsize[2:0] == 3'h3) & (dma_haddr[2:0] == 3'b0)));
1436 : endproperty
1437 :
1438 :
1439 : `endif
1440 : end // if (pt.BUILD_AHB_LITE == 1)
1441 :
1442 :
1443 : // unpack packet
1444 : // also need retires_p==3
1445 :
1446 : assign trace_rv_i_insn_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_insn_ip[31:0];
1447 :
1448 : assign trace_rv_i_address_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_address_ip[31:0];
1449 :
1450 : assign trace_rv_i_valid_ip = trace_rv_trace_pkt.trace_rv_i_valid_ip;
1451 :
1452 : assign trace_rv_i_exception_ip = trace_rv_trace_pkt.trace_rv_i_exception_ip;
1453 :
1454 : assign trace_rv_i_ecause_ip[4:0] = trace_rv_trace_pkt.trace_rv_i_ecause_ip[4:0];
1455 :
1456 : assign trace_rv_i_interrupt_ip = trace_rv_trace_pkt.trace_rv_i_interrupt_ip;
1457 :
1458 : assign trace_rv_i_tval_ip[31:0] = trace_rv_trace_pkt.trace_rv_i_tval_ip[31:0];
1459 :
1460 :
1461 :
1462 : endmodule // el2_veer
1463 :
|
