Line data    Source code

       1              : //********************************************************************************
       2              : // SPDX-License-Identifier: Apache-2.0
       3              : // Copyright 2020 Western Digital Corporation or its affiliates.
       4              : // Copyright 2022 Microsoft Corporation
       5              : // Copyright (c) 2023 Antmicro <www.antmicro.com>
       6              : //
       7              : // Licensed under the Apache License, Version 2.0 (the "License");
       8              : // you may not use this file except in compliance with the License.
       9              : // You may obtain a copy of the License at
      10              : //
      11              : // http://www.apache.org/licenses/LICENSE-2.0
      12              : //
      13              : // Unless required by applicable law or agreed to in writing, software
      14              : // distributed under the License is distributed on an "AS IS" BASIS,
      15              : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      16              : // See the License for the specific language governing permissions and
      17              : // limitations under the License.
      18              : //********************************************************************************
      19              : 
      20              : 
      21              : import el2_pkg::*;
      22              : interface el2_mem_if #(
      23              :     `include "el2_param.vh"
      24              : ) ();
      25              :   localparam DCCM_ECC_WIDTH = pt.DCCM_FDATA_WIDTH - pt.DCCM_DATA_WIDTH;
      26              : 
      27              :   //////////////////////////////////////////
      28              :   // Clock
      29    145092138 :   logic                                                               clk;
      30              : 
      31              : 
      32              :   //////////////////////////////////////////
      33              :   // ICCM
      34       786552 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_clken;
      35           48 :   logic [pt.ICCM_NUM_BANKS-1:0]                                       iccm_wren_bank;
      36       479510 :   logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
      37              : 
      38          260 :   logic [pt.ICCM_NUM_BANKS-1:0][                                31:0] iccm_bank_wr_data;
      39           12 :   logic [pt.ICCM_NUM_BANKS-1:0][               pt.ICCM_ECC_WIDTH-1:0] iccm_bank_wr_ecc;
      40        66189 :   logic [pt.ICCM_NUM_BANKS-1:0][                                31:0] iccm_bank_dout;
      41       159453 :   logic [pt.ICCM_NUM_BANKS-1:0][               pt.ICCM_ECC_WIDTH-1:0] iccm_bank_ecc;
      42              : 
      43              : 
      44              :   //////////////////////////////////////////
      45              :   // DCCM
      46       569098 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_clken;
      47       178988 :   logic [pt.DCCM_NUM_BANKS-1:0]                                       dccm_wren_bank;
      48      2067548 :   logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
      49        22958 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank;
      50       152547 :   logic [pt.DCCM_NUM_BANKS-1:0][                  DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank;
      51         5381 :   logic [pt.DCCM_NUM_BANKS-1:0][              pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout;
      52        18762 :   logic [pt.DCCM_NUM_BANKS-1:0][                  DCCM_ECC_WIDTH-1:0] dccm_bank_ecc;
      53              : 
      54              : 
      55              :   //////////////////////////////////////////
      56              :   // MODPORTS
      57              :   modport veer_iccm(
      58              :       input clk,
      59              :       // ICCM
      60              :       output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc,
      61              :       input iccm_bank_dout, iccm_bank_ecc
      62              :   );
      63              : 
      64              :   modport veer_dccm(
      65              :       input clk,
      66              :       // DCCM
      67              :       output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank,
      68              :       input dccm_bank_dout, dccm_bank_ecc
      69              :   );
      70              : 
      71              :   modport veer_sram_src(
      72              :       output clk,
      73              :       // ICCM
      74              :       output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc,
      75              :       input iccm_bank_dout, iccm_bank_ecc,
      76              :       // DCCM
      77              :       output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank,
      78              :       input dccm_bank_dout, dccm_bank_ecc
      79              :   );
      80              : 
      81              :   modport veer_sram_sink(
      82              :       input clk,
      83              :       // ICCM
      84              :       input iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc,
      85              :       output iccm_bank_dout, iccm_bank_ecc,
      86              :       // DCCM
      87              :       input dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank,
      88              :       output dccm_bank_dout, dccm_bank_ecc
      89              :   );
      90              : 
      91              : endinterface