Line data Source code
1 : //********************************************************************************
2 : // SPDX-License-Identifier: Apache-2.0
3 : // Copyright 2020 Western Digital Corporation or its affiliates.
4 : // Copyright 2022 Microsoft Corporation
5 : // Copyright (c) 2023 Antmicro <www.antmicro.com>
6 : //
7 : // Licensed under the Apache License, Version 2.0 (the "License");
8 : // you may not use this file except in compliance with the License.
9 : // You may obtain a copy of the License at
10 : //
11 : // http://www.apache.org/licenses/LICENSE-2.0
12 : //
13 : // Unless required by applicable law or agreed to in writing, software
14 : // distributed under the License is distributed on an "AS IS" BASIS,
15 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 : // See the License for the specific language governing permissions and
17 : // limitations under the License.
18 : //********************************************************************************
19 :
20 :
21 : import el2_pkg::*;
22 : interface el2_mem_if #(
23 : `include "el2_param.vh"
24 : ) ();
25 : //////////////////////////////////////////
26 : // Clock
27 253634628 : logic clk;
28 :
29 :
30 : //////////////////////////////////////////
31 : // ICCM
32 925070 : logic [pt.ICCM_NUM_BANKS-1:0] iccm_clken;
33 1138 : logic [pt.ICCM_NUM_BANKS-1:0] iccm_wren_bank;
34 11407036 : logic [pt.ICCM_NUM_BANKS-1:0][pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] iccm_addr_bank;
35 :
36 473 : logic [pt.ICCM_NUM_BANKS-1:0][ 31:0] iccm_bank_wr_data;
37 436 : logic [pt.ICCM_NUM_BANKS-1:0][ pt.ICCM_ECC_WIDTH-1:0] iccm_bank_wr_ecc;
38 212293 : logic [pt.ICCM_NUM_BANKS-1:0][ 31:0] iccm_bank_dout;
39 222055 : logic [pt.ICCM_NUM_BANKS-1:0][ pt.ICCM_ECC_WIDTH-1:0] iccm_bank_ecc;
40 :
41 :
42 : //////////////////////////////////////////
43 : // DCCM
44 995120 : logic [pt.DCCM_NUM_BANKS-1:0] dccm_clken;
45 351166 : logic [pt.DCCM_NUM_BANKS-1:0] dccm_wren_bank;
46 6198895 : logic [pt.DCCM_NUM_BANKS-1:0][pt.DCCM_BITS-1:(pt.DCCM_BANK_BITS+2)] dccm_addr_bank;
47 473625 : logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_DATA_WIDTH-1:0] dccm_wr_data_bank;
48 524550 : logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_ECC_WIDTH-1:0] dccm_wr_ecc_bank;
49 262013 : logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_DATA_WIDTH-1:0] dccm_bank_dout;
50 268008 : logic [pt.DCCM_NUM_BANKS-1:0][ pt.DCCM_ECC_WIDTH-1:0] dccm_bank_ecc;
51 :
52 : //////////////////////////////////////////
53 : // ICACHE DATA
54 4727296 : logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] ic_b_sb_wren;
55 : logic [pt.ICACHE_BANKS_WAY-1:0][(71*pt.ICACHE_NUM_WAYS)-1:0] ic_b_sb_bit_en_vec;
56 : logic [pt.ICACHE_BANKS_WAY-1:0][(71*pt.ICACHE_NUM_WAYS)-1:0] wb_packeddout_pre;
57 14295792 : logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_sb_wr_data;
58 19125756 : logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_INDEX_HI : pt.ICACHE_DATA_INDEX_LO] ic_rw_addr_bank_q;
59 9968616 : logic [pt.ICACHE_BANKS_WAY-1:0] ic_bank_way_clken_final;
60 0 : logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_bank_way_clken_final_up;
61 : logic [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0][71-1:0] wb_dout_pre_up;
62 :
63 : //////////////////////////////////////////
64 : // ICACHE TAG
65 9464816 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_clken_final;
66 1181896 : logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_wren_q;
67 1181896 : logic [(26*pt.ICACHE_NUM_WAYS)-1 :0] ic_tag_wren_biten_vec;
68 0 : logic [(26*pt.ICACHE_NUM_WAYS)-1 :0] ic_tag_data_raw_packed_pre;
69 190556 : logic [25:0] ic_tag_wr_data;
70 8176152 : logic [pt.ICACHE_INDEX_HI: pt.ICACHE_TAG_INDEX_LO] ic_rw_addr_q;
71 0 : logic [pt.ICACHE_NUM_WAYS-1:0] [25:0] ic_tag_data_raw_pre;
72 :
73 : //////////////////////////////////////////
74 : // MODPORTS
75 : modport veer_iccm(
76 : input clk,
77 : // ICCM
78 : output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc,
79 : input iccm_bank_dout, iccm_bank_ecc
80 : );
81 :
82 : modport veer_dccm(
83 : input clk,
84 : // DCCM
85 : output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank,
86 : input dccm_bank_dout, dccm_bank_ecc
87 : );
88 :
89 : modport veer_sram_src(
90 : output clk,
91 : // ICCM
92 : output iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc,
93 : input iccm_bank_dout, iccm_bank_ecc,
94 : // DCCM
95 : output dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank,
96 : input dccm_bank_dout, dccm_bank_ecc
97 : );
98 :
99 : modport veer_sram_sink(
100 : input clk,
101 : // ICCM
102 : input iccm_clken, iccm_wren_bank, iccm_addr_bank, iccm_bank_wr_data, iccm_bank_wr_ecc,
103 : output iccm_bank_dout, iccm_bank_ecc,
104 : // DCCM
105 : input dccm_clken, dccm_wren_bank, dccm_addr_bank, dccm_wr_data_bank, dccm_wr_ecc_bank,
106 : output dccm_bank_dout, dccm_bank_ecc
107 : );
108 :
109 : modport veer_icache_data(
110 : // data
111 : output ic_b_sb_wren, ic_b_sb_bit_en_vec, ic_sb_wr_data, ic_rw_addr_bank_q, ic_bank_way_clken_final, ic_bank_way_clken_final_up,
112 : input wb_packeddout_pre, wb_dout_pre_up
113 : );
114 :
115 : modport veer_icache_tag(
116 : // tag
117 : output ic_tag_clken_final, ic_tag_wren_q, ic_tag_wren_biten_vec, ic_tag_wr_data, ic_rw_addr_q,
118 : input ic_tag_data_raw_packed_pre,ic_tag_data_raw_pre
119 : );
120 :
121 : modport veer_icache_src(
122 : output clk,
123 : // data
124 : output ic_b_sb_wren, ic_b_sb_bit_en_vec, ic_sb_wr_data, ic_rw_addr_bank_q, ic_bank_way_clken_final, ic_bank_way_clken_final_up,
125 : input wb_packeddout_pre, wb_dout_pre_up,
126 : // tag
127 : output ic_tag_clken_final, ic_tag_wren_q, ic_tag_wren_biten_vec, ic_tag_wr_data, ic_rw_addr_q,
128 : input ic_tag_data_raw_packed_pre,ic_tag_data_raw_pre
129 : );
130 :
131 : endinterface
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