Project Full coverage report
Current view: Cores-VeeR-EL2—Cores-VeeR-EL2—design—el2_mem.sv Coverage Hit Total
Test Date: 08-11-2024 Toggle 70.8% 34 48
Test: all Branch 0.0% 0 0

            Line data    Source code
       1              : //********************************************************************************
       2              : // SPDX-License-Identifier: Apache-2.0
       3              : // Copyright 2020 Western Digital Corporation or its affiliates.
       4              : // Copyright (c) 2023 Antmicro <www.antmicro.com>
       5              : //
       6              : // Licensed under the Apache License, Version 2.0 (the "License");
       7              : // you may not use this file except in compliance with the License.
       8              : // You may obtain a copy of the License at
       9              : //
      10              : // http://www.apache.org/licenses/LICENSE-2.0
      11              : //
      12              : // Unless required by applicable law or agreed to in writing, software
      13              : // distributed under the License is distributed on an "AS IS" BASIS,
      14              : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      15              : // See the License for the specific language governing permissions and
      16              : // limitations under the License.
      17              : //********************************************************************************
      18              : 
      19              : module el2_mem
      20              : import el2_pkg::*;
      21              : #(
      22              : `include "el2_param.vh"
      23              :  )
      24              : (
      25     69890155 :    input logic         clk,
      26          338 :    input logic         rst_l,
      27            2 :    input logic         dccm_clk_override,
      28            2 :    input logic         icm_clk_override,
      29            8 :    input logic         dec_tlu_core_ecc_disable,
      30              : 
      31              :    //DCCM ports
      32       262894 :    input logic         dccm_wren,
      33       561000 :    input logic         dccm_rden,
      34        18811 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_lo,
      35        18811 :    input logic [pt.DCCM_BITS-1:0]  dccm_wr_addr_hi,
      36       471334 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_lo,
      37       677729 :    input logic [pt.DCCM_BITS-1:0]  dccm_rd_addr_hi,
      38         5376 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_lo,
      39         5376 :    input logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_wr_data_hi,
      40              : 
      41              : 
      42        47176 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_lo,
      43        47176 :    output logic [pt.DCCM_FDATA_WIDTH-1:0]  dccm_rd_data_hi,
      44              : 
      45              :    //ICCM ports
      46       160275 :    input logic [pt.ICCM_BITS-1:1]  iccm_rw_addr,
      47            8 :    input logic                                        iccm_buf_correct_ecc,                    // ICCM is doing a single bit error correct cycle
      48            8 :    input logic                                        iccm_correction_state,               // ICCM is doing a single bit error correct cycle
      49           74 :    input logic         iccm_wren,
      50       133206 :    input logic         iccm_rden,
      51            0 :    input logic [2:0]   iccm_wr_size,
      52           14 :    input logic [77:0]  iccm_wr_data,
      53              : 
      54       136532 :    output logic [63:0] iccm_rd_data,
      55       161264 :    output logic [77:0] iccm_rd_data_ecc,
      56              : 
      57              :    // Icache and Itag Ports
      58              : 
      59          490 :    input  logic [31:1]  ic_rw_addr,
      60       255918 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_tag_valid,
      61        10432 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]   ic_wr_en,
      62       680962 :    input  logic         ic_rd_en,
      63      1738700 :    input  logic [63:0] ic_premux_data,      // Premux data to be muxed with each way of the Icache.
      64      5605966 :    input  logic         ic_sel_premux_data, // Premux data sel
      65            0 :    input el2_ic_data_ext_in_pkt_t   [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0]         ic_data_ext_in_pkt,
      66            0 :    input el2_ic_tag_ext_in_pkt_t    [pt.ICACHE_NUM_WAYS-1:0]           ic_tag_ext_in_pkt,
      67              : 
      68       560643 :    input  logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
      69            0 :    input  logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
      70       231589 :    output logic [70:0]               ic_debug_rd_data ,  // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      71            0 :    input  logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
      72            0 :    input  logic                      ic_debug_rd_en,     // Icache debug rd
      73            0 :    input  logic                      ic_debug_wr_en,     // Icache debug wr
      74            0 :    input  logic                      ic_debug_tag_array, // Debug tag array
      75            0 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]                ic_debug_way,       // Debug way. Rd or Wr.
      76              : 
      77      2137120 :    output logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
      78            0 :    output logic [25:0]               ictag_debug_rd_data,// Debug icache tag.
      79              : 
      80              : 
      81            0 :    output logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,    // ecc error per bank
      82            0 :    output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,          // parity error per bank
      83       109586 :    output logic [pt.ICACHE_NUM_WAYS-1:0]   ic_rd_hit,
      84            0 :    output logic         ic_tag_perr,        // Icache Tag parity error
      85              : 
      86              :    el2_mem_if.veer_sram_src mem_export,
      87              : 
      88            0 :    input  logic         scan_mode
      89              : 
      90              : );
      91              : 
      92     69890155 :    logic active_clk;
      93              :    rvoclkhdr active_cg   ( .en(1'b1),         .l1clk(active_clk), .* );
      94              : 
      95              :    el2_mem_if mem_export_local ();
      96              : 
      97              :    assign mem_export      .clk = clk;
      98              :    assign mem_export_local.clk = clk;
      99              : 
     100              :    assign mem_export      .iccm_clken         = mem_export_local.iccm_clken;
     101              :    assign mem_export      .iccm_wren_bank     = mem_export_local.iccm_wren_bank;
     102              :    assign mem_export      .iccm_addr_bank     = mem_export_local.iccm_addr_bank;
     103              :    assign mem_export      .iccm_bank_wr_data  = mem_export_local.iccm_bank_wr_data;
     104              :    assign mem_export      .iccm_bank_wr_ecc   = mem_export_local.iccm_bank_wr_ecc;
     105              :    assign mem_export_local.iccm_bank_dout     = mem_export.      iccm_bank_dout;
     106              :    assign mem_export_local.iccm_bank_ecc      = mem_export.      iccm_bank_ecc;
     107              : 
     108              :    assign mem_export      .dccm_clken         = mem_export_local.dccm_clken;
     109              :    assign mem_export      .dccm_wren_bank     = mem_export_local.dccm_wren_bank;
     110              :    assign mem_export      .dccm_addr_bank     = mem_export_local.dccm_addr_bank;
     111              :    assign mem_export      .dccm_wr_data_bank  = mem_export_local.dccm_wr_data_bank;
     112              :    assign mem_export      .dccm_wr_ecc_bank   = mem_export_local.dccm_wr_ecc_bank;
     113              :    assign mem_export_local.dccm_bank_dout     = mem_export      .dccm_bank_dout;
     114              :    assign mem_export_local.dccm_bank_ecc      = mem_export      .dccm_bank_ecc;
     115              : 
     116              :    // DCCM Instantiation
     117              :    if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
     118              :       el2_lsu_dccm_mem #(.pt(pt)) dccm (
     119              :          .clk_override(dccm_clk_override),
     120              :          .dccm_mem_export(mem_export_local.veer_dccm),
     121              :          .*
     122              :       );
     123              :    end else begin: Gen_dccm_disable
     124              :       assign dccm_rd_data_lo = '0;
     125              :       assign dccm_rd_data_hi = '0;
     126              :    end
     127              : 
     128              : if ( pt.ICACHE_ENABLE ) begin: icache
     129              :    el2_ifu_ic_mem #(.pt(pt)) icm  (
     130              :       .clk_override(icm_clk_override),
     131              :       .*
     132              :    );
     133              : end
     134              : else  begin
     135              :    assign   ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] = '0;
     136              :    assign   ic_tag_perr    = '0 ;
     137              :    assign   ic_rd_data  = '0 ;
     138              :    assign   ictag_debug_rd_data  = '0 ;
     139              :    assign   ic_debug_rd_data  = '0 ;
     140              :    assign   ic_eccerr      = '0;
     141              : end // else: !if( pt.ICACHE_ENABLE )
     142              : 
     143              : 
     144              : 
     145              : if (pt.ICCM_ENABLE) begin : iccm
     146              :    el2_ifu_iccm_mem  #(.pt(pt)) iccm (.*,
     147              :                   .clk_override(icm_clk_override),
     148              :                   .iccm_rw_addr(iccm_rw_addr[pt.ICCM_BITS-1:1]),
     149              :                   .iccm_rd_data(iccm_rd_data[63:0]),
     150              :                   .iccm_mem_export(mem_export_local.veer_iccm)
     151              :                    );
     152              : end
     153              : else  begin
     154              :    assign  iccm_rd_data    = '0 ;
     155              :    assign iccm_rd_data_ecc = '0 ;
     156              : end
     157              : 
     158              : 
     159              : endmodule