Line data Source code
1 : //********************************************************************************
2 : // SPDX-License-Identifier: Apache-2.0
3 : // Copyright 2020 Western Digital Corporation or its affiliates.
4 : // Copyright (c) 2023 Antmicro <www.antmicro.com>
5 : //
6 : // Licensed under the Apache License, Version 2.0 (the "License");
7 : // you may not use this file except in compliance with the License.
8 : // You may obtain a copy of the License at
9 : //
10 : // http://www.apache.org/licenses/LICENSE-2.0
11 : //
12 : // Unless required by applicable law or agreed to in writing, software
13 : // distributed under the License is distributed on an "AS IS" BASIS,
14 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 : // See the License for the specific language governing permissions and
16 : // limitations under the License.
17 : //********************************************************************************
18 :
19 : module el2_mem
20 : import el2_pkg::*;
21 : #(
22 : `include "el2_param.vh"
23 : )
24 : (
25 69840565 : input logic clk,
26 338 : input logic rst_l,
27 2 : input logic dccm_clk_override,
28 2 : input logic icm_clk_override,
29 8 : input logic dec_tlu_core_ecc_disable,
30 :
31 : //DCCM ports
32 262894 : input logic dccm_wren,
33 561000 : input logic dccm_rden,
34 18811 : input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo,
35 18811 : input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi,
36 470956 : input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo,
37 677351 : input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi,
38 5376 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
39 5376 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
40 :
41 :
42 47176 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
43 47176 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
44 :
45 : //ICCM ports
46 160236 : input logic [pt.ICCM_BITS-1:1] iccm_rw_addr,
47 8 : input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
48 8 : input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
49 74 : input logic iccm_wren,
50 133206 : input logic iccm_rden,
51 0 : input logic [2:0] iccm_wr_size,
52 14 : input logic [77:0] iccm_wr_data,
53 :
54 136532 : output logic [63:0] iccm_rd_data,
55 161264 : output logic [77:0] iccm_rd_data_ecc,
56 :
57 : // Icache and Itag Ports
58 :
59 489 : input logic [31:1] ic_rw_addr,
60 255918 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid,
61 10432 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en,
62 680948 : input logic ic_rd_en,
63 1737398 : input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
64 5599841 : input logic ic_sel_premux_data, // Premux data sel
65 0 : input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
66 0 : input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
67 :
68 560245 : input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
69 0 : input logic [70:0] ic_debug_wr_data, // Debug wr cache.
70 231591 : output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
71 0 : input logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
72 20 : input logic ic_debug_rd_en, // Icache debug rd
73 20 : input logic ic_debug_wr_en, // Icache debug wr
74 8 : input logic ic_debug_tag_array, // Debug tag array
75 0 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
76 :
77 2135818 : output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
78 0 : output logic [25:0] ictag_debug_rd_data,// Debug icache tag.
79 :
80 :
81 0 : output logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
82 0 : output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
83 109586 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,
84 0 : output logic ic_tag_perr, // Icache Tag parity error
85 :
86 : el2_mem_if.veer_sram_src mem_export,
87 :
88 : // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
89 : /*verilator coverage_off*/
90 : input logic scan_mode
91 : /*verilator coverage_on*/
92 :
93 : );
94 :
95 69840565 : logic active_clk;
96 : rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
97 :
98 : el2_mem_if mem_export_local ();
99 :
100 : assign mem_export .clk = clk;
101 : assign mem_export_local.clk = clk;
102 :
103 : assign mem_export .iccm_clken = mem_export_local.iccm_clken;
104 : assign mem_export .iccm_wren_bank = mem_export_local.iccm_wren_bank;
105 : assign mem_export .iccm_addr_bank = mem_export_local.iccm_addr_bank;
106 : assign mem_export .iccm_bank_wr_data = mem_export_local.iccm_bank_wr_data;
107 : assign mem_export .iccm_bank_wr_ecc = mem_export_local.iccm_bank_wr_ecc;
108 : assign mem_export_local.iccm_bank_dout = mem_export. iccm_bank_dout;
109 : assign mem_export_local.iccm_bank_ecc = mem_export. iccm_bank_ecc;
110 :
111 : assign mem_export .dccm_clken = mem_export_local.dccm_clken;
112 : assign mem_export .dccm_wren_bank = mem_export_local.dccm_wren_bank;
113 : assign mem_export .dccm_addr_bank = mem_export_local.dccm_addr_bank;
114 : assign mem_export .dccm_wr_data_bank = mem_export_local.dccm_wr_data_bank;
115 : assign mem_export .dccm_wr_ecc_bank = mem_export_local.dccm_wr_ecc_bank;
116 : assign mem_export_local.dccm_bank_dout = mem_export .dccm_bank_dout;
117 : assign mem_export_local.dccm_bank_ecc = mem_export .dccm_bank_ecc;
118 :
119 : // DCCM Instantiation
120 : if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
121 : el2_lsu_dccm_mem #(.pt(pt)) dccm (
122 : .clk_override(dccm_clk_override),
123 : .dccm_mem_export(mem_export_local.veer_dccm),
124 : .*
125 : );
126 : end else begin: Gen_dccm_disable
127 : assign dccm_rd_data_lo = '0;
128 : assign dccm_rd_data_hi = '0;
129 : end
130 :
131 : if ( pt.ICACHE_ENABLE ) begin: icache
132 : el2_ifu_ic_mem #(.pt(pt)) icm (
133 : .clk_override(icm_clk_override),
134 : .*
135 : );
136 : end
137 : else begin
138 : assign ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] = '0;
139 : assign ic_tag_perr = '0 ;
140 : assign ic_rd_data = '0 ;
141 : assign ictag_debug_rd_data = '0 ;
142 : assign ic_debug_rd_data = '0 ;
143 : assign ic_eccerr = '0;
144 : end // else: !if( pt.ICACHE_ENABLE )
145 :
146 :
147 :
148 : if (pt.ICCM_ENABLE) begin : iccm
149 : el2_ifu_iccm_mem #(.pt(pt)) iccm (.*,
150 : .clk_override(icm_clk_override),
151 : .iccm_rw_addr(iccm_rw_addr[pt.ICCM_BITS-1:1]),
152 : .iccm_rd_data(iccm_rd_data[63:0]),
153 : .iccm_mem_export(mem_export_local.veer_iccm)
154 : );
155 : end
156 : else begin
157 : assign iccm_rd_data = '0 ;
158 : assign iccm_rd_data_ecc = '0 ;
159 : end
160 :
161 :
162 : endmodule
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