Line data Source code
1 : //********************************************************************************
2 : // SPDX-License-Identifier: Apache-2.0
3 : // Copyright 2020 Western Digital Corporation or its affiliates.
4 : // Copyright (c) 2023 Antmicro <www.antmicro.com>
5 : //
6 : // Licensed under the Apache License, Version 2.0 (the "License");
7 : // you may not use this file except in compliance with the License.
8 : // You may obtain a copy of the License at
9 : //
10 : // http://www.apache.org/licenses/LICENSE-2.0
11 : //
12 : // Unless required by applicable law or agreed to in writing, software
13 : // distributed under the License is distributed on an "AS IS" BASIS,
14 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 : // See the License for the specific language governing permissions and
16 : // limitations under the License.
17 : //********************************************************************************
18 :
19 : module el2_mem
20 : import el2_pkg::*;
21 : #(
22 : `include "el2_param.vh"
23 : )
24 : (
25 115884880 : input logic clk,
26 299 : input logic rst_l,
27 2 : input logic dccm_clk_override,
28 2 : input logic icm_clk_override,
29 8 : input logic dec_tlu_core_ecc_disable,
30 :
31 : //DCCM ports
32 273904 : input logic dccm_wren,
33 620164 : input logic dccm_rden,
34 173860 : input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo,
35 173860 : input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi,
36 2097926 : input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo,
37 2365941 : input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi,
38 174952 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
39 174952 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
40 :
41 :
42 429168 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
43 429168 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
44 :
45 : //ICCM ports
46 8827177 : input logic [pt.ICCM_BITS-1:1] iccm_rw_addr,
47 16 : input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
48 16 : input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
49 124 : input logic iccm_wren,
50 133336 : input logic iccm_rden,
51 108 : input logic [2:0] iccm_wr_size,
52 66 : input logic [77:0] iccm_wr_data,
53 :
54 311643 : output logic [63:0] iccm_rd_data,
55 319384 : output logic [77:0] iccm_rd_data_ecc,
56 :
57 : // Icache and Itag Ports
58 :
59 9485644 : input logic [31:1] ic_rw_addr,
60 1835828 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid,
61 1181806 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en,
62 1801295 : input logic ic_rd_en,
63 8541488 : input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
64 9154391 : input logic ic_sel_premux_data, // Premux data sel
65 :
66 3573862 : input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
67 10 : input logic [70:0] ic_debug_wr_data, // Debug wr cache.
68 29199 : output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
69 50 : input logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
70 20 : input logic ic_debug_rd_en, // Icache debug rd
71 100 : input logic ic_debug_wr_en, // Icache debug wr
72 8 : input logic ic_debug_tag_array, // Debug tag array
73 300 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
74 :
75 10156594 : output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
76 0 : output logic [25:0] ictag_debug_rd_data,// Debug icache tag.
77 :
78 :
79 6 : output logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
80 0 : output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
81 16001 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit,
82 0 : output logic ic_tag_perr, // Icache Tag parity error
83 :
84 : el2_mem_if.veer_sram_src mem_export,
85 : el2_mem_if.veer_icache_src icache_export,
86 :
87 : // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
88 : /*pragma coverage off*/
89 : input logic scan_mode
90 : /*pragma coverage on*/
91 :
92 : );
93 :
94 115884880 : logic active_clk;
95 : rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
96 :
97 : el2_mem_if mem_export_local ();
98 :
99 : assign mem_export_local.clk = clk;
100 :
101 : assign mem_export .clk = mem_export_local.clk;
102 :
103 : assign mem_export .iccm_clken = mem_export_local.iccm_clken;
104 : assign mem_export .iccm_wren_bank = mem_export_local.iccm_wren_bank;
105 : assign mem_export .iccm_addr_bank = mem_export_local.iccm_addr_bank;
106 : assign mem_export .iccm_bank_wr_data = mem_export_local.iccm_bank_wr_data;
107 : assign mem_export .iccm_bank_wr_ecc = mem_export_local.iccm_bank_wr_ecc;
108 : assign mem_export_local.iccm_bank_dout = mem_export. iccm_bank_dout;
109 : assign mem_export_local.iccm_bank_ecc = mem_export. iccm_bank_ecc;
110 :
111 : assign mem_export .dccm_clken = mem_export_local.dccm_clken;
112 : assign mem_export .dccm_wren_bank = mem_export_local.dccm_wren_bank;
113 : assign mem_export .dccm_addr_bank = mem_export_local.dccm_addr_bank;
114 : assign mem_export .dccm_wr_data_bank = mem_export_local.dccm_wr_data_bank;
115 : assign mem_export .dccm_wr_ecc_bank = mem_export_local.dccm_wr_ecc_bank;
116 : assign mem_export_local.dccm_bank_dout = mem_export .dccm_bank_dout;
117 : assign mem_export_local.dccm_bank_ecc = mem_export .dccm_bank_ecc;
118 :
119 : // icache data
120 : assign icache_export .ic_b_sb_wren = mem_export_local.ic_b_sb_wren;
121 : assign icache_export .ic_b_sb_bit_en_vec = mem_export_local.ic_b_sb_bit_en_vec;
122 : assign icache_export .ic_sb_wr_data = mem_export_local.ic_sb_wr_data;
123 : assign icache_export .ic_rw_addr_bank_q = mem_export_local.ic_rw_addr_bank_q;
124 : assign icache_export .ic_bank_way_clken_final = mem_export_local.ic_bank_way_clken_final;
125 : assign icache_export .ic_bank_way_clken_final_up = mem_export_local.ic_bank_way_clken_final_up;
126 : assign mem_export_local.wb_packeddout_pre = icache_export .wb_packeddout_pre;
127 : assign mem_export_local.wb_dout_pre_up = icache_export .wb_dout_pre_up;
128 :
129 : // icache tag
130 : assign icache_export .ic_tag_clken_final = mem_export_local.ic_tag_clken_final;
131 : assign icache_export .ic_tag_wren_q = mem_export_local.ic_tag_wren_q;
132 : assign icache_export .ic_tag_wren_biten_vec = mem_export_local.ic_tag_wren_biten_vec;
133 : assign icache_export .ic_tag_wr_data = mem_export_local.ic_tag_wr_data;
134 : assign icache_export .ic_rw_addr_q = mem_export_local.ic_rw_addr_q;
135 : assign mem_export_local.ic_tag_data_raw_packed_pre = icache_export .ic_tag_data_raw_packed_pre;
136 : assign mem_export_local.ic_tag_data_raw_pre = icache_export .ic_tag_data_raw_pre;
137 :
138 : // DCCM Instantiation
139 : if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
140 : el2_lsu_dccm_mem #(.pt(pt)) dccm (
141 : .clk_override(dccm_clk_override),
142 : .dccm_mem_export(mem_export_local.veer_dccm),
143 : .*
144 : );
145 : end else begin: Gen_dccm_disable
146 : assign dccm_rd_data_lo = '0;
147 : assign dccm_rd_data_hi = '0;
148 : end
149 :
150 : if ( pt.ICACHE_ENABLE ) begin: icache
151 : el2_ifu_ic_mem #(.pt(pt)) icm (
152 : .clk_override(icm_clk_override),
153 : .icache_export(mem_export_local.veer_icache_src),
154 : .*
155 : );
156 : end
157 : else begin
158 : assign ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] = '0;
159 : assign ic_tag_perr = '0 ;
160 : assign ic_rd_data = '0 ;
161 : assign ictag_debug_rd_data = '0 ;
162 : assign ic_debug_rd_data = '0 ;
163 : assign ic_eccerr = '0;
164 : end // else: !if( pt.ICACHE_ENABLE )
165 :
166 :
167 :
168 : if (pt.ICCM_ENABLE) begin : iccm
169 : el2_ifu_iccm_mem #(.pt(pt)) iccm (.*,
170 : .clk_override(icm_clk_override),
171 : .iccm_rw_addr(iccm_rw_addr[pt.ICCM_BITS-1:1]),
172 : .iccm_rd_data(iccm_rd_data[63:0]),
173 : .iccm_mem_export(mem_export_local.veer_iccm)
174 : );
175 : end
176 : else begin
177 : assign iccm_rd_data = '0 ;
178 : assign iccm_rd_data_ecc = '0 ;
179 : end
180 :
181 :
182 : endmodule
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