Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 : //********************************************************************************
17 : // $Id$
18 : //
19 : //
20 : // Owner:
21 : // Function: Top level file for load store unit
22 : // Comments:
23 : //
24 : //
25 : // DC1 -> DC2 -> DC3 -> DC4 (Commit)
26 : //
27 : //********************************************************************************
28 : module el2_lsu_ecc
29 : import el2_pkg::*;
30 : #(
31 : `include "el2_param.vh"
32 : )
33 : (
34 61843746 : input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
35 61843746 : input logic lsu_c2_r_clk, // clock
36 0 : input logic clk_override, // Override non-functional clock gating
37 316 : input logic rst_l, // reset, active low
38 0 : input logic scan_mode, // scan mode
39 :
40 478184 : input el2_lsu_pkt_t lsu_pkt_m, // packet in m
41 478181 : input el2_lsu_pkt_t lsu_pkt_r, // packet in r
42 7574 : input logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any,
43 :
44 8 : input logic dec_tlu_core_ecc_disable, // disables the ecc computation and error flagging
45 :
46 561000 : input logic lsu_dccm_rden_r, // dccm rden
47 614420 : input logic addr_in_dccm_r, // address in dccm
48 471772 : input logic [pt.DCCM_BITS-1:0] lsu_addr_r, // start address
49 678346 : input logic [pt.DCCM_BITS-1:0] end_addr_r, // end address
50 0 : input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_r, // data from the dccm
51 0 : input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_r, // data from the dccm
52 0 : input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_r, // data from the dccm + ecc
53 0 : input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_r, // data from the dccm + ecc
54 2 : output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_r, // corrected dccm data R-stage
55 2 : output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r, // corrected dccm data R-stage
56 2 : output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_r_ff, // corrected dccm data R+1 stage
57 2 : output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r_ff, // corrected dccm data R+1 stage
58 :
59 4 : input logic ld_single_ecc_error_r, // ld has a single ecc error
60 4 : input logic ld_single_ecc_error_r_ff, // ld has a single ecc error
61 561000 : input logic lsu_dccm_rden_m, // dccm rden
62 614420 : input logic addr_in_dccm_m, // address in dccm
63 471774 : input logic [pt.DCCM_BITS-1:0] lsu_addr_m, // start address
64 678348 : input logic [pt.DCCM_BITS-1:0] end_addr_m, // end address
65 47172 : input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_m, // raw data from mem
66 47172 : input logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_lo_m, // raw data from mem
67 154095 : input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_m, // ecc read out from mem
68 154095 : input logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_lo_m, // ecc read out from mem
69 47172 : output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_m, // corrected dccm data M-stage
70 47172 : output logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_m, // corrected dccm data M-stage
71 :
72 0 : input logic dma_dccm_wen, // Perform DMA writes only for word/dword
73 12 : input logic [31:0] dma_dccm_wdata_lo, // Shifted dma data to lower bits to make it consistent to lsu stores
74 0 : input logic [31:0] dma_dccm_wdata_hi, // Shifted dma data to lower bits to make it consistent to lsu stores
75 0 : output logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_hi, // ECC bits for the DMA wdata
76 50849 : output logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, // ECC bits for the DMA wdata
77 :
78 50849 : output logic [pt.DCCM_ECC_WIDTH-1:0] stbuf_ecc_any, // Encoded data with ECC bits
79 0 : output logic [pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_hi_r_ff, // Encoded data with ECC bits
80 50849 : output logic [pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_lo_r_ff, // Encoded data with ECC bits
81 :
82 0 : output logic single_ecc_error_hi_r, // sec detected
83 4 : output logic single_ecc_error_lo_r, // sec detected on lower dccm bank
84 4 : output logic lsu_single_ecc_error_r, // or of the 2
85 4 : output logic lsu_double_ecc_error_r, // double error detected
86 :
87 4 : output logic lsu_single_ecc_error_m, // or of the 2
88 4 : output logic lsu_double_ecc_error_m // double error detected
89 :
90 : );
91 :
92 0 : logic is_ldst_r;
93 557884 : logic is_ldst_hi_any, is_ldst_lo_any;
94 7376 : logic [pt.DCCM_DATA_WIDTH-1:0] dccm_wdata_hi_any, dccm_wdata_lo_any;
95 50849 : logic [pt.DCCM_ECC_WIDTH-1:0] dccm_wdata_ecc_hi_any, dccm_wdata_ecc_lo_any;
96 47172 : logic [pt.DCCM_DATA_WIDTH-1:0] dccm_rdata_hi_any, dccm_rdata_lo_any;
97 154095 : logic [pt.DCCM_ECC_WIDTH-1:0] dccm_data_ecc_hi_any, dccm_data_ecc_lo_any;
98 47172 : logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_hi_any, sec_data_lo_any;
99 4 : logic single_ecc_error_hi_any, single_ecc_error_lo_any;
100 4 : logic double_ecc_error_hi_any, double_ecc_error_lo_any;
101 :
102 4 : logic double_ecc_error_hi_m, double_ecc_error_lo_m;
103 0 : logic double_ecc_error_hi_r, double_ecc_error_lo_r;
104 :
105 154095 : logic [6:0] ecc_out_hi_nc, ecc_out_lo_nc;
106 :
107 :
108 : if (pt.LOAD_TO_USE_PLUS1 == 1) begin: L2U_Plus1_1
109 : logic ldst_dual_m, ldst_dual_r;
110 : logic is_ldst_m;
111 : logic is_ldst_hi_r, is_ldst_lo_r;
112 :
113 : assign ldst_dual_r = (lsu_addr_r[2] != end_addr_r[2]);
114 : assign is_ldst_r = lsu_pkt_r.valid & (lsu_pkt_r.load | lsu_pkt_r.store) & addr_in_dccm_r & lsu_dccm_rden_r;
115 : assign is_ldst_lo_r = is_ldst_r & ~dec_tlu_core_ecc_disable;
116 : assign is_ldst_hi_r = is_ldst_r & ldst_dual_r & ~dec_tlu_core_ecc_disable; // Always check the ECC Hi/Lo for DMA since we don't align for DMA
117 :
118 : assign is_ldst_hi_any = is_ldst_hi_r;
119 : assign dccm_rdata_hi_any[pt.DCCM_DATA_WIDTH-1:0] = dccm_rdata_hi_r[pt.DCCM_DATA_WIDTH-1:0];
120 : assign dccm_data_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_hi_r[pt.DCCM_ECC_WIDTH-1:0];
121 : assign is_ldst_lo_any = is_ldst_lo_r;
122 : assign dccm_rdata_lo_any[pt.DCCM_DATA_WIDTH-1:0] = dccm_rdata_lo_r[pt.DCCM_DATA_WIDTH-1:0];
123 : assign dccm_data_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_lo_r[pt.DCCM_ECC_WIDTH-1:0];
124 :
125 : assign sec_data_hi_r[pt.DCCM_DATA_WIDTH-1:0] = sec_data_hi_any[pt.DCCM_DATA_WIDTH-1:0];
126 : assign single_ecc_error_hi_r = single_ecc_error_hi_any;
127 : assign double_ecc_error_hi_r = double_ecc_error_hi_any;
128 : assign sec_data_lo_r[pt.DCCM_DATA_WIDTH-1:0] = sec_data_lo_any[pt.DCCM_DATA_WIDTH-1:0];
129 : assign single_ecc_error_lo_r = single_ecc_error_lo_any;
130 : assign double_ecc_error_lo_r = double_ecc_error_lo_any;
131 :
132 : assign lsu_single_ecc_error_r = single_ecc_error_hi_r | single_ecc_error_lo_r;
133 : assign lsu_double_ecc_error_r = double_ecc_error_hi_r | double_ecc_error_lo_r;
134 :
135 : end else begin: L2U_Plus1_0
136 :
137 : logic ldst_dual_m;
138 : logic is_ldst_m;
139 : logic is_ldst_hi_m, is_ldst_lo_m;
140 :
141 : assign ldst_dual_m = (lsu_addr_m[2] != end_addr_m[2]);
142 : assign is_ldst_m = lsu_pkt_m.valid & (lsu_pkt_m.load | lsu_pkt_m.store) & addr_in_dccm_m & lsu_dccm_rden_m;
143 : assign is_ldst_lo_m = is_ldst_m & ~dec_tlu_core_ecc_disable;
144 : assign is_ldst_hi_m = is_ldst_m & (ldst_dual_m | lsu_pkt_m.dma) & ~dec_tlu_core_ecc_disable; // Always check the ECC Hi/Lo for DMA since we don't align for DMA
145 :
146 : assign is_ldst_hi_any = is_ldst_hi_m;
147 : assign dccm_rdata_hi_any[pt.DCCM_DATA_WIDTH-1:0] = dccm_rdata_hi_m[pt.DCCM_DATA_WIDTH-1:0];
148 : assign dccm_data_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_hi_m[pt.DCCM_ECC_WIDTH-1:0];
149 : assign is_ldst_lo_any = is_ldst_lo_m;
150 : assign dccm_rdata_lo_any[pt.DCCM_DATA_WIDTH-1:0] = dccm_rdata_lo_m[pt.DCCM_DATA_WIDTH-1:0];
151 : assign dccm_data_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0] = dccm_data_ecc_lo_m[pt.DCCM_ECC_WIDTH-1:0];
152 :
153 : assign sec_data_hi_m[pt.DCCM_DATA_WIDTH-1:0] = sec_data_hi_any[pt.DCCM_DATA_WIDTH-1:0];
154 : assign double_ecc_error_hi_m = double_ecc_error_hi_any;
155 : assign sec_data_lo_m[pt.DCCM_DATA_WIDTH-1:0] = sec_data_lo_any[pt.DCCM_DATA_WIDTH-1:0];
156 : assign double_ecc_error_lo_m = double_ecc_error_lo_any;
157 :
158 : assign lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any;
159 : assign lsu_double_ecc_error_m = double_ecc_error_hi_m | double_ecc_error_lo_m;
160 :
161 : // Flops
162 : rvdff #(1) lsu_single_ecc_err_r (.din(lsu_single_ecc_error_m), .dout(lsu_single_ecc_error_r), .clk(lsu_c2_r_clk), .*);
163 : rvdff #(1) lsu_double_ecc_err_r (.din(lsu_double_ecc_error_m), .dout(lsu_double_ecc_error_r), .clk(lsu_c2_r_clk), .*);
164 : rvdff #(.WIDTH(1)) ldst_sec_lo_rff (.din(single_ecc_error_lo_any), .dout(single_ecc_error_lo_r), .clk(lsu_c2_r_clk), .*);
165 : rvdff #(.WIDTH(1)) ldst_sec_hi_rff (.din(single_ecc_error_hi_any), .dout(single_ecc_error_hi_r), .clk(lsu_c2_r_clk), .*);
166 : rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_hi_rff (.din(sec_data_hi_m[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_hi_r[pt.DCCM_DATA_WIDTH-1:0]), .en(lsu_single_ecc_error_m | clk_override), .*);
167 : rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_lo_rff (.din(sec_data_lo_m[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_lo_r[pt.DCCM_DATA_WIDTH-1:0]), .en(lsu_single_ecc_error_m | clk_override), .*);
168 :
169 : end
170 :
171 : // Logic for ECC generation during write
172 : assign dccm_wdata_lo_any[pt.DCCM_DATA_WIDTH-1:0] = ld_single_ecc_error_r_ff ? sec_data_lo_r_ff[pt.DCCM_DATA_WIDTH-1:0] : (dma_dccm_wen ? dma_dccm_wdata_lo[pt.DCCM_DATA_WIDTH-1:0] : stbuf_data_any[pt.DCCM_DATA_WIDTH-1:0]);
173 : assign dccm_wdata_hi_any[pt.DCCM_DATA_WIDTH-1:0] = ld_single_ecc_error_r_ff ? sec_data_hi_r_ff[pt.DCCM_DATA_WIDTH-1:0] : (dma_dccm_wen ? dma_dccm_wdata_hi[pt.DCCM_DATA_WIDTH-1:0] : 32'h0);
174 :
175 : assign sec_data_ecc_hi_r_ff[pt.DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0];
176 : assign sec_data_ecc_lo_r_ff[pt.DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0];
177 : assign stbuf_ecc_any[pt.DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0];
178 : assign dma_dccm_wdata_ecc_hi[pt.DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0];
179 : assign dma_dccm_wdata_ecc_lo[pt.DCCM_ECC_WIDTH-1:0] = dccm_wdata_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0];
180 :
181 : // Instantiate ECC blocks
182 : if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
183 :
184 : //Detect/Repair for Hi
185 : rvecc_decode lsu_ecc_decode_hi (
186 : // Inputs
187 : .en(is_ldst_hi_any),
188 : .sed_ded (1'b0), // 1 : means only detection
189 : .din(dccm_rdata_hi_any[pt.DCCM_DATA_WIDTH-1:0]),
190 : .ecc_in(dccm_data_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0]),
191 : // Outputs
192 : .dout(sec_data_hi_any[pt.DCCM_DATA_WIDTH-1:0]),
193 : .ecc_out (ecc_out_hi_nc[6:0]),
194 : .single_ecc_error(single_ecc_error_hi_any),
195 : .double_ecc_error(double_ecc_error_hi_any),
196 : .*
197 : );
198 :
199 : //Detect/Repair for Lo
200 : rvecc_decode lsu_ecc_decode_lo (
201 : // Inputs
202 : .en(is_ldst_lo_any),
203 : .sed_ded (1'b0), // 1 : means only detection
204 : .din(dccm_rdata_lo_any[pt.DCCM_DATA_WIDTH-1:0] ),
205 : .ecc_in(dccm_data_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0]),
206 : // Outputs
207 : .dout(sec_data_lo_any[pt.DCCM_DATA_WIDTH-1:0]),
208 : .ecc_out (ecc_out_lo_nc[6:0]),
209 : .single_ecc_error(single_ecc_error_lo_any),
210 : .double_ecc_error(double_ecc_error_lo_any),
211 : .*
212 : );
213 :
214 : rvecc_encode lsu_ecc_encode_hi (
215 : //Inputs
216 : .din(dccm_wdata_hi_any[pt.DCCM_DATA_WIDTH-1:0]),
217 : //Outputs
218 : .ecc_out(dccm_wdata_ecc_hi_any[pt.DCCM_ECC_WIDTH-1:0]),
219 : .*
220 : );
221 : rvecc_encode lsu_ecc_encode_lo (
222 : //Inputs
223 : .din(dccm_wdata_lo_any[pt.DCCM_DATA_WIDTH-1:0]),
224 : //Outputs
225 : .ecc_out(dccm_wdata_ecc_lo_any[pt.DCCM_ECC_WIDTH-1:0]),
226 : .*
227 : );
228 : end else begin: Gen_dccm_disable // block: Gen_dccm_enable
229 : assign sec_data_hi_any[pt.DCCM_DATA_WIDTH-1:0] = '0;
230 : assign sec_data_lo_any[pt.DCCM_DATA_WIDTH-1:0] = '0;
231 : assign single_ecc_error_hi_any = '0;
232 : assign double_ecc_error_hi_any = '0;
233 : assign single_ecc_error_lo_any = '0;
234 : assign double_ecc_error_lo_any = '0;
235 : end
236 :
237 : rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_hi_rplus1ff (.din(sec_data_hi_r[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_hi_r_ff[pt.DCCM_DATA_WIDTH-1:0]), .en(ld_single_ecc_error_r | clk_override), .clk(clk), .*);
238 : rvdffe #(.WIDTH(pt.DCCM_DATA_WIDTH)) sec_data_lo_rplus1ff (.din(sec_data_lo_r[pt.DCCM_DATA_WIDTH-1:0]), .dout(sec_data_lo_r_ff[pt.DCCM_DATA_WIDTH-1:0]), .en(ld_single_ecc_error_r | clk_override), .clk(clk), .*);
239 :
240 :
241 : endmodule // el2_lsu_ecc
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