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Current view: Cores-VeeR-EL2—Cores-VeeR-EL2—design—lsu—el2_lsu_clkdomain.sv Coverage Hit Total
Test Date: 08-11-2024 Toggle 85.0% 34 40
Test: all Branch 0.0% 0 0

            Line data    Source code
       1              : // Copyright 2020 Western Digital Corporation or its affiliates.
       2              : //
       3              : // Licensed under the Apache License, Version 2.0 (the "License");
       4              : // you may not use this file except in compliance with the License.
       5              : // You may obtain a copy of the License at
       6              : //
       7              : // http://www.apache.org/licenses/LICENSE-2.0
       8              : //
       9              : // Unless required by applicable law or agreed to in writing, software
      10              : // distributed under the License is distributed on an "AS IS" BASIS,
      11              : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      12              : // See the License for the specific language governing permissions and
      13              : // limitations under the License.
      14              : 
      15              : //********************************************************************************
      16              : // $Id$
      17              : //
      18              : //
      19              : // Owner:
      20              : // Function: Clock Generation Block
      21              : // Comments: All the clocks are generate here
      22              : //
      23              : // //********************************************************************************
      24              : 
      25              : 
      26              : module el2_lsu_clkdomain
      27              : import el2_pkg::*;
      28              : #(
      29              : `include "el2_param.vh"
      30              : )(
      31     69890155 :    input logic      clk,                               // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
      32     69890155 :    input logic      active_clk,                        // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
      33          338 :    input logic      rst_l,                             // reset, active low
      34            0 :    input logic      dec_tlu_force_halt,                // This will be high till TLU goes to debug halt
      35              : 
      36              :    // Inputs
      37            2 :    input logic      clk_override,                      // chciken bit to turn off clock gating
      38            0 :    input logic      dma_dccm_req,                      // dma is active
      39       258932 :    input logic      ldst_stbuf_reqvld_r,               // allocating in to the store queue
      40              : 
      41       258448 :    input logic      stbuf_reqvld_any,                  // stbuf is draining
      42            0 :    input logic      stbuf_reqvld_flushed_any,          // instruction going to stbuf is flushed
      43      1668015 :    input logic      lsu_busreq_r,                      // busreq in r
      44       816681 :    input logic      lsu_bus_buffer_pend_any,           // bus buffer has a pending bus entry
      45      1196006 :    input logic      lsu_bus_buffer_empty_any,          // external bus buffer is empty
      46       258787 :    input logic      lsu_stbuf_empty_any,               // stbuf is empty
      47              : 
      48          338 :    input logic      lsu_bus_clk_en,                    // bus clock enable
      49              : 
      50       624113 :    input el2_lsu_pkt_t  lsu_p,                        // lsu packet in decode
      51       478398 :    input el2_lsu_pkt_t  lsu_pkt_d,                    // lsu packet in d
      52       478350 :    input el2_lsu_pkt_t  lsu_pkt_m,                    // lsu packet in m
      53       478347 :    input el2_lsu_pkt_t  lsu_pkt_r,                    // lsu packet in r
      54              : 
      55              :    // Outputs
      56      2052784 :    output logic     lsu_bus_obuf_c1_clken,             // obuf clock enable
      57      1088880 :    output logic     lsu_busm_clken,                    // bus clock enable
      58              : 
      59     69890155 :    output logic     lsu_c1_m_clk,                      // m pipe single pulse clock
      60     69890155 :    output logic     lsu_c1_r_clk,                      // r pipe single pulse clock
      61              : 
      62     69890155 :    output logic     lsu_c2_m_clk,                      // m pipe double pulse clock
      63     69890155 :    output logic     lsu_c2_r_clk,                      // r pipe double pulse clock
      64              : 
      65     69890155 :    output logic     lsu_store_c1_m_clk,                // store in m
      66     69890155 :    output logic     lsu_store_c1_r_clk,                // store in r
      67              : 
      68     69890155 :    output logic     lsu_stbuf_c1_clk,
      69            0 :    output logic     lsu_bus_obuf_c1_clk,               // ibuf clock
      70     69890155 :    output logic     lsu_bus_ibuf_c1_clk,               // ibuf clock
      71     69890155 :    output logic     lsu_bus_buf_c1_clk,                // ibuf clock
      72            0 :    output logic     lsu_busm_clk,                      // bus clock
      73              : 
      74     69890155 :    output logic     lsu_free_c2_clk,                   // free double pulse clock
      75              : 
      76            0 :    input  logic     scan_mode                          // Scan mode
      77              : );
      78              : 
      79      2288158 :    logic lsu_c1_m_clken, lsu_c1_r_clken;
      80      2042897 :    logic lsu_c2_m_clken, lsu_c2_r_clken;
      81      2288131 :    logic lsu_c1_m_clken_q, lsu_c1_r_clken_q;
      82      1073570 :    logic lsu_store_c1_m_clken, lsu_store_c1_r_clken;
      83              : 
      84              : 
      85       200948 :    logic lsu_stbuf_c1_clken;
      86      1088880 :    logic lsu_bus_ibuf_c1_clken, lsu_bus_buf_c1_clken;
      87              : 
      88       856626 :    logic lsu_free_c1_clken, lsu_free_c1_clken_q, lsu_free_c2_clken;
      89              : 
      90              :    //-------------------------------------------------------------------------------------------
      91              :    // Clock Enable logic
      92              :    //-------------------------------------------------------------------------------------------
      93              : 
      94              :    assign lsu_c1_m_clken = lsu_p.valid | dma_dccm_req | clk_override;
      95              :    assign lsu_c1_r_clken = lsu_pkt_m.valid | lsu_c1_m_clken_q | clk_override;
      96              : 
      97              :    assign lsu_c2_m_clken = lsu_c1_m_clken | lsu_c1_m_clken_q | clk_override;
      98              :    assign lsu_c2_r_clken = lsu_c1_r_clken | lsu_c1_r_clken_q | clk_override;
      99              : 
     100              :    assign lsu_store_c1_m_clken = ((lsu_c1_m_clken & lsu_pkt_d.store) | clk_override) ;
     101              :    assign lsu_store_c1_r_clken = ((lsu_c1_r_clken & lsu_pkt_m.store) | clk_override) ;
     102              : 
     103              :    assign lsu_stbuf_c1_clken = ldst_stbuf_reqvld_r | stbuf_reqvld_any | stbuf_reqvld_flushed_any | clk_override;
     104              :    assign lsu_bus_ibuf_c1_clken = lsu_busreq_r | clk_override;
     105              :    assign lsu_bus_obuf_c1_clken = (lsu_bus_buffer_pend_any | lsu_busreq_r | clk_override) & lsu_bus_clk_en;
     106              :    assign lsu_bus_buf_c1_clken  = ~lsu_bus_buffer_empty_any | lsu_busreq_r | dec_tlu_force_halt | clk_override;
     107              : 
     108              :    assign lsu_free_c1_clken = (lsu_p.valid | lsu_pkt_d.valid | lsu_pkt_m.valid | lsu_pkt_r.valid) |
     109              :                               ~lsu_bus_buffer_empty_any | ~lsu_stbuf_empty_any | clk_override;
     110              :    assign lsu_free_c2_clken = lsu_free_c1_clken | lsu_free_c1_clken_q | clk_override;
     111              : 
     112              :     // Flops
     113              :    rvdff #(1) lsu_free_c1_clkenff (.din(lsu_free_c1_clken), .dout(lsu_free_c1_clken_q), .clk(active_clk), .*);
     114              : 
     115              :    rvdff #(1) lsu_c1_m_clkenff (.din(lsu_c1_m_clken), .dout(lsu_c1_m_clken_q), .clk(lsu_free_c2_clk), .*);
     116              :    rvdff #(1) lsu_c1_r_clkenff (.din(lsu_c1_r_clken), .dout(lsu_c1_r_clken_q), .clk(lsu_free_c2_clk), .*);
     117              : 
     118              :    // Clock Headers
     119              :    rvoclkhdr lsu_c1m_cgc ( .en(lsu_c1_m_clken), .l1clk(lsu_c1_m_clk), .* );
     120              :    rvoclkhdr lsu_c1r_cgc ( .en(lsu_c1_r_clken), .l1clk(lsu_c1_r_clk), .* );
     121              : 
     122              :    rvoclkhdr lsu_c2m_cgc ( .en(lsu_c2_m_clken), .l1clk(lsu_c2_m_clk), .* );
     123              :    rvoclkhdr lsu_c2r_cgc ( .en(lsu_c2_r_clken), .l1clk(lsu_c2_r_clk), .* );
     124              : 
     125              :    rvoclkhdr lsu_store_c1m_cgc (.en(lsu_store_c1_m_clken), .l1clk(lsu_store_c1_m_clk), .*);
     126              :    rvoclkhdr lsu_store_c1r_cgc (.en(lsu_store_c1_r_clken), .l1clk(lsu_store_c1_r_clk), .*);
     127              : 
     128              :    rvoclkhdr lsu_stbuf_c1_cgc ( .en(lsu_stbuf_c1_clken), .l1clk(lsu_stbuf_c1_clk), .* );
     129              :    rvoclkhdr lsu_bus_ibuf_c1_cgc ( .en(lsu_bus_ibuf_c1_clken), .l1clk(lsu_bus_ibuf_c1_clk), .* );
     130              :    rvoclkhdr lsu_bus_buf_c1_cgc  ( .en(lsu_bus_buf_c1_clken),  .l1clk(lsu_bus_buf_c1_clk), .* );
     131              : 
     132              :    assign lsu_busm_clken = (~lsu_bus_buffer_empty_any | lsu_busreq_r | clk_override) & lsu_bus_clk_en;
     133              : 
     134              : `ifdef RV_FPGA_OPTIMIZE
     135              :    assign lsu_busm_clk = 1'b0;
     136              :    assign lsu_bus_obuf_c1_clk = 1'b0;
     137              : `else
     138              :    rvclkhdr  lsu_bus_obuf_c1_cgc ( .en(lsu_bus_obuf_c1_clken), .l1clk(lsu_bus_obuf_c1_clk), .* );
     139              :    rvclkhdr  lsu_busm_cgc (.en(lsu_busm_clken), .l1clk(lsu_busm_clk), .*);
     140              : `endif
     141              : 
     142              :    rvoclkhdr lsu_free_cgc (.en(lsu_free_c2_clken), .l1clk(lsu_free_c2_clk), .*);
     143              : 
     144              : endmodule
     145              :