Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 : //********************************************************************************
17 : // $Id$
18 : //
19 : //
20 : // Owner:
21 : // Function: lsu interface with interface queue
22 : // Comments:
23 : //
24 : //********************************************************************************
25 : module el2_lsu_bus_intf
26 : import el2_pkg::*;
27 : #(
28 : `include "el2_param.vh"
29 : )(
30 61843746 : input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
31 0 : input logic clk_override, // Override non-functional clock gating
32 316 : input logic rst_l, // reset, active low
33 0 : input logic scan_mode, // scan mode
34 0 : input logic dec_tlu_external_ldfwd_disable, // disable load to load forwarding for externals
35 4 : input logic dec_tlu_wb_coalescing_disable, // disable write buffer coalescing
36 301 : input logic dec_tlu_sideeffect_posted_disable, // disable the posted sideeffect load store to the bus
37 :
38 : // various clocks needed for the bus reads and writes
39 2035983 : input logic lsu_bus_obuf_c1_clken, // obuf clock enable
40 1088274 : input logic lsu_busm_clken, // bus clock enable
41 :
42 61843746 : input logic lsu_c1_r_clk, // r pipe single pulse clock
43 61843746 : input logic lsu_c2_r_clk, // r pipe double pulse clock
44 61843746 : input logic lsu_bus_ibuf_c1_clk, // ibuf single pulse clock
45 0 : input logic lsu_bus_obuf_c1_clk, // obuf single pulse clock
46 61843746 : input logic lsu_bus_buf_c1_clk, // buf single pulse clock
47 61843746 : input logic lsu_free_c2_clk, // free clock double pulse clock
48 61843746 : input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
49 0 : input logic lsu_busm_clk, // bus clock
50 :
51 2276073 : input logic dec_lsu_valid_raw_d, // Raw valid for address computation
52 1669696 : input logic lsu_busreq_m, // bus request is in m
53 :
54 478184 : input el2_lsu_pkt_t lsu_pkt_m, // lsu packet flowing down the pipe
55 478181 : input el2_lsu_pkt_t lsu_pkt_r, // lsu packet flowing down the pipe
56 :
57 350819 : input logic [31:0] lsu_addr_m, // lsu address flowing down the pipe
58 347000 : input logic [31:0] lsu_addr_r, // lsu address flowing down the pipe
59 :
60 351009 : input logic [31:0] end_addr_m, // lsu address flowing down the pipe
61 347184 : input logic [31:0] end_addr_r, // lsu address flowing down the pipe
62 :
63 54816 : input logic [31:0] store_data_r, // store data flowing down the pipe
64 0 : input logic dec_tlu_force_halt,
65 :
66 2279496 : input logic lsu_commit_r, // lsu instruction in r commits
67 29240 : input logic is_sideeffects_m, // lsu attribute is side_effects
68 58638 : input logic flush_m_up, // flush
69 29654 : input logic flush_r, // flush
70 36568 : input logic ldst_dual_d, ldst_dual_m, ldst_dual_r,
71 :
72 1659482 : output logic lsu_busreq_r, // bus request is in r
73 808157 : output logic lsu_bus_buffer_pend_any, // bus buffer has a pending bus entry
74 49046 : output logic lsu_bus_buffer_full_any, // write buffer is full
75 1187701 : output logic lsu_bus_buffer_empty_any, // write buffer is empty
76 200 : output logic [31:0] bus_read_data_m, // the bus return data
77 :
78 :
79 0 : output logic lsu_imprecise_error_load_any, // imprecise load bus error
80 0 : output logic lsu_imprecise_error_store_any, // imprecise store bus error
81 401 : output logic [31:0] lsu_imprecise_error_addr_any, // address of the imprecise error
82 :
83 : // Non-blocking loads
84 881640 : output logic lsu_nonblock_load_valid_m, // there is an external load -> put in the cam
85 504869 : output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // the tag of the external non block load
86 0 : output logic lsu_nonblock_load_inv_r, // invalidate signal for the cam entry for non block loads
87 504866 : output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
88 920896 : output logic lsu_nonblock_load_data_valid,// the non block is valid - sending information back to the cam
89 0 : output logic lsu_nonblock_load_data_error,// non block load has an error
90 36662 : output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error
91 71560 : output logic [31:0] lsu_nonblock_load_data, // Data of the non block load
92 :
93 : // PMU events
94 1667379 : output logic lsu_pmu_bus_trxn,
95 36420 : output logic lsu_pmu_bus_misaligned,
96 0 : output logic lsu_pmu_bus_error,
97 67818 : output logic lsu_pmu_bus_busy,
98 :
99 : // AXI Write Channels
100 855209 : output logic lsu_axi_awvalid,
101 1107817 : input logic lsu_axi_awready,
102 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
103 401 : output logic [31:0] lsu_axi_awaddr,
104 314 : output logic [3:0] lsu_axi_awregion,
105 0 : output logic [7:0] lsu_axi_awlen,
106 0 : output logic [2:0] lsu_axi_awsize,
107 0 : output logic [1:0] lsu_axi_awburst,
108 0 : output logic lsu_axi_awlock,
109 2985 : output logic [3:0] lsu_axi_awcache,
110 0 : output logic [2:0] lsu_axi_awprot,
111 0 : output logic [3:0] lsu_axi_awqos,
112 :
113 855209 : output logic lsu_axi_wvalid,
114 1107817 : input logic lsu_axi_wready,
115 31411 : output logic [63:0] lsu_axi_wdata,
116 224989 : output logic [7:0] lsu_axi_wstrb,
117 317 : output logic lsu_axi_wlast,
118 :
119 868520 : input logic lsu_axi_bvalid,
120 317 : output logic lsu_axi_bready,
121 0 : input logic [1:0] lsu_axi_bresp,
122 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
123 :
124 : // AXI Read Channels
125 868958 : output logic lsu_axi_arvalid,
126 1115481 : input logic lsu_axi_arready,
127 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
128 401 : output logic [31:0] lsu_axi_araddr,
129 314 : output logic [3:0] lsu_axi_arregion,
130 0 : output logic [7:0] lsu_axi_arlen,
131 0 : output logic [2:0] lsu_axi_arsize,
132 0 : output logic [1:0] lsu_axi_arburst,
133 0 : output logic lsu_axi_arlock,
134 2985 : output logic [3:0] lsu_axi_arcache,
135 0 : output logic [2:0] lsu_axi_arprot,
136 0 : output logic [3:0] lsu_axi_arqos,
137 :
138 929722 : input logic lsu_axi_rvalid,
139 317 : output logic lsu_axi_rready,
140 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
141 28838 : input logic [63:0] lsu_axi_rdata,
142 0 : input logic [1:0] lsu_axi_rresp,
143 :
144 316 : input logic lsu_bus_clk_en
145 :
146 : );
147 :
148 :
149 :
150 316 : logic lsu_bus_clk_en_q;
151 :
152 8172 : logic [3:0] ldst_byteen_m, ldst_byteen_r;
153 0 : logic [7:0] ldst_byteen_ext_m, ldst_byteen_ext_r;
154 0 : logic [3:0] ldst_byteen_hi_m, ldst_byteen_hi_r;
155 431586 : logic [3:0] ldst_byteen_lo_m, ldst_byteen_lo_r;
156 29230 : logic is_sideeffects_r;
157 :
158 125038 : logic [63:0] store_data_ext_r;
159 1948 : logic [31:0] store_data_hi_r;
160 63402 : logic [31:0] store_data_lo_r;
161 :
162 1701223 : logic addr_match_dw_lo_r_m;
163 1659527 : logic addr_match_word_lo_r_m;
164 98804 : logic no_word_merge_r, no_dword_merge_r;
165 :
166 654 : logic ld_addr_rhit_lo_lo, ld_addr_rhit_hi_lo, ld_addr_rhit_lo_hi, ld_addr_rhit_hi_hi;
167 0 : logic [3:0] ld_byte_rhit_lo_lo, ld_byte_rhit_hi_lo, ld_byte_rhit_lo_hi, ld_byte_rhit_hi_hi;
168 :
169 56 : logic [3:0] ld_byte_hit_lo, ld_byte_rhit_lo;
170 0 : logic [3:0] ld_byte_hit_hi, ld_byte_rhit_hi;
171 :
172 16 : logic [31:0] ld_fwddata_rpipe_lo;
173 0 : logic [31:0] ld_fwddata_rpipe_hi;
174 :
175 0 : logic [3:0] ld_byte_hit_buf_lo, ld_byte_hit_buf_hi;
176 74 : logic [31:0] ld_fwddata_buf_lo, ld_fwddata_buf_hi;
177 :
178 74 : logic [63:0] ld_fwddata_lo, ld_fwddata_hi;
179 804 : logic [63:0] ld_fwddata_m;
180 :
181 5698 : logic ld_full_hit_hi_m, ld_full_hit_lo_m;
182 10332 : logic ld_full_hit_m;
183 :
184 : assign ldst_byteen_m[3:0] = ({4{lsu_pkt_m.by}} & 4'b0001) |
185 : ({4{lsu_pkt_m.half}} & 4'b0011) |
186 : ({4{lsu_pkt_m.word}} & 4'b1111);
187 :
188 : // Read/Write Buffer
189 : el2_lsu_bus_buffer #(.pt(pt)) bus_buffer (
190 : .*
191 : );
192 :
193 : // Logic to determine if dc5 store can be coalesced or not with younger stores. Bypass ibuf if cannot colaesced
194 : assign addr_match_dw_lo_r_m = (lsu_addr_r[31:3] == lsu_addr_m[31:3]);
195 : assign addr_match_word_lo_r_m = addr_match_dw_lo_r_m & ~(lsu_addr_r[2]^lsu_addr_m[2]);
196 :
197 : assign no_word_merge_r = lsu_busreq_r & ~ldst_dual_r & lsu_busreq_m & (lsu_pkt_m.load | ~addr_match_word_lo_r_m);
198 : assign no_dword_merge_r = lsu_busreq_r & ~ldst_dual_r & lsu_busreq_m & (lsu_pkt_m.load | ~addr_match_dw_lo_r_m);
199 :
200 : // Create Hi/Lo signals
201 : assign ldst_byteen_ext_m[7:0] = {4'b0,ldst_byteen_m[3:0]} << lsu_addr_m[1:0];
202 : assign ldst_byteen_ext_r[7:0] = {4'b0,ldst_byteen_r[3:0]} << lsu_addr_r[1:0];
203 :
204 : assign store_data_ext_r[63:0] = {32'b0,store_data_r[31:0]} << {lsu_addr_r[1:0],3'b0};
205 :
206 : assign ldst_byteen_hi_m[3:0] = ldst_byteen_ext_m[7:4];
207 : assign ldst_byteen_lo_m[3:0] = ldst_byteen_ext_m[3:0];
208 : assign ldst_byteen_hi_r[3:0] = ldst_byteen_ext_r[7:4];
209 : assign ldst_byteen_lo_r[3:0] = ldst_byteen_ext_r[3:0];
210 :
211 : assign store_data_hi_r[31:0] = store_data_ext_r[63:32];
212 : assign store_data_lo_r[31:0] = store_data_ext_r[31:0];
213 :
214 : assign ld_addr_rhit_lo_lo = (lsu_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;
215 : assign ld_addr_rhit_lo_hi = (end_addr_m[31:2] == lsu_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;
216 : assign ld_addr_rhit_hi_lo = (lsu_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;
217 : assign ld_addr_rhit_hi_hi = (end_addr_m[31:2] == end_addr_r[31:2]) & lsu_pkt_r.valid & lsu_pkt_r.store & lsu_busreq_m & lsu_busreq_r;
218 :
219 : for (genvar i=0; i<4; i++) begin: GenBusBufFwd
220 : assign ld_byte_rhit_lo_lo[i] = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[i] & ldst_byteen_lo_m[i];
221 : assign ld_byte_rhit_lo_hi[i] = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[i] & ldst_byteen_hi_m[i];
222 : assign ld_byte_rhit_hi_lo[i] = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[i] & ldst_byteen_lo_m[i];
223 : assign ld_byte_rhit_hi_hi[i] = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[i] & ldst_byteen_hi_m[i];
224 :
225 : assign ld_byte_hit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i] |
226 : ld_byte_hit_buf_lo[i];
227 :
228 : assign ld_byte_hit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i] |
229 : ld_byte_hit_buf_hi[i];
230 :
231 : assign ld_byte_rhit_lo[i] = ld_byte_rhit_lo_lo[i] | ld_byte_rhit_hi_lo[i];
232 : assign ld_byte_rhit_hi[i] = ld_byte_rhit_lo_hi[i] | ld_byte_rhit_hi_hi[i];
233 :
234 : assign ld_fwddata_rpipe_lo[(8*i)+7:(8*i)] = ({8{ld_byte_rhit_lo_lo[i]}} & store_data_lo_r[(8*i)+7:(8*i)]) |
235 : ({8{ld_byte_rhit_hi_lo[i]}} & store_data_hi_r[(8*i)+7:(8*i)]);
236 :
237 : assign ld_fwddata_rpipe_hi[(8*i)+7:(8*i)] = ({8{ld_byte_rhit_lo_hi[i]}} & store_data_lo_r[(8*i)+7:(8*i)]) |
238 : ({8{ld_byte_rhit_hi_hi[i]}} & store_data_hi_r[(8*i)+7:(8*i)]);
239 :
240 : // Final muxing between m/r
241 : assign ld_fwddata_lo[(8*i)+7:(8*i)] = ld_byte_rhit_lo[i] ? ld_fwddata_rpipe_lo[(8*i)+7:(8*i)] : ld_fwddata_buf_lo[(8*i)+7:(8*i)];
242 :
243 : assign ld_fwddata_hi[(8*i)+7:(8*i)] = ld_byte_rhit_hi[i] ? ld_fwddata_rpipe_hi[(8*i)+7:(8*i)] : ld_fwddata_buf_hi[(8*i)+7:(8*i)];
244 :
245 : end
246 :
247 317 : always_comb begin
248 317 : ld_full_hit_lo_m = 1'b1;
249 317 : ld_full_hit_hi_m = 1'b1;
250 317 : for (int i=0; i<4; i++) begin
251 1268 : ld_full_hit_lo_m &= (ld_byte_hit_lo[i] | ~ldst_byteen_lo_m[i]);
252 1268 : ld_full_hit_hi_m &= (ld_byte_hit_hi[i] | ~ldst_byteen_hi_m[i]);
253 : end
254 : end
255 :
256 : // This will be high if all the bytes of load hit the stores in pipe/write buffer (m/r/wrbuf)
257 : assign ld_full_hit_m = ld_full_hit_lo_m & ld_full_hit_hi_m & lsu_busreq_m & lsu_pkt_m.load & ~is_sideeffects_m;
258 :
259 : assign ld_fwddata_m[63:0] = 64'({ld_fwddata_hi[31:0], ld_fwddata_lo[31:0]} >> (8*lsu_addr_m[1:0]));
260 : assign bus_read_data_m[31:0] = ld_fwddata_m[31:0];
261 :
262 : // Fifo flops
263 :
264 : rvdff #(.WIDTH(1)) clken_ff (.din(lsu_bus_clk_en), .dout(lsu_bus_clk_en_q), .clk(active_clk), .*);
265 :
266 : rvdff #(.WIDTH(1)) is_sideeffects_rff (.din(is_sideeffects_m), .dout(is_sideeffects_r), .clk(lsu_c1_r_clk), .*);
267 :
268 : rvdff #(4) lsu_byten_rff (.*, .din(ldst_byteen_m[3:0]), .dout(ldst_byteen_r[3:0]), .clk(lsu_c1_r_clk));
269 :
270 : `ifdef RV_ASSERT_ON
271 :
272 : // Assertion to check AXI write address is aligned to size
273 : property lsu_axi_awaddr_aligned;
274 : @(posedge lsu_busm_clk) disable iff(~rst_l) lsu_axi_awvalid |-> ((lsu_axi_awsize[2:0] == 3'h0) |
275 : ((lsu_axi_awsize[2:0] == 3'h1) & (lsu_axi_awaddr[0] == 1'b0)) |
276 : ((lsu_axi_awsize[2:0] == 3'h2) & (lsu_axi_awaddr[1:0] == 2'b0)) |
277 : ((lsu_axi_awsize[2:0] == 3'h3) & (lsu_axi_awaddr[2:0] == 3'b0)));
278 : endproperty
279 : assert_lsu_axi_awaddr_aligned: assert property (lsu_axi_awaddr_aligned) else
280 : $display("Assertion lsu_axi_awaddr_aligned failed: lsu_axi_awvalid=1'b%b, lsu_axi_awsize=3'h%h, lsu_axi_awaddr=32'h%h",lsu_axi_awvalid, lsu_axi_awsize[2:0], lsu_axi_awaddr[31:0]);
281 : // Assertion to check awvalid stays stable during entire bus clock
282 :
283 : // Assertion to check AXI read address is aligned to size
284 : property lsu_axi_araddr_aligned;
285 : @(posedge lsu_busm_clk) disable iff(~rst_l) lsu_axi_arvalid |-> ((lsu_axi_arsize[2:0] == 3'h0) |
286 : ((lsu_axi_arsize[2:0] == 3'h1) & (lsu_axi_araddr[0] == 1'b0)) |
287 : ((lsu_axi_arsize[2:0] == 3'h2) & (lsu_axi_araddr[1:0] == 2'b0)) |
288 : ((lsu_axi_arsize[2:0] == 3'h3) & (lsu_axi_araddr[2:0] == 3'b0)));
289 : endproperty
290 : assert_lsu_axi_araddr_aligned: assert property (lsu_axi_araddr_aligned) else
291 : $display("Assertion lsu_axi_araddr_aligned failed: lsu_axi_awvalid=1'b%b, lsu_axi_awsize=3'h%h, lsu_axi_araddr=32'h%h",lsu_axi_awvalid, lsu_axi_awsize[2:0], lsu_axi_araddr[31:0]);
292 :
293 : // Assertion to check awvalid stays stable during entire bus clock
294 : property lsu_axi_awvalid_stable;
295 : @(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid != $past(lsu_axi_awvalid)) |-> ($past(lsu_bus_clk_en) | dec_tlu_force_halt);
296 : endproperty
297 : assert_lsu_axi_awvalid_stable: assert property (lsu_axi_awvalid_stable) else
298 : $display("LSU AXI awvalid changed in middle of bus clock");
299 :
300 : // Assertion to check awid stays stable during entire bus clock
301 : property lsu_axi_awid_stable;
302 : @(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awid[pt.LSU_BUS_TAG-1:0] != $past(lsu_axi_awid[pt.LSU_BUS_TAG-1:0]))) |-> $past(lsu_bus_clk_en);
303 : endproperty
304 : assert_lsu_axi_awid_stable: assert property (lsu_axi_awid_stable) else
305 : $display("LSU AXI awid changed in middle of bus clock");
306 :
307 : // Assertion to check awaddr stays stable during entire bus clock
308 : property lsu_axi_awaddr_stable;
309 : @(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awaddr[31:0] != $past(lsu_axi_awaddr[31:0]))) |-> $past(lsu_bus_clk_en);
310 : endproperty
311 : assert_lsu_axi_awaddr_stable: assert property (lsu_axi_awaddr_stable) else
312 : $display("LSU AXI awaddr changed in middle of bus clock");
313 :
314 : // Assertion to check awsize stays stable during entire bus clock
315 : property lsu_axi_awsize_stable;
316 : @(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_awsize[2:0] != $past(lsu_axi_awsize[2:0]))) |-> $past(lsu_bus_clk_en);
317 : endproperty
318 : assert_lsu_axi_awsize_stable: assert property (lsu_axi_awsize_stable) else
319 : $display("LSU AXI awsize changed in middle of bus clock");
320 :
321 : // Assertion to check wstrb stays stable during entire bus clock
322 : property lsu_axi_wstrb_stable;
323 : @(posedge clk) disable iff(~rst_l) (lsu_axi_wvalid & (lsu_axi_wstrb[7:0] != $past(lsu_axi_wstrb[7:0]))) |-> $past(lsu_bus_clk_en);
324 : endproperty
325 : assert_lsu_axi_wstrb_stable: assert property (lsu_axi_wstrb_stable) else
326 : $display("LSU AXI wstrb changed in middle of bus clock");
327 :
328 : // Assertion to check wdata stays stable during entire bus clock
329 : property lsu_axi_wdata_stable;
330 : @(posedge clk) disable iff(~rst_l) (lsu_axi_wvalid & (lsu_axi_wdata[63:0] != $past(lsu_axi_wdata[63:0]))) |-> $past(lsu_bus_clk_en);
331 : endproperty
332 : assert_lsu_axi_wdata_stable: assert property (lsu_axi_wdata_stable) else
333 : $display("LSU AXI wdata changed in middle of bus clock");
334 :
335 : // Assertion to check awvalid stays stable during entire bus clock
336 : property lsu_axi_arvalid_stable;
337 : @(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid != $past(lsu_axi_arvalid)) |-> ($past(lsu_bus_clk_en) | dec_tlu_force_halt);
338 : endproperty
339 : assert_lsu_axi_arvalid_stable: assert property (lsu_axi_arvalid_stable) else
340 : $display("LSU AXI awvalid changed in middle of bus clock");
341 :
342 : // Assertion to check awid stays stable during entire bus clock
343 : property lsu_axi_arid_stable;
344 : @(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid & (lsu_axi_arid[pt.LSU_BUS_TAG-1:0] != $past(lsu_axi_arid[pt.LSU_BUS_TAG-1:0]))) |-> $past(lsu_bus_clk_en);
345 : endproperty
346 : assert_lsu_axi_arid_stable: assert property (lsu_axi_arid_stable) else
347 : $display("LSU AXI awid changed in middle of bus clock");
348 :
349 : // Assertion to check awaddr stays stable during entire bus clock
350 : property lsu_axi_araddr_stable;
351 : @(posedge clk) disable iff(~rst_l) (lsu_axi_arvalid & (lsu_axi_araddr[31:0] != $past(lsu_axi_araddr[31:0]))) |-> $past(lsu_bus_clk_en);
352 : endproperty
353 : assert_lsu_axi_araddr_stable: assert property (lsu_axi_araddr_stable) else
354 : $display("LSU AXI awaddr changed in middle of bus clock");
355 :
356 : // Assertion to check awsize stays stable during entire bus clock
357 : property lsu_axi_arsize_stable;
358 : @(posedge clk) disable iff(~rst_l) (lsu_axi_awvalid & (lsu_axi_arsize[2:0] != $past(lsu_axi_arsize[2:0]))) |-> $past(lsu_bus_clk_en);
359 : endproperty
360 : assert_lsu_axi_arsize_stable: assert property (lsu_axi_arsize_stable) else
361 : $display("LSU AXI awsize changed in middle of bus clock");
362 :
363 : `endif
364 :
365 : endmodule // el2_lsu_bus_intf
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