Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 : //********************************************************************************
17 : // $Id$
18 : //
19 : //
20 : // Owner:
21 : // Function: lsu interface with interface queue
22 : // Comments:
23 : //
24 : //********************************************************************************
25 :
26 : module el2_lsu_bus_buffer
27 : import el2_pkg::*;
28 : #(
29 : `include "el2_param.vh"
30 : )(
31 61843746 : input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
32 0 : input logic clk_override, // Override non-functional clock gating
33 316 : input logic rst_l, // reset, active low
34 0 : input logic scan_mode, // scan mode
35 0 : input logic dec_tlu_external_ldfwd_disable, // disable load to load forwarding for externals
36 4 : input logic dec_tlu_wb_coalescing_disable, // disable write buffer coalescing
37 301 : input logic dec_tlu_sideeffect_posted_disable, // Don't block the sideeffect load store to the bus
38 0 : input logic dec_tlu_force_halt,
39 :
40 : // various clocks needed for the bus reads and writes
41 2035983 : input logic lsu_bus_obuf_c1_clken,
42 1088274 : input logic lsu_busm_clken,
43 61843746 : input logic lsu_c2_r_clk,
44 61843746 : input logic lsu_bus_ibuf_c1_clk,
45 0 : input logic lsu_bus_obuf_c1_clk,
46 61843746 : input logic lsu_bus_buf_c1_clk,
47 61843746 : input logic lsu_free_c2_clk,
48 0 : input logic lsu_busm_clk,
49 :
50 :
51 2276073 : input logic dec_lsu_valid_raw_d, // Raw valid for address computation
52 478184 : input el2_lsu_pkt_t lsu_pkt_m, // lsu packet flowing down the pipe
53 478181 : input el2_lsu_pkt_t lsu_pkt_r, // lsu packet flowing down the pipe
54 :
55 350819 : input logic [31:0] lsu_addr_m, // lsu address flowing down the pipe
56 351009 : input logic [31:0] end_addr_m, // lsu address flowing down the pipe
57 347000 : input logic [31:0] lsu_addr_r, // lsu address flowing down the pipe
58 347184 : input logic [31:0] end_addr_r, // lsu address flowing down the pipe
59 54816 : input logic [31:0] store_data_r, // store data flowing down the pipe
60 :
61 119084 : input logic no_word_merge_r, // r store doesn't need to wait in ibuf since it will not coalesce
62 98804 : input logic no_dword_merge_r, // r store doesn't need to wait in ibuf since it will not coalesce
63 1669696 : input logic lsu_busreq_m, // bus request is in m
64 1659482 : output logic lsu_busreq_r, // bus request is in r
65 10332 : input logic ld_full_hit_m, // load can get all its byte from a write buffer entry
66 58638 : input logic flush_m_up, // flush
67 29654 : input logic flush_r, // flush
68 2279496 : input logic lsu_commit_r, // lsu instruction in r commits
69 29230 : input logic is_sideeffects_r, // lsu attribute is side_effects
70 36568 : input logic ldst_dual_d, // load/store is unaligned at 32 bit boundary
71 36568 : input logic ldst_dual_m, // load/store is unaligned at 32 bit boundary
72 36568 : input logic ldst_dual_r, // load/store is unaligned at 32 bit boundary
73 :
74 0 : input logic [7:0] ldst_byteen_ext_m, // HI and LO signals
75 :
76 808157 : output logic lsu_bus_buffer_pend_any, // bus buffer has a pending bus entry
77 49046 : output logic lsu_bus_buffer_full_any, // bus buffer is full
78 1187701 : output logic lsu_bus_buffer_empty_any, // bus buffer is empty
79 :
80 0 : output logic [3:0] ld_byte_hit_buf_lo, ld_byte_hit_buf_hi, // Byte enables for forwarding data
81 74 : output logic [31:0] ld_fwddata_buf_lo, ld_fwddata_buf_hi, // load forwarding data
82 :
83 0 : output logic lsu_imprecise_error_load_any, // imprecise load bus error
84 0 : output logic lsu_imprecise_error_store_any, // imprecise store bus error
85 401 : output logic [31:0] lsu_imprecise_error_addr_any, // address of the imprecise error
86 :
87 : // Non-blocking loads
88 881640 : output logic lsu_nonblock_load_valid_m, // there is an external load -> put in the cam
89 504869 : output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // the tag of the external non block load
90 0 : output logic lsu_nonblock_load_inv_r, // invalidate signal for the cam entry for non block loads
91 504866 : output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
92 920896 : output logic lsu_nonblock_load_data_valid, // the non block is valid - sending information back to the cam
93 0 : output logic lsu_nonblock_load_data_error, // non block load has an error
94 36662 : output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error
95 71560 : output logic [31:0] lsu_nonblock_load_data, // Data of the non block load
96 :
97 : // PMU events
98 1667379 : output logic lsu_pmu_bus_trxn,
99 36420 : output logic lsu_pmu_bus_misaligned,
100 0 : output logic lsu_pmu_bus_error,
101 67818 : output logic lsu_pmu_bus_busy,
102 :
103 : // AXI Write Channels
104 855209 : output logic lsu_axi_awvalid,
105 1107817 : input logic lsu_axi_awready,
106 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
107 401 : output logic [31:0] lsu_axi_awaddr,
108 314 : output logic [3:0] lsu_axi_awregion,
109 0 : output logic [7:0] lsu_axi_awlen,
110 0 : output logic [2:0] lsu_axi_awsize,
111 0 : output logic [1:0] lsu_axi_awburst,
112 0 : output logic lsu_axi_awlock,
113 2985 : output logic [3:0] lsu_axi_awcache,
114 0 : output logic [2:0] lsu_axi_awprot,
115 0 : output logic [3:0] lsu_axi_awqos,
116 :
117 855209 : output logic lsu_axi_wvalid,
118 1107817 : input logic lsu_axi_wready,
119 31411 : output logic [63:0] lsu_axi_wdata,
120 224989 : output logic [7:0] lsu_axi_wstrb,
121 317 : output logic lsu_axi_wlast,
122 :
123 868520 : input logic lsu_axi_bvalid,
124 317 : output logic lsu_axi_bready,
125 0 : input logic [1:0] lsu_axi_bresp,
126 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
127 :
128 : // AXI Read Channels
129 868958 : output logic lsu_axi_arvalid,
130 1115481 : input logic lsu_axi_arready,
131 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
132 401 : output logic [31:0] lsu_axi_araddr,
133 314 : output logic [3:0] lsu_axi_arregion,
134 0 : output logic [7:0] lsu_axi_arlen,
135 0 : output logic [2:0] lsu_axi_arsize,
136 0 : output logic [1:0] lsu_axi_arburst,
137 0 : output logic lsu_axi_arlock,
138 2985 : output logic [3:0] lsu_axi_arcache,
139 0 : output logic [2:0] lsu_axi_arprot,
140 0 : output logic [3:0] lsu_axi_arqos,
141 :
142 929722 : input logic lsu_axi_rvalid,
143 317 : output logic lsu_axi_rready,
144 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
145 28838 : input logic [63:0] lsu_axi_rdata,
146 0 : input logic [1:0] lsu_axi_rresp,
147 :
148 316 : input logic lsu_bus_clk_en,
149 316 : input logic lsu_bus_clk_en_q
150 :
151 : );
152 :
153 : // For Ld: IDLE -> START_WAIT -> CMD -> RESP -> DONE_PARTIAL(?) -> DONE_WAIT(?) -> DONE -> IDLE
154 : // For St: IDLE -> START_WAIT -> CMD -> RESP(?) -> IDLE
155 : typedef enum logic [2:0] {IDLE=3'b000, START_WAIT=3'b001, CMD=3'b010, RESP=3'b011, DONE_PARTIAL=3'b100, DONE_WAIT=3'b101, DONE=3'b110} state_t;
156 :
157 : localparam DEPTH = pt.LSU_NUM_NBLOAD;
158 : localparam DEPTH_LOG2 = pt.LSU_NUM_NBLOAD_WIDTH;
159 : localparam TIMER = 8; // This can be only power of 2
160 : localparam TIMER_MAX = TIMER - 1; // Maximum value of timer
161 : localparam TIMER_LOG2 = (TIMER < 2) ? 1 : $clog2(TIMER);
162 :
163 434262 : logic [3:0] ldst_byteen_hi_m, ldst_byteen_lo_m;
164 2450 : logic [DEPTH-1:0] ld_addr_hitvec_lo, ld_addr_hitvec_hi;
165 0 : logic [3:0][DEPTH-1:0] ld_byte_hitvec_lo, ld_byte_hitvec_hi;
166 0 : logic [3:0][DEPTH-1:0] ld_byte_hitvecfn_lo, ld_byte_hitvecfn_hi;
167 :
168 19036 : logic ld_addr_ibuf_hit_lo, ld_addr_ibuf_hit_hi;
169 0 : logic [3:0] ld_byte_ibuf_hit_lo, ld_byte_ibuf_hit_hi;
170 :
171 8172 : logic [3:0] ldst_byteen_r;
172 431718 : logic [3:0] ldst_byteen_hi_r, ldst_byteen_lo_r;
173 62092 : logic [31:0] store_data_hi_r, store_data_lo_r;
174 56512 : logic is_aligned_r; // Aligned load/store
175 18349 : logic ldst_samedw_r;
176 :
177 881494 : logic lsu_nonblock_load_valid_r;
178 45442 : logic [31:0] lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo, lsu_nonblock_data_unalgn;
179 206010 : logic [1:0] lsu_nonblock_addr_offset;
180 129683 : logic [1:0] lsu_nonblock_sz;
181 243322 : logic lsu_nonblock_unsign;
182 920896 : logic lsu_nonblock_load_data_ready;
183 :
184 4572 : logic [DEPTH-1:0] CmdPtr0Dec, CmdPtr1Dec;
185 798 : logic [DEPTH-1:0] RspPtrDec;
186 18787 : logic [DEPTH_LOG2-1:0] CmdPtr0, CmdPtr1;
187 2718 : logic [DEPTH_LOG2-1:0] RspPtr;
188 504866 : logic [DEPTH_LOG2-1:0] WrPtr0_m, WrPtr0_r;
189 563828 : logic [DEPTH_LOG2-1:0] WrPtr1_m, WrPtr1_r;
190 14100 : logic found_wrptr0, found_wrptr1, found_cmdptr0, found_cmdptr1;
191 0 : logic [3:0] buf_numvld_any, buf_numvld_wrcmd_any, buf_numvld_cmd_any, buf_numvld_pend_any;
192 23634 : logic any_done_wait_state;
193 15181 : logic bus_sideeffect_pend;
194 20 : logic bus_coalescing_disable;
195 :
196 87222 : logic bus_addr_match_pending;
197 1662861 : logic bus_cmd_sent, bus_cmd_ready;
198 864881 : logic bus_wcmd_sent, bus_wdata_sent;
199 722090 : logic bus_rsp_read, bus_rsp_write;
200 0 : logic [pt.LSU_BUS_TAG-1:0] bus_rsp_read_tag, bus_rsp_write_tag;
201 0 : logic bus_rsp_read_error, bus_rsp_write_error;
202 28838 : logic [63:0] bus_rsp_rdata;
203 :
204 : // Bus buffer signals
205 12908 : state_t [DEPTH-1:0] buf_state;
206 1239 : logic [DEPTH-1:0][1:0] buf_sz;
207 20 : logic [DEPTH-1:0][31:0] buf_addr;
208 2643 : logic [DEPTH-1:0][3:0] buf_byteen;
209 4 : logic [DEPTH-1:0] buf_sideeffect;
210 2144 : logic [DEPTH-1:0] buf_write;
211 584 : logic [DEPTH-1:0] buf_unsign;
212 62 : logic [DEPTH-1:0] buf_dual;
213 1120 : logic [DEPTH-1:0] buf_samedw;
214 3044 : logic [DEPTH-1:0] buf_nomerge;
215 62 : logic [DEPTH-1:0] buf_dualhi;
216 610 : logic [DEPTH-1:0][DEPTH_LOG2-1:0] buf_dualtag;
217 798 : logic [DEPTH-1:0] buf_ldfwd;
218 1138 : logic [DEPTH-1:0][DEPTH_LOG2-1:0] buf_ldfwdtag;
219 0 : logic [DEPTH-1:0] buf_error;
220 1245 : logic [DEPTH-1:0][31:0] buf_data;
221 0 : logic [DEPTH-1:0][DEPTH-1:0] buf_age, buf_age_younger;
222 0 : logic [DEPTH-1:0][DEPTH-1:0] buf_rspage, buf_rsp_pickage;
223 :
224 13092 : state_t [DEPTH-1:0] buf_nxtstate;
225 12908 : logic [DEPTH-1:0] buf_rst;
226 64458 : logic [DEPTH-1:0] buf_state_en;
227 24620 : logic [DEPTH-1:0] buf_cmd_state_bus_en;
228 24142 : logic [DEPTH-1:0] buf_resp_state_bus_en;
229 43086 : logic [DEPTH-1:0] buf_state_bus_en;
230 36382 : logic [DEPTH-1:0] buf_dual_in;
231 18271 : logic [DEPTH-1:0] buf_samedw_in;
232 102968 : logic [DEPTH-1:0] buf_nomerge_in;
233 26802 : logic [DEPTH-1:0] buf_sideeffect_in;
234 531344 : logic [DEPTH-1:0] buf_unsign_in;
235 462466 : logic [DEPTH-1:0][1:0] buf_sz_in;
236 1060944 : logic [DEPTH-1:0] buf_write_in;
237 24624 : logic [DEPTH-1:0] buf_wr_en;
238 4480 : logic [DEPTH-1:0] buf_dualhi_in;
239 564429 : logic [DEPTH-1:0][DEPTH_LOG2-1:0] buf_dualtag_in;
240 14636 : logic [DEPTH-1:0] buf_ldfwd_en;
241 24622 : logic [DEPTH-1:0] buf_ldfwd_in;
242 2896 : logic [DEPTH-1:0][DEPTH_LOG2-1:0] buf_ldfwdtag_in;
243 432760 : logic [DEPTH-1:0][3:0] buf_byteen_in;
244 347724 : logic [DEPTH-1:0][31:0] buf_addr_in;
245 65090 : logic [DEPTH-1:0][31:0] buf_data_in;
246 0 : logic [DEPTH-1:0] buf_error_en;
247 37352 : logic [DEPTH-1:0] buf_data_en;
248 0 : logic [DEPTH-1:0][DEPTH-1:0] buf_age_in;
249 0 : logic [DEPTH-1:0][DEPTH-1:0] buf_ageQ;
250 0 : logic [DEPTH-1:0][DEPTH-1:0] buf_rspage_set;
251 0 : logic [DEPTH-1:0][DEPTH-1:0] buf_rspage_in;
252 0 : logic [DEPTH-1:0][DEPTH-1:0] buf_rspageQ;
253 :
254 : // Input buffer signals
255 792047 : logic ibuf_valid;
256 12414 : logic ibuf_dual;
257 7882 : logic ibuf_samedw;
258 254 : logic ibuf_nomerge;
259 49236 : logic [DEPTH_LOG2-1:0] ibuf_tag;
260 44004 : logic [DEPTH_LOG2-1:0] ibuf_dualtag;
261 202 : logic ibuf_sideeffect;
262 2 : logic ibuf_unsign;
263 374 : logic ibuf_write;
264 51687 : logic [1:0] ibuf_sz;
265 53388 : logic [3:0] ibuf_byteen;
266 332 : logic [31:0] ibuf_addr;
267 43177 : logic [31:0] ibuf_data;
268 763200 : logic [TIMER_LOG2-1:0] ibuf_timer;
269 :
270 933790 : logic ibuf_byp;
271 800872 : logic ibuf_wr_en;
272 792033 : logic ibuf_rst;
273 312538 : logic ibuf_force_drain;
274 792573 : logic ibuf_drain_vld;
275 11750 : logic [DEPTH-1:0] ibuf_drainvec_vld;
276 505998 : logic [DEPTH_LOG2-1:0] ibuf_tag_in;
277 504866 : logic [DEPTH_LOG2-1:0] ibuf_dualtag_in;
278 458640 : logic [1:0] ibuf_sz_in;
279 347184 : logic [31:0] ibuf_addr_in;
280 405384 : logic [3:0] ibuf_byteen_in;
281 63168 : logic [31:0] ibuf_data_in;
282 763210 : logic [TIMER_LOG2-1:0] ibuf_timer_in;
283 53568 : logic [3:0] ibuf_byteen_out;
284 43225 : logic [31:0] ibuf_data_out;
285 1305 : logic ibuf_merge_en, ibuf_merge_in;
286 :
287 : // Output buffer signals
288 1569521 : logic obuf_valid;
289 281646 : logic obuf_write;
290 23634 : logic obuf_nosend;
291 911064 : logic obuf_rdrsp_pend;
292 2668 : logic obuf_sideeffect;
293 401 : logic [31:0] obuf_addr;
294 31411 : logic [63:0] obuf_data;
295 124860 : logic [1:0] obuf_sz;
296 424295 : logic [7:0] obuf_byteen;
297 8190 : logic obuf_merge;
298 0 : logic obuf_cmd_done, obuf_data_done;
299 0 : logic [pt.LSU_BUS_TAG-1:0] obuf_tag0;
300 0 : logic [pt.LSU_BUS_TAG-1:0] obuf_tag1;
301 0 : logic [pt.LSU_BUS_TAG-1:0] obuf_rdrsp_tag;
302 :
303 809676 : logic ibuf_buf_byp;
304 65546 : logic obuf_force_wr_en;
305 314770 : logic obuf_wr_wait;
306 1606909 : logic obuf_wr_en, obuf_wr_enQ;
307 1569517 : logic obuf_rst;
308 333238 : logic obuf_write_in;
309 714540 : logic obuf_nosend_in;
310 316 : logic obuf_rdrsp_pend_en;
311 911064 : logic obuf_rdrsp_pend_in;
312 2812 : logic obuf_sideeffect_in;
313 46727 : logic obuf_aligned_in;
314 401 : logic [31:0] obuf_addr_in;
315 67746 : logic [63:0] obuf_data_in;
316 151902 : logic [1:0] obuf_sz_in;
317 458692 : logic [7:0] obuf_byteen_in;
318 15566 : logic obuf_merge_in;
319 0 : logic obuf_cmd_done_in, obuf_data_done_in;
320 0 : logic [pt.LSU_BUS_TAG-1:0] obuf_tag0_in;
321 0 : logic [pt.LSU_BUS_TAG-1:0] obuf_tag1_in;
322 0 : logic [pt.LSU_BUS_TAG-1:0] obuf_rdrsp_tag_in;
323 :
324 15566 : logic obuf_merge_en;
325 288436 : logic [TIMER_LOG2-1:0] obuf_wr_timer, obuf_wr_timer_in;
326 290998 : logic [7:0] obuf_byteen0_in, obuf_byteen1_in;
327 46595 : logic [63:0] obuf_data0_in, obuf_data1_in;
328 :
329 854945 : logic lsu_axi_awvalid_q, lsu_axi_awready_q;
330 854945 : logic lsu_axi_wvalid_q, lsu_axi_wready_q;
331 879147 : logic lsu_axi_arvalid_q, lsu_axi_arready_q;
332 314 : logic lsu_axi_bvalid_q, lsu_axi_bready_q;
333 314 : logic lsu_axi_rvalid_q, lsu_axi_rready_q;
334 0 : logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid_q, lsu_axi_rid_q;
335 0 : logic [1:0] lsu_axi_bresp_q, lsu_axi_rresp_q;
336 0 : logic [pt.LSU_BUS_TAG-1:0] lsu_imprecise_error_store_tag;
337 28837 : logic [63:0] lsu_axi_rdata_q;
338 :
339 : //------------------------------------------------------------------------------
340 : // Load forwarding logic start
341 : //------------------------------------------------------------------------------
342 :
343 : // Function to do 8 to 3 bit encoding
344 74791394 : function automatic logic [2:0] f_Enc8to3;
345 : input logic [7:0] Dec_value;
346 :
347 : logic [2:0] Enc_value;
348 74791394 : Enc_value[0] = Dec_value[1] | Dec_value[3] | Dec_value[5] | Dec_value[7];
349 74791394 : Enc_value[1] = Dec_value[2] | Dec_value[3] | Dec_value[6] | Dec_value[7];
350 74791394 : Enc_value[2] = Dec_value[4] | Dec_value[5] | Dec_value[6] | Dec_value[7];
351 :
352 74791394 : return Enc_value[2:0];
353 : endfunction // f_Enc8to3
354 :
355 : // Buffer hit logic for bus load forwarding
356 : assign ldst_byteen_hi_m[3:0] = ldst_byteen_ext_m[7:4];
357 : assign ldst_byteen_lo_m[3:0] = ldst_byteen_ext_m[3:0];
358 : for (genvar i=0; i<DEPTH; i++) begin
359 : assign ld_addr_hitvec_lo[i] = (lsu_addr_m[31:2] == buf_addr[i][31:2]) & buf_write[i] & (buf_state[i] != IDLE) & lsu_busreq_m;
360 : assign ld_addr_hitvec_hi[i] = (end_addr_m[31:2] == buf_addr[i][31:2]) & buf_write[i] & (buf_state[i] != IDLE) & lsu_busreq_m;
361 : end
362 :
363 : for (genvar j=0; j<4; j++) begin
364 : assign ld_byte_hit_buf_lo[j] = |(ld_byte_hitvecfn_lo[j]) | ld_byte_ibuf_hit_lo[j];
365 : assign ld_byte_hit_buf_hi[j] = |(ld_byte_hitvecfn_hi[j]) | ld_byte_ibuf_hit_hi[j];
366 : for (genvar i=0; i<DEPTH; i++) begin
367 : assign ld_byte_hitvec_lo[j][i] = ld_addr_hitvec_lo[i] & buf_byteen[i][j] & ldst_byteen_lo_m[j];
368 : assign ld_byte_hitvec_hi[j][i] = ld_addr_hitvec_hi[i] & buf_byteen[i][j] & ldst_byteen_hi_m[j];
369 :
370 : assign ld_byte_hitvecfn_lo[j][i] = ld_byte_hitvec_lo[j][i] & ~(|(ld_byte_hitvec_lo[j] & buf_age_younger[i])) & ~ld_byte_ibuf_hit_lo[j]; // Kill the byte enable if younger entry exists or byte exists in ibuf
371 : assign ld_byte_hitvecfn_hi[j][i] = ld_byte_hitvec_hi[j][i] & ~(|(ld_byte_hitvec_hi[j] & buf_age_younger[i])) & ~ld_byte_ibuf_hit_hi[j]; // Kill the byte enable if younger entry exists or byte exists in ibuf
372 : end
373 : end
374 :
375 : // Hit in the ibuf
376 : assign ld_addr_ibuf_hit_lo = (lsu_addr_m[31:2] == ibuf_addr[31:2]) & ibuf_write & ibuf_valid & lsu_busreq_m;
377 : assign ld_addr_ibuf_hit_hi = (end_addr_m[31:2] == ibuf_addr[31:2]) & ibuf_write & ibuf_valid & lsu_busreq_m;
378 :
379 : for (genvar i=0; i<4; i++) begin
380 : assign ld_byte_ibuf_hit_lo[i] = ld_addr_ibuf_hit_lo & ibuf_byteen[i] & ldst_byteen_lo_m[i];
381 : assign ld_byte_ibuf_hit_hi[i] = ld_addr_ibuf_hit_hi & ibuf_byteen[i] & ldst_byteen_hi_m[i];
382 : end
383 :
384 317 : always_comb begin
385 317 : ld_fwddata_buf_lo[31:0] = {{8{ld_byte_ibuf_hit_lo[3]}},{8{ld_byte_ibuf_hit_lo[2]}},{8{ld_byte_ibuf_hit_lo[1]}},{8{ld_byte_ibuf_hit_lo[0]}}} & ibuf_data[31:0];
386 317 : ld_fwddata_buf_hi[31:0] = {{8{ld_byte_ibuf_hit_hi[3]}},{8{ld_byte_ibuf_hit_hi[2]}},{8{ld_byte_ibuf_hit_hi[1]}},{8{ld_byte_ibuf_hit_hi[0]}}} & ibuf_data[31:0];
387 317 : for (int i=0; i<DEPTH; i++) begin
388 1268 : ld_fwddata_buf_lo[7:0] |= {8{ld_byte_hitvecfn_lo[0][i]}} & buf_data[i][7:0];
389 1268 : ld_fwddata_buf_lo[15:8] |= {8{ld_byte_hitvecfn_lo[1][i]}} & buf_data[i][15:8];
390 1268 : ld_fwddata_buf_lo[23:16] |= {8{ld_byte_hitvecfn_lo[2][i]}} & buf_data[i][23:16];
391 1268 : ld_fwddata_buf_lo[31:24] |= {8{ld_byte_hitvecfn_lo[3][i]}} & buf_data[i][31:24];
392 :
393 1268 : ld_fwddata_buf_hi[7:0] |= {8{ld_byte_hitvecfn_hi[0][i]}} & buf_data[i][7:0];
394 1268 : ld_fwddata_buf_hi[15:8] |= {8{ld_byte_hitvecfn_hi[1][i]}} & buf_data[i][15:8];
395 1268 : ld_fwddata_buf_hi[23:16] |= {8{ld_byte_hitvecfn_hi[2][i]}} & buf_data[i][23:16];
396 1268 : ld_fwddata_buf_hi[31:24] |= {8{ld_byte_hitvecfn_hi[3][i]}} & buf_data[i][31:24];
397 : end
398 : end
399 :
400 : //------------------------------------------------------------------------------
401 : // Load forwarding logic end
402 : //------------------------------------------------------------------------------
403 :
404 : assign bus_coalescing_disable = dec_tlu_wb_coalescing_disable | pt.BUILD_AHB_LITE;
405 :
406 : // Get the hi/lo byte enable
407 : assign ldst_byteen_r[3:0] = ({4{lsu_pkt_r.by}} & 4'b0001) |
408 : ({4{lsu_pkt_r.half}} & 4'b0011) |
409 : ({4{lsu_pkt_r.word}} & 4'b1111);
410 :
411 : assign {ldst_byteen_hi_r[3:0], ldst_byteen_lo_r[3:0]} = {4'b0,ldst_byteen_r[3:0]} << lsu_addr_r[1:0];
412 : assign {store_data_hi_r[31:0], store_data_lo_r[31:0]} = {32'b0,store_data_r[31:0]} << 8*lsu_addr_r[1:0];
413 : assign ldst_samedw_r = (lsu_addr_r[3] == end_addr_r[3]);
414 : assign is_aligned_r = (lsu_pkt_r.word & (lsu_addr_r[1:0] == 2'b0)) |
415 : (lsu_pkt_r.half & (lsu_addr_r[0] == 1'b0)) |
416 : lsu_pkt_r.by;
417 :
418 : //------------------------------------------------------------------------------
419 : // Input buffer logic starts here
420 : //------------------------------------------------------------------------------
421 :
422 : assign ibuf_byp = lsu_busreq_r & (lsu_pkt_r.load | no_word_merge_r) & ~ibuf_valid;
423 : assign ibuf_wr_en = lsu_busreq_r & lsu_commit_r & ~ibuf_byp;
424 : assign ibuf_rst = (ibuf_drain_vld & ~ibuf_wr_en) | dec_tlu_force_halt;
425 : assign ibuf_force_drain = lsu_busreq_m & ~lsu_busreq_r & ibuf_valid & (lsu_pkt_m.load | (ibuf_addr[31:2] != lsu_addr_m[31:2])); // Move the ibuf to buf if there is a non-colaescable ld/st in m but nothing in r
426 : assign ibuf_drain_vld = ibuf_valid & (((ibuf_wr_en | (ibuf_timer == TIMER_MAX)) & ~(ibuf_merge_en & ibuf_merge_in)) | ibuf_byp | ibuf_force_drain | ibuf_sideeffect | ~ibuf_write | bus_coalescing_disable);
427 : assign ibuf_tag_in[DEPTH_LOG2-1:0] = (ibuf_merge_en & ibuf_merge_in) ? ibuf_tag[DEPTH_LOG2-1:0] : (ldst_dual_r ? WrPtr1_r : WrPtr0_r);
428 : assign ibuf_dualtag_in[DEPTH_LOG2-1:0] = WrPtr0_r;
429 : assign ibuf_sz_in[1:0] = {lsu_pkt_r.word, lsu_pkt_r.half};
430 : assign ibuf_addr_in[31:0] = ldst_dual_r ? end_addr_r[31:0] : lsu_addr_r[31:0];
431 : assign ibuf_byteen_in[3:0] = (ibuf_merge_en & ibuf_merge_in) ? (ibuf_byteen[3:0] | ldst_byteen_lo_r[3:0]) : (ldst_dual_r ? ldst_byteen_hi_r[3:0] : ldst_byteen_lo_r[3:0]);
432 : for (genvar i=0; i<4; i++) begin
433 : assign ibuf_data_in[(8*i)+7:(8*i)] = (ibuf_merge_en & ibuf_merge_in) ? (ldst_byteen_lo_r[i] ? store_data_lo_r[(8*i)+7:(8*i)] : ibuf_data[(8*i)+7:(8*i)]) :
434 : (ldst_dual_r ? store_data_hi_r[(8*i)+7:(8*i)] : store_data_lo_r[(8*i)+7:(8*i)]);
435 : end
436 : assign ibuf_timer_in = ibuf_wr_en ? '0 : (ibuf_timer < TIMER_MAX) ? (ibuf_timer + 1'b1) : ibuf_timer;
437 :
438 :
439 : assign ibuf_merge_en = lsu_busreq_r & lsu_commit_r & lsu_pkt_r.store & ibuf_valid & ibuf_write & (lsu_addr_r[31:2] == ibuf_addr[31:2]) & ~is_sideeffects_r & ~bus_coalescing_disable;
440 : assign ibuf_merge_in = ~ldst_dual_r; // If it's a unaligned store, merge needs to happen on the way out of ibuf
441 :
442 : // ibuf signals going to bus buffer after merging
443 : for (genvar i=0; i<4; i++) begin
444 : assign ibuf_byteen_out[i] = (ibuf_merge_en & ~ibuf_merge_in) ? (ibuf_byteen[i] | ldst_byteen_lo_r[i]) : ibuf_byteen[i];
445 : assign ibuf_data_out[(8*i)+7:(8*i)] = (ibuf_merge_en & ~ibuf_merge_in) ? (ldst_byteen_lo_r[i] ? store_data_lo_r[(8*i)+7:(8*i)] : ibuf_data[(8*i)+7:(8*i)]) :
446 : ibuf_data[(8*i)+7:(8*i)];
447 : end
448 :
449 : rvdffsc #(.WIDTH(1)) ibuf_valid_ff (.din(1'b1), .dout(ibuf_valid), .en(ibuf_wr_en), .clear(ibuf_rst), .clk(lsu_free_c2_clk), .*);
450 : rvdffs #(.WIDTH(DEPTH_LOG2)) ibuf_tagff (.din(ibuf_tag_in), .dout(ibuf_tag), .en(ibuf_wr_en), .clk(lsu_bus_ibuf_c1_clk), .*);
451 : rvdffs #(.WIDTH(DEPTH_LOG2)) ibuf_dualtagff (.din(ibuf_dualtag_in), .dout(ibuf_dualtag), .en(ibuf_wr_en), .clk(lsu_bus_ibuf_c1_clk), .*);
452 : rvdffs #(.WIDTH(1)) ibuf_dualff (.din(ldst_dual_r), .dout(ibuf_dual), .en(ibuf_wr_en), .clk(lsu_bus_ibuf_c1_clk), .*);
453 : rvdffs #(.WIDTH(1)) ibuf_samedwff (.din(ldst_samedw_r), .dout(ibuf_samedw), .en(ibuf_wr_en), .clk(lsu_bus_ibuf_c1_clk), .*);
454 : rvdffs #(.WIDTH(1)) ibuf_nomergeff (.din(no_dword_merge_r), .dout(ibuf_nomerge), .en(ibuf_wr_en), .clk(lsu_bus_ibuf_c1_clk), .*);
455 : rvdffs #(.WIDTH(1)) ibuf_sideeffectff (.din(is_sideeffects_r), .dout(ibuf_sideeffect), .en(ibuf_wr_en), .clk(lsu_bus_ibuf_c1_clk), .*);
456 : rvdffs #(.WIDTH(1)) ibuf_unsignff (.din(lsu_pkt_r.unsign), .dout(ibuf_unsign), .en(ibuf_wr_en), .clk(lsu_bus_ibuf_c1_clk), .*);
457 : rvdffs #(.WIDTH(1)) ibuf_writeff (.din(lsu_pkt_r.store), .dout(ibuf_write), .en(ibuf_wr_en), .clk(lsu_bus_ibuf_c1_clk), .*);
458 : rvdffs #(.WIDTH(2)) ibuf_szff (.din(ibuf_sz_in[1:0]), .dout(ibuf_sz), .en(ibuf_wr_en), .clk(lsu_bus_ibuf_c1_clk), .*);
459 : rvdffe #(.WIDTH(32)) ibuf_addrff (.din(ibuf_addr_in[31:0]), .dout(ibuf_addr), .en(ibuf_wr_en), .*);
460 : rvdffs #(.WIDTH(4)) ibuf_byteenff (.din(ibuf_byteen_in[3:0]), .dout(ibuf_byteen), .en(ibuf_wr_en), .clk(lsu_bus_ibuf_c1_clk), .*);
461 : rvdffe #(.WIDTH(32)) ibuf_dataff (.din(ibuf_data_in[31:0]), .dout(ibuf_data), .en(ibuf_wr_en), .*);
462 : rvdff #(.WIDTH(TIMER_LOG2)) ibuf_timerff (.din(ibuf_timer_in), .dout(ibuf_timer), .clk(lsu_free_c2_clk), .*);
463 :
464 :
465 : //------------------------------------------------------------------------------
466 : // Input buffer logic ends here
467 : //------------------------------------------------------------------------------
468 :
469 :
470 : //------------------------------------------------------------------------------
471 : // Output buffer logic starts here
472 : //------------------------------------------------------------------------------
473 :
474 : assign obuf_wr_wait = (buf_numvld_wrcmd_any[3:0] == 4'b1) & (buf_numvld_cmd_any[3:0] == 4'b1) & (obuf_wr_timer != TIMER_MAX) &
475 : ~bus_coalescing_disable & ~buf_nomerge[CmdPtr0] & ~buf_sideeffect[CmdPtr0] & ~obuf_force_wr_en;
476 : assign obuf_wr_timer_in = obuf_wr_en ? 3'b0: (((buf_numvld_cmd_any > 4'b0) & (obuf_wr_timer < TIMER_MAX)) ? (obuf_wr_timer + 1'b1) : obuf_wr_timer);
477 : assign obuf_force_wr_en = lsu_busreq_m & ~lsu_busreq_r & ~ibuf_valid & (buf_numvld_cmd_any[3:0] == 4'b1) & (lsu_addr_m[31:2] != buf_addr[CmdPtr0][31:2]); // Entry in m can't merge with entry going to obuf and there is no entry in between
478 : assign ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any[3:0] == 4'b0) & (~lsu_pkt_r.store | no_dword_merge_r);
479 :
480 : assign obuf_wr_en = ((ibuf_buf_byp & lsu_commit_r & ~(is_sideeffects_r & bus_sideeffect_pend)) |
481 : ((buf_state[CmdPtr0] == CMD) & found_cmdptr0 & ~buf_cmd_state_bus_en[CmdPtr0] & ~(buf_sideeffect[CmdPtr0] & bus_sideeffect_pend) &
482 : (~(buf_dual[CmdPtr0] & buf_samedw[CmdPtr0] & ~buf_write[CmdPtr0]) | found_cmdptr1 | buf_nomerge[CmdPtr0] | obuf_force_wr_en))) &
483 : (bus_cmd_ready | ~obuf_valid | obuf_nosend) & ~obuf_wr_wait & ~bus_addr_match_pending & lsu_bus_clk_en;
484 :
485 : assign obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & ~obuf_wr_en & lsu_bus_clk_en) | dec_tlu_force_halt;
486 :
487 : assign obuf_write_in = ibuf_buf_byp ? lsu_pkt_r.store : buf_write[CmdPtr0];
488 : assign obuf_sideeffect_in = ibuf_buf_byp ? is_sideeffects_r : buf_sideeffect[CmdPtr0];
489 : assign obuf_addr_in[31:0] = ibuf_buf_byp ? lsu_addr_r[31:0] : buf_addr[CmdPtr0];
490 : assign obuf_sz_in[1:0] = ibuf_buf_byp ? {lsu_pkt_r.word, lsu_pkt_r.half} : buf_sz[CmdPtr0];
491 : assign obuf_merge_in = obuf_merge_en;
492 : assign obuf_tag0_in[pt.LSU_BUS_TAG-1:0] = ibuf_buf_byp ? (pt.LSU_BUS_TAG)'(WrPtr0_r) : (pt.LSU_BUS_TAG)'(CmdPtr0);
493 : assign obuf_tag1_in[pt.LSU_BUS_TAG-1:0] = ibuf_buf_byp ? (pt.LSU_BUS_TAG)'(WrPtr1_r) : (pt.LSU_BUS_TAG)'(CmdPtr1);
494 :
495 : assign obuf_cmd_done_in = ~(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent);
496 : assign obuf_data_done_in = ~(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent);
497 :
498 : assign obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : ((obuf_sz_in[1:0] == 2'b0) |
499 : (obuf_sz_in[0] & ~obuf_addr_in[0]) |
500 : (obuf_sz_in[1] & ~(|obuf_addr_in[1:0])));
501 :
502 : assign obuf_rdrsp_pend_in = ((~(obuf_wr_en & ~obuf_nosend_in) & obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag))) | (bus_cmd_sent & ~obuf_write)) & ~dec_tlu_force_halt;
503 : assign obuf_rdrsp_pend_en = lsu_bus_clk_en | dec_tlu_force_halt;
504 : assign obuf_rdrsp_tag_in[pt.LSU_BUS_TAG-1:0] = (bus_cmd_sent & ~obuf_write) ? obuf_tag0[pt.LSU_BUS_TAG-1:0] : obuf_rdrsp_tag[pt.LSU_BUS_TAG-1:0];
505 : // No ld to ld fwd for aligned
506 : assign obuf_nosend_in = (obuf_addr_in[31:3] == obuf_addr[31:3]) & obuf_aligned_in & ~obuf_sideeffect & ~obuf_write & ~obuf_write_in & ~dec_tlu_external_ldfwd_disable &
507 : ((obuf_valid & ~obuf_nosend) | (obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag))));
508 :
509 : assign obuf_byteen0_in[7:0] = ibuf_buf_byp ? (lsu_addr_r[2] ? {ldst_byteen_lo_r[3:0],4'b0} : {4'b0,ldst_byteen_lo_r[3:0]}) :
510 : (buf_addr[CmdPtr0][2] ? {buf_byteen[CmdPtr0],4'b0} : {4'b0,buf_byteen[CmdPtr0]});
511 : assign obuf_byteen1_in[7:0] = ibuf_buf_byp ? (end_addr_r[2] ? {ldst_byteen_hi_r[3:0],4'b0} : {4'b0,ldst_byteen_hi_r[3:0]}) :
512 : (buf_addr[CmdPtr1][2] ? {buf_byteen[CmdPtr1],4'b0} : {4'b0,buf_byteen[CmdPtr1]});
513 : assign obuf_data0_in[63:0] = ibuf_buf_byp ? (lsu_addr_r[2] ? {store_data_lo_r[31:0],32'b0} : {32'b0,store_data_lo_r[31:0]}) :
514 : (buf_addr[CmdPtr0][2] ? {buf_data[CmdPtr0],32'b0} : {32'b0,buf_data[CmdPtr0]});
515 : assign obuf_data1_in[63:0] = ibuf_buf_byp ? (end_addr_r[2] ? {store_data_hi_r[31:0],32'b0} :{32'b0,store_data_hi_r[31:0]}) :
516 : (buf_addr[CmdPtr1][2] ? {buf_data[CmdPtr1],32'b0} : {32'b0,buf_data[CmdPtr1]});
517 :
518 : for (genvar i=0 ;i<8; i++) begin
519 : assign obuf_byteen_in[i] = obuf_byteen0_in[i] | (obuf_merge_en & obuf_byteen1_in[i]);
520 : assign obuf_data_in[(8*i)+7:(8*i)] = (obuf_merge_en & obuf_byteen1_in[i]) ? obuf_data1_in[(8*i)+7:(8*i)] : obuf_data0_in[(8*i)+7:(8*i)];
521 : end
522 :
523 : // No store obuf merging for AXI since all stores are sent non-posted. Can't track the second id right now
524 : assign obuf_merge_en = ((CmdPtr0 != CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (buf_state[CmdPtr0] == CMD) & (buf_state[CmdPtr1] == CMD) &
525 : ~buf_cmd_state_bus_en[CmdPtr0] & ~buf_sideeffect[CmdPtr0] &
526 : (~buf_write[CmdPtr0] & buf_dual[CmdPtr0] & ~buf_dualhi[CmdPtr0] & buf_samedw[CmdPtr0])) | // CmdPtr0/CmdPtr1 are for same load which is within a DW
527 : (ibuf_buf_byp & ldst_samedw_r & ldst_dual_r);
528 :
529 :
530 : rvdff_fpga #(.WIDTH(1)) obuf_wren_ff (.din(obuf_wr_en), .dout(obuf_wr_enQ), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
531 : rvdffsc #(.WIDTH(1)) obuf_valid_ff (.din(1'b1), .dout(obuf_valid), .en(obuf_wr_en), .clear(obuf_rst), .clk(lsu_free_c2_clk), .*);
532 : rvdffs #(.WIDTH(1)) obuf_nosend_ff (.din(obuf_nosend_in), .dout(obuf_nosend), .en(obuf_wr_en), .clk(lsu_free_c2_clk), .*);
533 : rvdffs #(.WIDTH(1)) obuf_rdrsp_pend_ff(.din(obuf_rdrsp_pend_in), .dout(obuf_rdrsp_pend), .en(obuf_rdrsp_pend_en), .clk(lsu_free_c2_clk), .*);
534 : rvdff_fpga #(.WIDTH(1)) obuf_cmd_done_ff (.din(obuf_cmd_done_in), .dout(obuf_cmd_done), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
535 : rvdff_fpga #(.WIDTH(1)) obuf_data_done_ff (.din(obuf_data_done_in), .dout(obuf_data_done), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
536 : rvdff_fpga #(.WIDTH(pt.LSU_BUS_TAG)) obuf_rdrsp_tagff (.din(obuf_rdrsp_tag_in), .dout(obuf_rdrsp_tag), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
537 : rvdffs_fpga #(.WIDTH(pt.LSU_BUS_TAG)) obuf_tag0ff (.din(obuf_tag0_in), .dout(obuf_tag0), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);
538 : rvdffs_fpga #(.WIDTH(pt.LSU_BUS_TAG)) obuf_tag1ff (.din(obuf_tag1_in), .dout(obuf_tag1), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);
539 : rvdffs_fpga #(.WIDTH(1)) obuf_mergeff (.din(obuf_merge_in), .dout(obuf_merge), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);
540 : rvdffs_fpga #(.WIDTH(1)) obuf_writeff (.din(obuf_write_in), .dout(obuf_write), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);
541 : rvdffs_fpga #(.WIDTH(1)) obuf_sideeffectff (.din(obuf_sideeffect_in), .dout(obuf_sideeffect), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);
542 : rvdffs_fpga #(.WIDTH(2)) obuf_szff (.din(obuf_sz_in[1:0]), .dout(obuf_sz), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);
543 : rvdffs_fpga #(.WIDTH(8)) obuf_byteenff (.din(obuf_byteen_in[7:0]), .dout(obuf_byteen), .en(obuf_wr_en), .clk(lsu_bus_obuf_c1_clk), .clken(lsu_bus_obuf_c1_clken), .rawclk(clk), .*);
544 : rvdffe #(.WIDTH(32)) obuf_addrff (.din(obuf_addr_in[31:0]), .dout(obuf_addr), .en(obuf_wr_en), .*);
545 : rvdffe #(.WIDTH(64)) obuf_dataff (.din(obuf_data_in[63:0]), .dout(obuf_data), .en(obuf_wr_en), .*);
546 : rvdff_fpga #(.WIDTH(TIMER_LOG2)) obuf_timerff (.din(obuf_wr_timer_in), .dout(obuf_wr_timer), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
547 :
548 :
549 : //------------------------------------------------------------------------------
550 : // Output buffer logic ends here
551 : //------------------------------------------------------------------------------
552 :
553 : // Find the entry to allocate and entry to send
554 317 : always_comb begin
555 317 : WrPtr0_m[DEPTH_LOG2-1:0] = '0;
556 317 : WrPtr1_m[DEPTH_LOG2-1:0] = '0;
557 317 : found_wrptr0 = '0;
558 317 : found_wrptr1 = '0;
559 :
560 : // Find first write pointer
561 317 : for (int i=0; i<DEPTH; i++) begin
562 88926 : if (~found_wrptr0) begin
563 88618 : WrPtr0_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
564 88618 : found_wrptr0 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i)) |
565 88618 : (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
566 : end
567 : end
568 :
569 : // Find second write pointer
570 317 : for (int i=0; i<DEPTH; i++) begin
571 152937 : if (~found_wrptr1) begin
572 152629 : WrPtr1_m[DEPTH_LOG2-1:0] = DEPTH_LOG2'(i);
573 152629 : found_wrptr1 = (buf_state[i] == IDLE) & ~((ibuf_valid & (ibuf_tag == i)) |
574 152629 : (lsu_busreq_m & (WrPtr0_m == i)) |
575 152629 : (lsu_busreq_r & ((WrPtr0_r == i) | (ldst_dual_r & (WrPtr1_r == i)))));
576 : end
577 : end
578 : end
579 :
580 : // Get the command ptr
581 : for (genvar i=0; i<DEPTH; i++) begin
582 : // These should be one-hot
583 : assign CmdPtr0Dec[i] = ~(|buf_age[i]) & (buf_state[i] == CMD) & ~buf_cmd_state_bus_en[i];
584 : assign CmdPtr1Dec[i] = ~(|(buf_age[i] & ~CmdPtr0Dec)) & ~CmdPtr0Dec[i] & (buf_state[i] == CMD) & ~buf_cmd_state_bus_en[i];
585 : assign RspPtrDec[i] = ~(|buf_rsp_pickage[i]) & (buf_state[i] == DONE_WAIT);
586 : end
587 :
588 : assign found_cmdptr0 = |CmdPtr0Dec;
589 : assign found_cmdptr1 = |CmdPtr1Dec;
590 : assign CmdPtr0 = f_Enc8to3(8'(CmdPtr0Dec[DEPTH-1:0]));
591 : assign CmdPtr1 = f_Enc8to3(8'(CmdPtr1Dec[DEPTH-1:0]));
592 : assign RspPtr = f_Enc8to3(8'(RspPtrDec[DEPTH-1:0]));
593 :
594 : // Age vector
595 : for (genvar i=0; i<DEPTH; i++) begin: GenAgeVec
596 : for (genvar j=0; j<DEPTH; j++) begin
597 : assign buf_age_in[i][j] = (((buf_state[i] == IDLE) & buf_state_en[i]) &
598 : (((buf_state[j] == START_WAIT) | ((buf_state[j] == CMD) & ~buf_cmd_state_bus_en[j])) | // Set age bit for older entries
599 : (ibuf_drain_vld & lsu_busreq_r & (ibuf_byp | ldst_dual_r) & (i == WrPtr0_r) & (j == ibuf_tag)) | // Set case for dual lo
600 : (ibuf_byp & lsu_busreq_r & ldst_dual_r & (i == WrPtr1_r) & (j == WrPtr0_r)))) | // ibuf bypass case
601 : buf_age[i][j];
602 :
603 :
604 : assign buf_age[i][j] = buf_ageQ[i][j] & ~((buf_state[j] == CMD) & buf_cmd_state_bus_en[j]) & ~dec_tlu_force_halt; // Reset case
605 :
606 : assign buf_age_younger[i][j] = (i == j) ? 1'b0: (~buf_age[i][j] & (buf_state[j] != IDLE)); // Younger entries
607 : end
608 : end
609 :
610 : // Age vector for responses
611 : for (genvar i=0; i<DEPTH; i++) begin: GenRspAgeVec
612 : for (genvar j=0; j<DEPTH; j++) begin
613 : assign buf_rspage_set[i][j] = ((buf_state[i] == IDLE) & buf_state_en[i]) &
614 : (~((buf_state[j] == IDLE) | (buf_state[j] == DONE)) | // Set age bit for older entries
615 : (ibuf_drain_vld & lsu_busreq_r & (ibuf_byp | ldst_dual_r) & (DEPTH_LOG2'(i) == WrPtr0_r) & (DEPTH_LOG2'(j) == ibuf_tag)) | // Set case for dual lo
616 : (ibuf_byp & lsu_busreq_r & ldst_dual_r & (DEPTH_LOG2'(i) == WrPtr1_r) & (DEPTH_LOG2'(j) == WrPtr0_r)));
617 : assign buf_rspage_in[i][j] = buf_rspage_set[i][j] | buf_rspage[i][j];
618 : assign buf_rspage[i][j] = buf_rspageQ[i][j] & ~((buf_state[j] == DONE) | (buf_state[j] == IDLE)) & ~dec_tlu_force_halt; // Reset case
619 : assign buf_rsp_pickage[i][j] = buf_rspageQ[i][j] & (buf_state[j] == DONE_WAIT);
620 : end
621 : end
622 :
623 : //------------------------------------------------------------------------------
624 : // Buffer logic
625 : //------------------------------------------------------------------------------
626 0 : for (genvar i=0; i<DEPTH; i++) begin : genblock
627 :
628 : assign ibuf_drainvec_vld[i] = (ibuf_drain_vld & (i == ibuf_tag));
629 : assign buf_byteen_in[i] = ibuf_drainvec_vld[i] ? ibuf_byteen_out[3:0] : ((ibuf_byp & ldst_dual_r & (i == WrPtr1_r)) ? ldst_byteen_hi_r[3:0] : ldst_byteen_lo_r[3:0]);
630 : assign buf_addr_in[i] = ibuf_drainvec_vld[i] ? ibuf_addr[31:0] : ((ibuf_byp & ldst_dual_r & (i == WrPtr1_r)) ? end_addr_r[31:0] : lsu_addr_r[31:0]);
631 : assign buf_dual_in[i] = ibuf_drainvec_vld[i] ? ibuf_dual : ldst_dual_r;
632 : assign buf_samedw_in[i] = ibuf_drainvec_vld[i] ? ibuf_samedw : ldst_samedw_r;
633 : assign buf_nomerge_in[i] = ibuf_drainvec_vld[i] ? (ibuf_nomerge | ibuf_force_drain) : no_dword_merge_r;
634 : assign buf_dualhi_in[i] = ibuf_drainvec_vld[i] ? ibuf_dual : (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)); // If it's dual, ibuf will always have the high
635 : assign buf_dualtag_in[i] = ibuf_drainvec_vld[i] ? ibuf_dualtag : ((ibuf_byp & ldst_dual_r & (i == WrPtr1_r)) ? WrPtr0_r : WrPtr1_r);
636 : assign buf_sideeffect_in[i] = ibuf_drainvec_vld[i] ? ibuf_sideeffect : is_sideeffects_r;
637 : assign buf_unsign_in[i] = ibuf_drainvec_vld[i] ? ibuf_unsign : lsu_pkt_r.unsign;
638 : assign buf_sz_in[i] = ibuf_drainvec_vld[i] ? ibuf_sz : {lsu_pkt_r.word, lsu_pkt_r.half};
639 : assign buf_write_in[i] = ibuf_drainvec_vld[i] ? ibuf_write : lsu_pkt_r.store;
640 :
641 : // Buffer entry state machine
642 1268 : always_comb begin
643 1268 : buf_nxtstate[i] = IDLE;
644 1268 : buf_state_en[i] = '0;
645 1268 : buf_resp_state_bus_en[i] = '0;
646 1268 : buf_state_bus_en[i] = '0;
647 1268 : buf_wr_en[i] = '0;
648 1268 : buf_data_in[i] = '0;
649 1268 : buf_data_en[i] = '0;
650 1268 : buf_error_en[i] = '0;
651 1268 : buf_rst[i] = dec_tlu_force_halt;
652 1268 : buf_ldfwd_en[i] = dec_tlu_force_halt;
653 1268 : buf_ldfwd_in[i] = '0;
654 1268 : buf_ldfwdtag_in[i] = '0;
655 :
656 1268 : case (buf_state[i])
657 92666200 : IDLE: begin
658 92666200 : buf_nxtstate[i] = lsu_bus_clk_en ? CMD : START_WAIT;
659 92666200 : buf_state_en[i] = (lsu_busreq_r & lsu_commit_r & (((ibuf_byp | ldst_dual_r) & ~ibuf_merge_en & (i == WrPtr0_r)) | (ibuf_byp & ldst_dual_r & (i == WrPtr1_r)))) |
660 92666200 : (ibuf_drain_vld & (i == ibuf_tag));
661 92666200 : buf_wr_en[i] = buf_state_en[i];
662 92666200 : buf_data_en[i] = buf_state_en[i];
663 92666200 : buf_data_in[i] = (ibuf_drain_vld & (i == ibuf_tag)) ? ibuf_data_out[31:0] : store_data_lo_r[31:0];
664 92666200 : buf_cmd_state_bus_en[i] = '0;
665 : end
666 0 : START_WAIT: begin
667 0 : buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : CMD;
668 0 : buf_state_en[i] = lsu_bus_clk_en | dec_tlu_force_halt;
669 0 : buf_cmd_state_bus_en[i] = '0;
670 : end
671 2423662 : CMD: begin
672 2423662 : buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : (obuf_nosend & bus_rsp_read & (bus_rsp_read_tag == obuf_rdrsp_tag)) ? DONE_WAIT : RESP;
673 2423662 : buf_cmd_state_bus_en[i] = ((obuf_tag0 == i) | (obuf_merge & (obuf_tag1 == i))) & obuf_valid & obuf_wr_enQ; // Just use the recently written obuf_valid
674 2423662 : buf_state_bus_en[i] = buf_cmd_state_bus_en[i];
675 2423662 : buf_state_en[i] = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
676 2423662 : buf_ldfwd_in[i] = 1'b1;
677 2423662 : buf_ldfwd_en[i] = buf_state_en[i] & ~buf_write[i] & obuf_nosend & ~dec_tlu_force_halt;
678 2423662 : buf_ldfwdtag_in[i] = DEPTH_LOG2'(obuf_rdrsp_tag[pt.LSU_BUS_TAG-2:0]);
679 2423662 : buf_data_en[i] = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read;
680 2423662 : buf_error_en[i] = buf_state_bus_en[i] & lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error;
681 2423662 : buf_data_in[i] = buf_error_en[i] ? bus_rsp_rdata[31:0] : (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]);
682 : end
683 1460609 : RESP: begin
684 1460609 : buf_nxtstate[i] = (dec_tlu_force_halt | (buf_write[i] & ~bus_rsp_write_error)) ? IDLE : // Side-effect writes will be non-posted
685 1460609 : (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & (buf_state[buf_dualtag[i]] != DONE_PARTIAL)) ? DONE_PARTIAL : // Goto DONE_PARTIAL if this is the first return of dual
686 1460609 : (buf_ldfwd[i] | any_done_wait_state |
687 1460609 : (buf_dual[i] & ~buf_samedw[i] & ~buf_write[i] & buf_ldfwd[buf_dualtag[i]] &
688 1460609 : (buf_state[buf_dualtag[i]] == DONE_PARTIAL) & any_done_wait_state)) ? DONE_WAIT : DONE;
689 1460609 : buf_resp_state_bus_en[i] = (bus_rsp_write & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))) |
690 1460609 : (bus_rsp_read & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i)) |
691 1460609 : (buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
692 1460609 : (buf_dual[i] & buf_dualhi[i] & ~buf_write[i] & buf_samedw[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])))));
693 1460609 : buf_state_bus_en[i] = buf_resp_state_bus_en[i];
694 1460609 : buf_state_en[i] = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
695 1460609 : buf_data_en[i] = buf_state_bus_en[i] & bus_rsp_read & lsu_bus_clk_en;
696 : // Need to capture the error for stores as well for AXI
697 1460609 : buf_error_en[i] = buf_state_bus_en[i] & lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(i))) |
698 1460609 : (bus_rsp_read_error & buf_ldfwd[i] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[i]))) |
699 1460609 : (bus_rsp_write_error & (bus_rsp_write_tag == (pt.LSU_BUS_TAG)'(i))));
700 1460609 : buf_data_in[i][31:0] = (buf_state_en[i] & ~buf_error_en[i]) ? (buf_addr[i][2] ? bus_rsp_rdata[63:32] : bus_rsp_rdata[31:0]) : bus_rsp_rdata[31:0];
701 1460609 : buf_cmd_state_bus_en[i] = '0;
702 : end
703 8824 : DONE_PARTIAL: begin // Other part of dual load hasn't returned
704 8824 : buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : (buf_ldfwd[i] | buf_ldfwd[buf_dualtag[i]] | any_done_wait_state) ? DONE_WAIT : DONE;
705 8824 : buf_state_bus_en[i] = bus_rsp_read & ((bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_dualtag[i])) |
706 8824 : (buf_ldfwd[buf_dualtag[i]] & (bus_rsp_read_tag == (pt.LSU_BUS_TAG)'(buf_ldfwdtag[buf_dualtag[i]]))));
707 8824 : buf_state_en[i] = (buf_state_bus_en[i] & lsu_bus_clk_en) | dec_tlu_force_halt;
708 8824 : buf_cmd_state_bus_en[i] = '0;
709 : end
710 12005 : DONE_WAIT: begin // START_WAIT state if there are multiple outstanding nb returns
711 12005 : buf_nxtstate[i] = dec_tlu_force_halt ? IDLE : DONE;
712 12005 : buf_state_en[i] = ((RspPtr == DEPTH_LOG2'(i)) | (buf_dual[i] & (buf_dualtag[i] == RspPtr))) | dec_tlu_force_halt;
713 12005 : buf_cmd_state_bus_en[i] = '0;
714 : end
715 481828 : DONE: begin
716 481828 : buf_nxtstate[i] = IDLE;
717 481828 : buf_rst[i] = 1'b1;
718 481828 : buf_state_en[i] = 1'b1;
719 481828 : buf_ldfwd_in[i] = 1'b0;
720 481828 : buf_ldfwd_en[i] = buf_state_en[i];
721 481828 : buf_cmd_state_bus_en[i] = '0;
722 : end
723 0 : default : begin
724 0 : buf_nxtstate[i] = IDLE;
725 0 : buf_state_en[i] = '0;
726 0 : buf_resp_state_bus_en[i] = '0;
727 0 : buf_state_bus_en[i] = '0;
728 0 : buf_wr_en[i] = '0;
729 0 : buf_data_in[i] = '0;
730 0 : buf_data_en[i] = '0;
731 0 : buf_error_en[i] = '0;
732 0 : buf_rst[i] = '0;
733 0 : buf_cmd_state_bus_en[i] = '0;
734 : end
735 : endcase
736 : end
737 :
738 : rvdffs #(.WIDTH($bits(state_t))) buf_state_ff (.din(buf_nxtstate[i]), .dout({buf_state[i]}), .en(buf_state_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
739 : rvdff #(.WIDTH(DEPTH)) buf_ageff (.din(buf_age_in[i]), .dout(buf_ageQ[i]), .clk(lsu_bus_buf_c1_clk), .*);
740 : rvdff #(.WIDTH(DEPTH)) buf_rspageff (.din(buf_rspage_in[i]), .dout(buf_rspageQ[i]), .clk(lsu_bus_buf_c1_clk), .*);
741 : rvdffs #(.WIDTH(DEPTH_LOG2)) buf_dualtagff (.din(buf_dualtag_in[i]), .dout(buf_dualtag[i]), .en(buf_wr_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
742 : rvdffs #(.WIDTH(1)) buf_dualff (.din(buf_dual_in[i]), .dout(buf_dual[i]), .en(buf_wr_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
743 : rvdffs #(.WIDTH(1)) buf_samedwff (.din(buf_samedw_in[i]), .dout(buf_samedw[i]), .en(buf_wr_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
744 : rvdffs #(.WIDTH(1)) buf_nomergeff (.din(buf_nomerge_in[i]), .dout(buf_nomerge[i]), .en(buf_wr_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
745 : rvdffs #(.WIDTH(1)) buf_dualhiff (.din(buf_dualhi_in[i]), .dout(buf_dualhi[i]), .en(buf_wr_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
746 : rvdffs #(.WIDTH(1)) buf_ldfwdff (.din(buf_ldfwd_in[i]), .dout(buf_ldfwd[i]), .en(buf_ldfwd_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
747 : rvdffs #(.WIDTH(DEPTH_LOG2)) buf_ldfwdtagff (.din(buf_ldfwdtag_in[i]), .dout(buf_ldfwdtag[i]), .en(buf_ldfwd_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
748 : rvdffs #(.WIDTH(1)) buf_sideeffectff (.din(buf_sideeffect_in[i]), .dout(buf_sideeffect[i]), .en(buf_wr_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
749 : rvdffs #(.WIDTH(1)) buf_unsignff (.din(buf_unsign_in[i]), .dout(buf_unsign[i]), .en(buf_wr_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
750 : rvdffs #(.WIDTH(1)) buf_writeff (.din(buf_write_in[i]), .dout(buf_write[i]), .en(buf_wr_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
751 : rvdffs #(.WIDTH(2)) buf_szff (.din(buf_sz_in[i]), .dout(buf_sz[i]), .en(buf_wr_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
752 : rvdffe #(.WIDTH(32)) buf_addrff (.din(buf_addr_in[i][31:0]), .dout(buf_addr[i]), .en(buf_wr_en[i]), .*);
753 : rvdffs #(.WIDTH(4)) buf_byteenff (.din(buf_byteen_in[i][3:0]), .dout(buf_byteen[i]), .en(buf_wr_en[i]), .clk(lsu_bus_buf_c1_clk), .*);
754 : rvdffe #(.WIDTH(32)) buf_dataff (.din(buf_data_in[i][31:0]), .dout(buf_data[i]), .en(buf_data_en[i]), .*);
755 : rvdffsc #(.WIDTH(1)) buf_errorff (.din(1'b1), .dout(buf_error[i]), .en(buf_error_en[i]), .clear(buf_rst[i]), .clk(lsu_bus_buf_c1_clk), .*);
756 :
757 : end
758 :
759 : // buffer full logic
760 317 : always_comb begin
761 317 : buf_numvld_any[3:0] = 4'(({1'b0,lsu_busreq_m} << ldst_dual_m) +
762 317 : ({1'b0,lsu_busreq_r} << ldst_dual_r) +
763 317 : ibuf_valid);
764 317 : buf_numvld_wrcmd_any[3:0] = 4'b0;
765 317 : buf_numvld_cmd_any[3:0] = 4'b0;
766 317 : buf_numvld_pend_any[3:0] = 4'b0;
767 317 : any_done_wait_state = 1'b0;
768 317 : for (int i=0; i<DEPTH; i++) begin
769 1268 : buf_numvld_any[3:0] += {3'b0, (buf_state[i] != IDLE)};
770 1268 : buf_numvld_wrcmd_any[3:0] += {3'b0, (buf_write[i] & (buf_state[i] == CMD) & ~buf_cmd_state_bus_en[i])};
771 1268 : buf_numvld_cmd_any[3:0] += {3'b0, ((buf_state[i] == CMD) & ~buf_cmd_state_bus_en[i])};
772 1268 : buf_numvld_pend_any[3:0] += {3'b0, ((buf_state[i] == START_WAIT) | ((buf_state[i] == CMD) & ~buf_cmd_state_bus_en[i]))};
773 1268 : any_done_wait_state |= (buf_state[i] == DONE_WAIT);
774 : end
775 : end
776 :
777 : assign lsu_bus_buffer_pend_any = (buf_numvld_pend_any != 0);
778 : assign lsu_bus_buffer_full_any = (ldst_dual_d & dec_lsu_valid_raw_d) ? (buf_numvld_any[3:0] >= (DEPTH-1)) : (buf_numvld_any[3:0] == DEPTH);
779 : assign lsu_bus_buffer_empty_any = ~(|buf_state[DEPTH-1:0]) & ~ibuf_valid & ~obuf_valid;
780 :
781 :
782 : // Non blocking ports
783 : assign lsu_nonblock_load_valid_m = lsu_busreq_m & lsu_pkt_m.valid & lsu_pkt_m.load & ~flush_m_up & ~ld_full_hit_m;
784 : assign lsu_nonblock_load_tag_m[DEPTH_LOG2-1:0] = WrPtr0_m[DEPTH_LOG2-1:0];
785 : assign lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & ~lsu_commit_r;
786 : assign lsu_nonblock_load_inv_tag_r[DEPTH_LOG2-1:0] = WrPtr0_r[DEPTH_LOG2-1:0]; // r tag needs to be accurate even if there is no invalidate
787 :
788 317 : always_comb begin
789 317 : lsu_nonblock_load_data_ready = '0;
790 317 : lsu_nonblock_load_data_error = '0;
791 317 : lsu_nonblock_load_data_tag[DEPTH_LOG2-1:0] = '0;
792 317 : lsu_nonblock_load_data_lo[31:0] = '0;
793 317 : lsu_nonblock_load_data_hi[31:0] = '0;
794 317 : for (int i=0; i<DEPTH; i++) begin
795 : // Use buf_rst[i] instead of buf_state_en[i] for timing
796 1268 : lsu_nonblock_load_data_ready |= (buf_state[i] == DONE) & ~buf_write[i];
797 1268 : lsu_nonblock_load_data_error |= (buf_state[i] == DONE) & buf_error[i] & ~buf_write[i];
798 1268 : lsu_nonblock_load_data_tag[DEPTH_LOG2-1:0] |= DEPTH_LOG2'(i) & {DEPTH_LOG2{((buf_state[i] == DONE) & ~buf_write[i] & (~buf_dual[i] | ~buf_dualhi[i]))}};
799 1268 : lsu_nonblock_load_data_lo[31:0] |= buf_data[i][31:0] & {32{((buf_state[i] == DONE) & ~buf_write[i] & (~buf_dual[i] | ~buf_dualhi[i]))}};
800 1268 : lsu_nonblock_load_data_hi[31:0] |= buf_data[i][31:0] & {32{((buf_state[i] == DONE) & ~buf_write[i] & (buf_dual[i] & buf_dualhi[i]))}};
801 : end
802 : end
803 :
804 : assign lsu_nonblock_addr_offset[1:0] = buf_addr[lsu_nonblock_load_data_tag][1:0];
805 : assign lsu_nonblock_sz[1:0] = buf_sz[lsu_nonblock_load_data_tag][1:0];
806 : assign lsu_nonblock_unsign = buf_unsign[lsu_nonblock_load_data_tag];
807 : assign lsu_nonblock_data_unalgn[31:0] = 32'({lsu_nonblock_load_data_hi[31:0], lsu_nonblock_load_data_lo[31:0]} >> 8*lsu_nonblock_addr_offset[1:0]);
808 :
809 : assign lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & ~lsu_nonblock_load_data_error;
810 : assign lsu_nonblock_load_data[31:0] = ({32{ lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b00)}} & {24'b0,lsu_nonblock_data_unalgn[7:0]}) |
811 : ({32{ lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b01)}} & {16'b0,lsu_nonblock_data_unalgn[15:0]}) |
812 : ({32{~lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b00)}} & {{24{lsu_nonblock_data_unalgn[7]}}, lsu_nonblock_data_unalgn[7:0]}) |
813 : ({32{~lsu_nonblock_unsign & (lsu_nonblock_sz[1:0] == 2'b01)}} & {{16{lsu_nonblock_data_unalgn[15]}},lsu_nonblock_data_unalgn[15:0]}) |
814 : ({32{(lsu_nonblock_sz[1:0] == 2'b10)}} & lsu_nonblock_data_unalgn[31:0]);
815 :
816 : // Determine if there is a pending return to sideeffect load/store
817 317 : always_comb begin
818 317 : bus_sideeffect_pend = obuf_valid & obuf_sideeffect & dec_tlu_sideeffect_posted_disable;
819 317 : for (int i=0; i<DEPTH; i++) begin
820 1268 : bus_sideeffect_pend |= ((buf_state[i] == RESP) & buf_sideeffect[i] & dec_tlu_sideeffect_posted_disable);
821 : end
822 : end
823 :
824 : // We have no ordering rules for AXI. Need to check outstanding trxns to same address for AXI
825 317 : always_comb begin
826 317 : bus_addr_match_pending = '0;
827 317 : for (int i=0; i<DEPTH; i++) begin
828 1268 : bus_addr_match_pending |= (obuf_valid & (obuf_addr[31:3] == buf_addr[i][31:3]) & (buf_state[i] == RESP) & ~((obuf_tag0 == (pt.LSU_BUS_TAG)'(i)) | (obuf_merge & (obuf_tag1 == (pt.LSU_BUS_TAG)'(i)))));
829 : end
830 : end
831 :
832 : // Generic bus signals
833 : assign bus_cmd_ready = obuf_write ? ((obuf_cmd_done | obuf_data_done) ? (obuf_cmd_done ? lsu_axi_wready : lsu_axi_awready) : (lsu_axi_awready & lsu_axi_wready)) : lsu_axi_arready;
834 : assign bus_wcmd_sent = lsu_axi_awvalid & lsu_axi_awready;
835 : assign bus_wdata_sent = lsu_axi_wvalid & lsu_axi_wready;
836 : assign bus_cmd_sent = ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (lsu_axi_arvalid & lsu_axi_arready);
837 :
838 : assign bus_rsp_read = lsu_axi_rvalid & lsu_axi_rready;
839 : assign bus_rsp_write = lsu_axi_bvalid & lsu_axi_bready;
840 : assign bus_rsp_read_tag[pt.LSU_BUS_TAG-1:0] = lsu_axi_rid[pt.LSU_BUS_TAG-1:0];
841 : assign bus_rsp_write_tag[pt.LSU_BUS_TAG-1:0] = lsu_axi_bid[pt.LSU_BUS_TAG-1:0];
842 : assign bus_rsp_write_error = bus_rsp_write & (lsu_axi_bresp[1:0] != 2'b0);
843 : assign bus_rsp_read_error = bus_rsp_read & (lsu_axi_rresp[1:0] != 2'b0);
844 : assign bus_rsp_rdata[63:0] = lsu_axi_rdata[63:0];
845 :
846 : // AXI command signals
847 : assign lsu_axi_awvalid = obuf_valid & obuf_write & ~obuf_cmd_done & ~bus_addr_match_pending;
848 : assign lsu_axi_awid[pt.LSU_BUS_TAG-1:0] = (pt.LSU_BUS_TAG)'(obuf_tag0);
849 : assign lsu_axi_awaddr[31:0] = obuf_sideeffect ? obuf_addr[31:0] : {obuf_addr[31:3],3'b0};
850 : assign lsu_axi_awsize[2:0] = obuf_sideeffect ? {1'b0, obuf_sz[1:0]} : 3'b011;
851 : assign lsu_axi_awprot[2:0] = 3'b001;
852 : assign lsu_axi_awcache[3:0] = obuf_sideeffect ? 4'b0 : 4'b1111;
853 : assign lsu_axi_awregion[3:0] = obuf_addr[31:28];
854 : assign lsu_axi_awlen[7:0] = '0;
855 : assign lsu_axi_awburst[1:0] = 2'b01;
856 : assign lsu_axi_awqos[3:0] = '0;
857 : assign lsu_axi_awlock = '0;
858 :
859 : assign lsu_axi_wvalid = obuf_valid & obuf_write & ~obuf_data_done & ~bus_addr_match_pending;
860 : assign lsu_axi_wstrb[7:0] = obuf_byteen[7:0] & {8{obuf_write}};
861 : assign lsu_axi_wdata[63:0] = obuf_data[63:0];
862 : assign lsu_axi_wlast = '1;
863 :
864 : assign lsu_axi_arvalid = obuf_valid & ~obuf_write & ~obuf_nosend & ~bus_addr_match_pending;
865 : assign lsu_axi_arid[pt.LSU_BUS_TAG-1:0] = (pt.LSU_BUS_TAG)'(obuf_tag0);
866 : assign lsu_axi_araddr[31:0] = obuf_sideeffect ? obuf_addr[31:0] : {obuf_addr[31:3],3'b0};
867 : assign lsu_axi_arsize[2:0] = obuf_sideeffect ? {1'b0, obuf_sz[1:0]} : 3'b011;
868 : assign lsu_axi_arprot[2:0] = 3'b001;
869 : assign lsu_axi_arcache[3:0] = obuf_sideeffect ? 4'b0 : 4'b1111;
870 : assign lsu_axi_arregion[3:0] = obuf_addr[31:28];
871 : assign lsu_axi_arlen[7:0] = '0;
872 : assign lsu_axi_arburst[1:0] = 2'b01;
873 : assign lsu_axi_arqos[3:0] = '0;
874 : assign lsu_axi_arlock = '0;
875 :
876 : assign lsu_axi_bready = 1;
877 : assign lsu_axi_rready = 1;
878 :
879 317 : always_comb begin
880 317 : lsu_imprecise_error_store_any = '0;
881 317 : lsu_imprecise_error_store_tag = '0;
882 317 : for (int i=0; i<DEPTH; i++) begin
883 1268 : lsu_imprecise_error_store_any |= lsu_bus_clk_en_q & (buf_state[i] == DONE) & buf_error[i] & buf_write[i];
884 1268 : lsu_imprecise_error_store_tag |= DEPTH_LOG2'(i) & {DEPTH_LOG2{((buf_state[i] == DONE) & buf_error[i] & buf_write[i])}};
885 : end
886 : end
887 : assign lsu_imprecise_error_load_any = lsu_nonblock_load_data_error & ~lsu_imprecise_error_store_any; // This is to make sure we send only one imprecise error for load/store
888 : assign lsu_imprecise_error_addr_any[31:0] = lsu_imprecise_error_store_any ? buf_addr[lsu_imprecise_error_store_tag[DEPTH_LOG2-1:0]] : buf_addr[lsu_nonblock_load_data_tag[DEPTH_LOG2-1:0]];
889 :
890 : // PMU signals
891 : assign lsu_pmu_bus_trxn = (lsu_axi_awvalid & lsu_axi_awready) | (lsu_axi_wvalid & lsu_axi_wready) | (lsu_axi_arvalid & lsu_axi_arready);
892 : assign lsu_pmu_bus_misaligned = lsu_busreq_r & ldst_dual_r & lsu_commit_r;
893 : assign lsu_pmu_bus_error = lsu_imprecise_error_load_any | lsu_imprecise_error_store_any;
894 : assign lsu_pmu_bus_busy = (lsu_axi_awvalid & ~lsu_axi_awready) | (lsu_axi_wvalid & ~lsu_axi_wready) | (lsu_axi_arvalid & ~lsu_axi_arready);
895 :
896 : rvdff_fpga #(.WIDTH(1)) lsu_axi_awvalid_ff (.din(lsu_axi_awvalid), .dout(lsu_axi_awvalid_q), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
897 : rvdff_fpga #(.WIDTH(1)) lsu_axi_awready_ff (.din(lsu_axi_awready), .dout(lsu_axi_awready_q), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
898 : rvdff_fpga #(.WIDTH(1)) lsu_axi_wvalid_ff (.din(lsu_axi_wvalid), .dout(lsu_axi_wvalid_q), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
899 : rvdff_fpga #(.WIDTH(1)) lsu_axi_wready_ff (.din(lsu_axi_wready), .dout(lsu_axi_wready_q), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
900 : rvdff_fpga #(.WIDTH(1)) lsu_axi_arvalid_ff (.din(lsu_axi_arvalid), .dout(lsu_axi_arvalid_q), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
901 : rvdff_fpga #(.WIDTH(1)) lsu_axi_arready_ff (.din(lsu_axi_arready), .dout(lsu_axi_arready_q), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
902 :
903 : rvdff_fpga #(.WIDTH(1)) lsu_axi_bvalid_ff (.din(lsu_axi_bvalid), .dout(lsu_axi_bvalid_q), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
904 : rvdff_fpga #(.WIDTH(1)) lsu_axi_bready_ff (.din(lsu_axi_bready), .dout(lsu_axi_bready_q), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
905 : rvdff_fpga #(.WIDTH(2)) lsu_axi_bresp_ff (.din(lsu_axi_bresp[1:0]), .dout(lsu_axi_bresp_q[1:0]), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
906 : rvdff_fpga #(.WIDTH(pt.LSU_BUS_TAG)) lsu_axi_bid_ff (.din(lsu_axi_bid[pt.LSU_BUS_TAG-1:0]),.dout(lsu_axi_bid_q[pt.LSU_BUS_TAG-1:0]),.clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
907 : rvdffe #(.WIDTH(64)) lsu_axi_rdata_ff (.din(lsu_axi_rdata[63:0]), .dout(lsu_axi_rdata_q[63:0]), .en((lsu_axi_rvalid | clk_override) & lsu_bus_clk_en), .*);
908 :
909 : rvdff_fpga #(.WIDTH(1)) lsu_axi_rvalid_ff (.din(lsu_axi_rvalid), .dout(lsu_axi_rvalid_q), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
910 : rvdff_fpga #(.WIDTH(1)) lsu_axi_rready_ff (.din(lsu_axi_rready), .dout(lsu_axi_rready_q), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
911 : rvdff_fpga #(.WIDTH(2)) lsu_axi_rresp_ff (.din(lsu_axi_rresp[1:0]), .dout(lsu_axi_rresp_q[1:0]), .clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
912 : rvdff_fpga #(.WIDTH(pt.LSU_BUS_TAG)) lsu_axi_rid_ff (.din(lsu_axi_rid[pt.LSU_BUS_TAG-1:0]),.dout(lsu_axi_rid_q[pt.LSU_BUS_TAG-1:0]),.clk(lsu_busm_clk), .clken(lsu_busm_clken), .rawclk(clk), .*);
913 :
914 : rvdff #(.WIDTH(DEPTH_LOG2)) lsu_WrPtr0_rff (.din(WrPtr0_m), .dout(WrPtr0_r), .clk(lsu_c2_r_clk), .*);
915 : rvdff #(.WIDTH(DEPTH_LOG2)) lsu_WrPtr1_rff (.din(WrPtr1_m), .dout(WrPtr1_r), .clk(lsu_c2_r_clk), .*);
916 :
917 : rvdff #(.WIDTH(1)) lsu_busreq_rff (.din(lsu_busreq_m & ~flush_r & ~ld_full_hit_m), .dout(lsu_busreq_r), .clk(lsu_c2_r_clk), .*);
918 : rvdff #(.WIDTH(1)) lsu_nonblock_load_valid_rff (.din(lsu_nonblock_load_valid_m), .dout(lsu_nonblock_load_valid_r), .clk(lsu_c2_r_clk), .*);
919 :
920 : `ifdef RV_ASSERT_ON
921 :
922 : for (genvar i=0; i<4; i++) begin: GenByte
923 : assert_ld_byte_hitvecfn_lo_onehot: assert #0 ($onehot0(ld_byte_hitvecfn_lo[i][DEPTH-1:0]));
924 : assert_ld_byte_hitvecfn_hi_onehot: assert #0 ($onehot0(ld_byte_hitvecfn_hi[i][DEPTH-1:0]));
925 : end
926 :
927 : for (genvar i=0; i<DEPTH; i++) begin: GenAssertAge
928 : assert_bufempty_agevec: assert #0 (~(lsu_bus_buffer_empty_any & |(buf_age[i])));
929 : end
930 :
931 : assert_CmdPtr0Dec_onehot: assert #0 ($onehot0(CmdPtr0Dec[DEPTH-1:0] & ~{DEPTH{dec_tlu_force_halt}}));
932 : assert_CmdPtr1Dec_onehot: assert #0 ($onehot0(CmdPtr1Dec[DEPTH-1:0] & ~{DEPTH{dec_tlu_force_halt}}));
933 :
934 : `endif
935 :
936 : endmodule // el2_lsu_bus_buffer
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