Project Full coverage report
Current view: Cores-VeeR-EL2—Cores-VeeR-EL2—design—lsu—el2_lsu_addrcheck.sv Coverage Hit Total
Test Date: 08-11-2024 Toggle 52.0% 26 50
Test: all Branch 0.0% 0 0

            Line data    Source code
       1              : // SPDX-License-Identifier: Apache-2.0
       2              : // Copyright 2020 Western Digital Corporation or its affiliates.
       3              : //
       4              : // Licensed under the Apache License, Version 2.0 (the "License");
       5              : // you may not use this file except in compliance with the License.
       6              : // You may obtain a copy of the License at
       7              : //
       8              : // http://www.apache.org/licenses/LICENSE-2.0
       9              : //
      10              : // Unless required by applicable law or agreed to in writing, software
      11              : // distributed under the License is distributed on an "AS IS" BASIS,
      12              : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      13              : // See the License for the specific language governing permissions and
      14              : // limitations under the License.
      15              : 
      16              : //********************************************************************************
      17              : // $Id$
      18              : //
      19              : //
      20              : // Owner:
      21              : // Function: Checks the memory map for the address
      22              : // Comments:
      23              : //
      24              : //********************************************************************************
      25              : module el2_lsu_addrcheck
      26              : import el2_pkg::*;
      27              : #(
      28              : `include "el2_param.vh"
      29              :  )(
      30     69890155 :    input logic          lsu_c2_m_clk,              // clock
      31          338 :    input logic          rst_l,                     // reset
      32              : 
      33       593665 :    input logic [31:0]   start_addr_d,              // start address for lsu
      34       593691 :    input logic [31:0]   end_addr_d,                // end address for lsu
      35       478398 :    input el2_lsu_pkt_t lsu_pkt_d,                 // packet in d
      36            0 :    input logic [31:0]   dec_tlu_mrac_ff,           // CSR read
      37      1447612 :    input logic [3:0]    rs1_region_d,              // address rs operand [31:28]
      38              : 
      39       475836 :    input logic [31:0]   rs1_d,                     // address rs operand
      40              : 
      41        37044 :    output logic         is_sideeffects_m,          // is sideffects space
      42       614422 :    output logic         addr_in_dccm_d,            // address in dccm
      43           12 :    output logic         addr_in_pic_d,             // address in pic
      44       614789 :    output logic         addr_external_d,           // address in external
      45              : 
      46           70 :    output logic         access_fault_d,            // access fault
      47           10 :    output logic         misaligned_fault_d,        // misaligned
      48            0 :    output logic [3:0]   exc_mscause_d,             // mscause for access/misaligned faults
      49              : 
      50            0 :    output logic         fir_dccm_access_error_d,   // Fast interrupt dccm access error
      51            0 :    output logic         fir_nondccm_access_error_d,// Fast interrupt dccm access error
      52              : 
      53       167064 :     input logic lsu_pmp_error_start,
      54       167064 :     input logic lsu_pmp_error_end,
      55              : 
      56            0 :    input  logic         scan_mode                  // Scan mode
      57              : );
      58              : 
      59              : 
      60            0 :    logic        non_dccm_access_ok;
      61        56839 :    logic        is_sideeffects_d, is_aligned_d;
      62       614422 :    logic        start_addr_in_dccm_d, end_addr_in_dccm_d;
      63       614450 :    logic        start_addr_in_dccm_region_d, end_addr_in_dccm_region_d;
      64           12 :    logic        start_addr_in_pic_d, end_addr_in_pic_d;
      65       614450 :    logic        start_addr_in_pic_region_d, end_addr_in_pic_region_d;
      66       824039 :    logic [4:0]  csr_idx;
      67         5862 :    logic        addr_in_iccm;
      68       614450 :    logic        start_addr_dccm_or_pic;
      69       614442 :    logic        base_reg_dccm_or_pic;
      70            8 :    logic        unmapped_access_fault_d, mpu_access_fault_d, picm_access_fault_d, regpred_access_fault_d;
      71           10 :    logic        regcross_misaligned_fault_d, sideeffect_misaligned_fault_d;
      72            0 :    logic [3:0]  access_fault_mscause_d;
      73            0 :    logic [3:0]  misaligned_fault_mscause_d;
      74              : 
      75              :    if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable
      76              :       // Start address check
      77              :       rvrangecheck #(.CCM_SADR(pt.DCCM_SADR),
      78              :                      .CCM_SIZE(pt.DCCM_SIZE)) start_addr_dccm_rangecheck (
      79              :          .addr(start_addr_d[31:0]),
      80              :          .in_range(start_addr_in_dccm_d),
      81              :          .in_region(start_addr_in_dccm_region_d)
      82              :       );
      83              : 
      84              :       // End address check
      85              :       rvrangecheck #(.CCM_SADR(pt.DCCM_SADR),
      86              :                      .CCM_SIZE(pt.DCCM_SIZE)) end_addr_dccm_rangecheck (
      87              :          .addr(end_addr_d[31:0]),
      88              :          .in_range(end_addr_in_dccm_d),
      89              :          .in_region(end_addr_in_dccm_region_d)
      90              :       );
      91              :    end else begin: Gen_dccm_disable // block: Gen_dccm_enable
      92              :       assign start_addr_in_dccm_d = '0;
      93              :       assign start_addr_in_dccm_region_d = '0;
      94              :       assign end_addr_in_dccm_d = '0;
      95              :       assign end_addr_in_dccm_region_d = '0;
      96              :    end
      97              : 
      98              :    if (pt.ICCM_ENABLE == 1) begin : check_iccm
      99              :       assign addr_in_iccm =  (start_addr_d[31:28] == pt.ICCM_REGION);
     100              :    end else begin
     101              :      assign addr_in_iccm = 1'b0;
     102              :    end
     103              : 
     104              :    // PIC memory check
     105              :    // Start address check
     106              :    rvrangecheck #(.CCM_SADR(pt.PIC_BASE_ADDR),
     107              :                   .CCM_SIZE(pt.PIC_SIZE)) start_addr_pic_rangecheck (
     108              :       .addr(start_addr_d[31:0]),
     109              :       .in_range(start_addr_in_pic_d),
     110              :       .in_region(start_addr_in_pic_region_d)
     111              :    );
     112              : 
     113              :    // End address check
     114              :    rvrangecheck #(.CCM_SADR(pt.PIC_BASE_ADDR),
     115              :                   .CCM_SIZE(pt.PIC_SIZE)) end_addr_pic_rangecheck (
     116              :       .addr(end_addr_d[31:0]),
     117              :       .in_range(end_addr_in_pic_d),
     118              :       .in_region(end_addr_in_pic_region_d)
     119              :    );
     120              : 
     121              :    assign start_addr_dccm_or_pic  = start_addr_in_dccm_region_d | start_addr_in_pic_region_d;
     122              :    assign base_reg_dccm_or_pic    = (|((rs1_region_d[3:0] == pt.DCCM_REGION) & pt.DCCM_ENABLE)) | (rs1_region_d[3:0] == pt.PIC_REGION);
     123              :    assign addr_in_dccm_d          = (start_addr_in_dccm_d & end_addr_in_dccm_d);
     124              :    assign addr_in_pic_d           = (start_addr_in_pic_d & end_addr_in_pic_d);
     125              : 
     126              :    assign addr_external_d   = ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d);
     127              :    assign csr_idx[4:0]       = {start_addr_d[31:28], 1'b1};
     128              :    assign is_sideeffects_d = dec_tlu_mrac_ff[csr_idx] & ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & lsu_pkt_d.valid & (lsu_pkt_d.store | lsu_pkt_d.load);  //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
     129              :    assign is_aligned_d    = (lsu_pkt_d.word & (start_addr_d[1:0] == 2'b0)) |
     130              :                                                             (lsu_pkt_d.half & (start_addr_d[0] == 1'b0)) |
     131              :                                                             lsu_pkt_d.by;
     132              : 
     133            0 :    logic ACCESS0_STARTOK;
     134            0 :    logic ACCESS1_STARTOK;
     135            0 :    logic ACCESS2_STARTOK;
     136            0 :    logic ACCESS3_STARTOK;
     137            0 :    logic ACCESS4_STARTOK;
     138            0 :    logic ACCESS5_STARTOK;
     139            0 :    logic ACCESS6_STARTOK;
     140            0 :    logic ACCESS7_STARTOK;
     141            0 :    logic ACCESS0_ENDOK;
     142            0 :    logic ACCESS1_ENDOK;
     143            0 :    logic ACCESS2_ENDOK;
     144            0 :    logic ACCESS3_ENDOK;
     145            0 :    logic ACCESS4_ENDOK;
     146            0 :    logic ACCESS5_ENDOK;
     147            0 :    logic ACCESS6_ENDOK;
     148            0 :    logic ACCESS7_ENDOK;
     149              : 
     150              :    assign ACCESS0_STARTOK = pt.DATA_ACCESS_ENABLE0 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK0)) == (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0);
     151              :    assign ACCESS1_STARTOK = pt.DATA_ACCESS_ENABLE1 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK1)) == (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1);
     152              :    assign ACCESS2_STARTOK = pt.DATA_ACCESS_ENABLE2 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK2)) == (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2);
     153              :    assign ACCESS3_STARTOK = pt.DATA_ACCESS_ENABLE3 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK3)) == (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3);
     154              :    assign ACCESS4_STARTOK = pt.DATA_ACCESS_ENABLE4 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK4)) == (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4);
     155              :    assign ACCESS5_STARTOK = pt.DATA_ACCESS_ENABLE5 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK5)) == (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5);
     156              :    assign ACCESS6_STARTOK = pt.DATA_ACCESS_ENABLE6 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK6)) == (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6);
     157              :    assign ACCESS7_STARTOK = pt.DATA_ACCESS_ENABLE7 & ((start_addr_d[31:0] | pt.DATA_ACCESS_MASK7)) == (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7);
     158              :    assign ACCESS0_ENDOK   = pt.DATA_ACCESS_ENABLE0 & ((end_addr_d[31:0]   | pt.DATA_ACCESS_MASK0)) == (pt.DATA_ACCESS_ADDR0 | pt.DATA_ACCESS_MASK0);
     159              :    assign ACCESS1_ENDOK   = pt.DATA_ACCESS_ENABLE1 & ((end_addr_d[31:0]   | pt.DATA_ACCESS_MASK1)) == (pt.DATA_ACCESS_ADDR1 | pt.DATA_ACCESS_MASK1);
     160              :    assign ACCESS2_ENDOK   = pt.DATA_ACCESS_ENABLE2 & ((end_addr_d[31:0]   | pt.DATA_ACCESS_MASK2)) == (pt.DATA_ACCESS_ADDR2 | pt.DATA_ACCESS_MASK2);
     161              :    assign ACCESS3_ENDOK   = pt.DATA_ACCESS_ENABLE3 & ((end_addr_d[31:0]   | pt.DATA_ACCESS_MASK3)) == (pt.DATA_ACCESS_ADDR3 | pt.DATA_ACCESS_MASK3);
     162              :    assign ACCESS4_ENDOK   = pt.DATA_ACCESS_ENABLE4 & ((end_addr_d[31:0]   | pt.DATA_ACCESS_MASK4)) == (pt.DATA_ACCESS_ADDR4 | pt.DATA_ACCESS_MASK4);
     163              :    assign ACCESS5_ENDOK   = pt.DATA_ACCESS_ENABLE5 & ((end_addr_d[31:0]   | pt.DATA_ACCESS_MASK5)) == (pt.DATA_ACCESS_ADDR5 | pt.DATA_ACCESS_MASK5);
     164              :    assign ACCESS6_ENDOK   = pt.DATA_ACCESS_ENABLE6 & ((end_addr_d[31:0]   | pt.DATA_ACCESS_MASK6)) == (pt.DATA_ACCESS_ADDR6 | pt.DATA_ACCESS_MASK6);
     165              :    assign ACCESS7_ENDOK   = pt.DATA_ACCESS_ENABLE7 & ((end_addr_d[31:0]   | pt.DATA_ACCESS_MASK7)) == (pt.DATA_ACCESS_ADDR7 | pt.DATA_ACCESS_MASK7);
     166              : 
     167              :   if (pt.PMP_ENTRIES == 0) begin
     168              :    assign non_dccm_access_ok = (~(|{pt.DATA_ACCESS_ENABLE0,pt.DATA_ACCESS_ENABLE1,pt.DATA_ACCESS_ENABLE2,pt.DATA_ACCESS_ENABLE3,pt.DATA_ACCESS_ENABLE4,pt.DATA_ACCESS_ENABLE5,pt.DATA_ACCESS_ENABLE6,pt.DATA_ACCESS_ENABLE7})) |
     169              :                                (( ACCESS0_STARTOK|
     170              :                                   ACCESS1_STARTOK|
     171              :                                   ACCESS2_STARTOK|
     172              :                                   ACCESS3_STARTOK|
     173              :                                   ACCESS4_STARTOK|
     174              :                                   ACCESS5_STARTOK|
     175              :                                   ACCESS6_STARTOK|
     176              :                                  ACCESS7_STARTOK)   &
     177              :                                 ( ACCESS0_ENDOK|
     178              :                                   ACCESS1_ENDOK|
     179              :                                   ACCESS2_ENDOK|
     180              :                                   ACCESS3_ENDOK|
     181              :                                   ACCESS4_ENDOK|
     182              :                                   ACCESS5_ENDOK|
     183              :                                   ACCESS6_ENDOK|
     184              :                                  ACCESS7_ENDOK));
     185              :   end
     186              : 
     187              :    // Access fault logic
     188              :    // 0. Unmapped local memory : Addr in dccm region but not in dccm offset OR Addr in picm region but not in picm offset OR DCCM -> PIC cross when DCCM/PIC in same region
     189              :    // 1. Uncorrectable (double bit) ECC error
     190              :    // 3. Address is not in a populated non-dccm region
     191              :    // 5. Region predication access fault: Base Address in DCCM/PIC and Final address in non-DCCM/non-PIC region or vice versa
     192              :    // 6. Ld/St access to picm are not word aligned or word size
     193              :    assign regpred_access_fault_d  = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic);                   // 5. Region predication access fault: Base Address in DCCM/PIC and Final address in non-DCCM/non-PIC region or vice versa
     194              :    assign picm_access_fault_d     = (addr_in_pic_d & ((start_addr_d[1:0] != 2'b0) | ~lsu_pkt_d.word));                                               // 6. Ld/St access to picm are not word aligned or word size
     195              : 
     196              :    if (pt.DCCM_ENABLE & (pt.DCCM_REGION == pt.PIC_REGION)) begin
     197              :       assign unmapped_access_fault_d = ((start_addr_in_dccm_region_d & ~(start_addr_in_dccm_d | start_addr_in_pic_d)) |   // 0. Addr in dccm/pic region but not in dccm/pic offset
     198              :                                         (end_addr_in_dccm_region_d & ~(end_addr_in_dccm_d | end_addr_in_pic_d))       |   // 0. Addr in dccm/pic region but not in dccm/pic offset
     199              :                                         (start_addr_in_dccm_d & end_addr_in_pic_d)                                    |   // 0. DCCM -> PIC cross when DCCM/PIC in same region
     200              :                                         (start_addr_in_pic_d  & end_addr_in_dccm_d));                                     // 0. DCCM -> PIC cross when DCCM/PIC in same region
     201              :     if (pt.PMP_ENTRIES > 0) begin
     202              :       assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                         // X. Address is in blocked region
     203              :     end else begin
     204              :       assign mpu_access_fault_d   = (~start_addr_in_dccm_region_d & ~non_dccm_access_ok);                              // 3. Address is not in a populated non-dccm region
     205              :     end
     206              :    end else begin
     207              :       assign unmapped_access_fault_d = ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d)                              |   // 0. Addr in dccm region but not in dccm offset
     208              :                                         (end_addr_in_dccm_region_d & ~end_addr_in_dccm_d)                                  |   // 0. Addr in dccm region but not in dccm offset
     209              :                                         (start_addr_in_pic_region_d & ~start_addr_in_pic_d)                                |   // 0. Addr in picm region but not in picm offset
     210              :                                         (end_addr_in_pic_region_d & ~end_addr_in_pic_d));                                      // 0. Addr in picm region but not in picm offset
     211              :     if (pt.PMP_ENTRIES > 0) begin
     212              :       assign mpu_access_fault_d   = (lsu_pmp_error_start | lsu_pmp_error_end);                                              // X. Address is in blocked region
     213              :     end else begin
     214              :       assign mpu_access_fault_d   = (~start_addr_in_pic_region_d & ~start_addr_in_dccm_region_d & ~non_dccm_access_ok);     // 3. Address is not in a populated non-dccm region
     215              :     end
     216              :    end
     217              : 
     218              :    assign access_fault_d = (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & lsu_pkt_d.valid & ~lsu_pkt_d.dma;
     219              :    assign access_fault_mscause_d[3:0] = unmapped_access_fault_d ? 4'h2 : mpu_access_fault_d ? 4'h3 : regpred_access_fault_d ? 4'h5 : picm_access_fault_d ? 4'h6 : 4'h0;
     220              : 
     221              :    // Misaligned happens due to 2 reasons
     222              :    // 0. Region cross
     223              :    // 1. sideeffects access which are not aligned
     224              :    assign regcross_misaligned_fault_d = (start_addr_d[31:28] != end_addr_d[31:28]);
     225              :    assign sideeffect_misaligned_fault_d = (is_sideeffects_d & ~is_aligned_d);
     226              :    assign misaligned_fault_d = (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & addr_external_d)) & lsu_pkt_d.valid & ~lsu_pkt_d.dma;
     227              :    assign misaligned_fault_mscause_d[3:0] = regcross_misaligned_fault_d ? 4'h2 : sideeffect_misaligned_fault_d ? 4'h1 : 4'h0;
     228              : 
     229              :    assign exc_mscause_d[3:0] = misaligned_fault_d ? misaligned_fault_mscause_d[3:0] : access_fault_mscause_d[3:0];
     230              : 
     231              :    // Fast interrupt error logic
     232              :    assign fir_dccm_access_error_d    = ((start_addr_in_dccm_region_d & ~start_addr_in_dccm_d) |
     233              :                                                                                 (end_addr_in_dccm_region_d   & ~end_addr_in_dccm_d)) & lsu_pkt_d.valid & lsu_pkt_d.fast_int;
     234              :    assign fir_nondccm_access_error_d = ~(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & lsu_pkt_d.valid & lsu_pkt_d.fast_int;
     235              : 
     236              :    rvdff #(.WIDTH(1))   is_sideeffects_mff (.din(is_sideeffects_d), .dout(is_sideeffects_m), .clk(lsu_c2_m_clk), .*);
     237              : 
     238              : endmodule // el2_lsu_addrcheck