Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 : //********************************************************************************
17 : // $Id$
18 : //
19 : //
20 : // Function: Top level file for load store unit
21 : // Comments:
22 : //
23 : //
24 : // DC1 -> DC2 -> DC3 -> DC4 (Commit)
25 : //
26 : //********************************************************************************
27 :
28 : module el2_lsu
29 : import el2_pkg::*;
30 : #(
31 : `include "el2_param.vh"
32 : )
33 : (
34 :
35 0 : input logic clk_override, // Override non-functional clock gating
36 58638 : input logic dec_tlu_flush_lower_r, // I0/I1 writeback flush. This is used to flush the old packets only
37 29654 : input logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state
38 0 : input logic dec_tlu_force_halt, // This will be high till TLU goes to debug halt
39 :
40 : // chicken signals
41 0 : input logic dec_tlu_external_ldfwd_disable, // disable load to load forwarding for externals
42 4 : input logic dec_tlu_wb_coalescing_disable, // disable the write buffer coalesce
43 301 : input logic dec_tlu_sideeffect_posted_disable, // disable the posted sideeffect load store to the bus
44 8 : input logic dec_tlu_core_ecc_disable, // disable the generation of the ecc
45 :
46 413833 : input logic [31:0] exu_lsu_rs1_d, // address rs operand
47 81386 : input logic [31:0] exu_lsu_rs2_d, // store data
48 270518 : input logic [11:0] dec_lsu_offset_d, // address offset operand
49 :
50 623945 : input el2_lsu_pkt_t lsu_p, // lsu control packet
51 2276073 : input logic dec_lsu_valid_raw_d, // Raw valid for address computation
52 0 : input logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control
53 :
54 38395 : output logic [31:0] lsu_result_m, // lsu load data
55 29134 : output logic [31:0] lsu_result_corr_r, // This is the ECC corrected data going to RF
56 49050 : output logic lsu_load_stall_any, // This is for blocking loads in the decode
57 59374 : output logic lsu_store_stall_any, // This is for blocking stores in the decode
58 4 : output logic lsu_fastint_stall_any, // Stall the fastint in decode-1 stage
59 1346967 : output logic lsu_idle_any, // lsu buffers are empty and no instruction in the pipeline. Doesn't include DMA
60 1346650 : output logic lsu_active, // Used to turn off top level clk
61 :
62 24694 : output logic [31:1] lsu_fir_addr, // fast interrupt address
63 0 : output logic [1:0] lsu_fir_error, // Error during fast interrupt lookup
64 :
65 4 : output logic lsu_single_ecc_error_incr, // Increment the ecc counter
66 4 : output el2_lsu_error_pkt_t lsu_error_pkt_r, // lsu exception packet
67 0 : output logic lsu_imprecise_error_load_any, // bus load imprecise error
68 0 : output logic lsu_imprecise_error_store_any, // bus store imprecise error
69 401 : output logic [31:0] lsu_imprecise_error_addr_any, // bus store imprecise error address
70 :
71 : // Non-blocking loads
72 881640 : output logic lsu_nonblock_load_valid_m, // there is an external load -> put in the cam
73 504869 : output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // the tag of the external non block load
74 0 : output logic lsu_nonblock_load_inv_r, // invalidate signal for the cam entry for non block loads
75 504866 : output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // tag of the enrty which needs to be invalidated
76 920896 : output logic lsu_nonblock_load_data_valid, // the non block is valid - sending information back to the cam
77 0 : output logic lsu_nonblock_load_data_error, // non block load has an error
78 36662 : output logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // the tag of the non block load sending the data/error
79 71560 : output logic [31:0] lsu_nonblock_load_data, // Data of the non block load
80 :
81 891764 : output logic lsu_pmu_load_external_m, // PMU : Bus loads
82 806110 : output logic lsu_pmu_store_external_m, // PMU : Bus loads
83 48786 : output logic lsu_pmu_misaligned_m, // PMU : misaligned
84 1667379 : output logic lsu_pmu_bus_trxn, // PMU : bus transaction
85 36420 : output logic lsu_pmu_bus_misaligned, // PMU : misaligned access going to the bus
86 0 : output logic lsu_pmu_bus_error, // PMU : bus sending error back
87 67818 : output logic lsu_pmu_bus_busy, // PMU : bus is not ready
88 :
89 : // Trigger signals
90 0 : input el2_trigger_pkt_t [3:0] trigger_pkt_any, // Trigger info from the decode
91 0 : output logic [3:0] lsu_trigger_match_m, // lsu trigger hit (one bit per trigger)
92 :
93 : // DCCM ports
94 262892 : output logic dccm_wren, // DCCM write enable
95 561000 : output logic dccm_rden, // DCCM read enable
96 18811 : output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo, // DCCM write address low bank
97 18811 : output logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi, // DCCM write address hi bank
98 471780 : output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo, // DCCM read address low bank
99 678187 : output logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, // DCCM read address hi bank (hi and low same if aligned read)
100 5374 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // DCCM write data for lo bank
101 5374 : output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // DCCM write data for hi bank
102 :
103 47172 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // DCCM read data low bank
104 47172 : input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // DCCM read data hi bank
105 :
106 : // PIC ports
107 0 : output logic picm_wren, // PIC memory write enable
108 0 : output logic picm_rden, // PIC memory read enable
109 0 : output logic picm_mken, // Need to read the mask for stores to determine which bits to write/forward
110 430 : output logic [31:0] picm_rdaddr, // address for pic read access
111 430 : output logic [31:0] picm_wraddr, // address for pic write access
112 92644 : output logic [31:0] picm_wr_data, // PIC memory write data
113 0 : input logic [31:0] picm_rd_data, // PIC memory read/mask data
114 :
115 : // AXI Write Channels
116 855209 : output logic lsu_axi_awvalid,
117 1107817 : input logic lsu_axi_awready,
118 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_awid,
119 401 : output logic [31:0] lsu_axi_awaddr,
120 314 : output logic [3:0] lsu_axi_awregion,
121 0 : output logic [7:0] lsu_axi_awlen,
122 0 : output logic [2:0] lsu_axi_awsize,
123 0 : output logic [1:0] lsu_axi_awburst,
124 0 : output logic lsu_axi_awlock,
125 2985 : output logic [3:0] lsu_axi_awcache,
126 0 : output logic [2:0] lsu_axi_awprot,
127 0 : output logic [3:0] lsu_axi_awqos,
128 :
129 855209 : output logic lsu_axi_wvalid,
130 1107817 : input logic lsu_axi_wready,
131 31411 : output logic [63:0] lsu_axi_wdata,
132 224989 : output logic [7:0] lsu_axi_wstrb,
133 317 : output logic lsu_axi_wlast,
134 :
135 868520 : input logic lsu_axi_bvalid,
136 317 : output logic lsu_axi_bready,
137 0 : input logic [1:0] lsu_axi_bresp,
138 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_bid,
139 :
140 : // AXI Read Channels
141 868958 : output logic lsu_axi_arvalid,
142 1115481 : input logic lsu_axi_arready,
143 0 : output logic [pt.LSU_BUS_TAG-1:0] lsu_axi_arid,
144 401 : output logic [31:0] lsu_axi_araddr,
145 314 : output logic [3:0] lsu_axi_arregion,
146 0 : output logic [7:0] lsu_axi_arlen,
147 0 : output logic [2:0] lsu_axi_arsize,
148 0 : output logic [1:0] lsu_axi_arburst,
149 0 : output logic lsu_axi_arlock,
150 2985 : output logic [3:0] lsu_axi_arcache,
151 0 : output logic [2:0] lsu_axi_arprot,
152 0 : output logic [3:0] lsu_axi_arqos,
153 :
154 929722 : input logic lsu_axi_rvalid,
155 317 : output logic lsu_axi_rready,
156 0 : input logic [pt.LSU_BUS_TAG-1:0] lsu_axi_rid,
157 28838 : input logic [63:0] lsu_axi_rdata,
158 0 : input logic [1:0] lsu_axi_rresp,
159 672602 : input logic lsu_axi_rlast,
160 :
161 316 : input logic lsu_bus_clk_en, // external drives a clock_en to control bus ratio
162 :
163 : // DMA slave
164 0 : input logic dma_dccm_req, // DMA read/write to dccm
165 12 : input logic [2:0] dma_mem_tag, // DMA request tag
166 0 : input logic [31:0] dma_mem_addr, // DMA address
167 0 : input logic [2:0] dma_mem_sz, // DMA access size
168 18 : input logic dma_mem_write, // DMA access is a write
169 12 : input logic [63:0] dma_mem_wdata, // DMA write data
170 :
171 0 : output logic dccm_dma_rvalid, // lsu data valid for DMA dccm read
172 4 : output logic dccm_dma_ecc_error, // DMA load had ecc error
173 12 : output logic [2:0] dccm_dma_rtag, // DMA request tag
174 39560 : output logic [63:0] dccm_dma_rdata, // lsu data for DMA dccm read
175 2225276 : output logic dccm_ready, // lsu ready for DMA access
176 :
177 : // DCCM ECC status
178 4 : output logic lsu_dccm_rd_ecc_single_err,
179 4 : output logic lsu_dccm_rd_ecc_double_err,
180 :
181 0 : input logic scan_mode, // scan mode
182 61843746 : input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
183 61843746 : input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
184 316 : input logic rst_l, // reset, active low
185 :
186 594111 : output logic [31:0] lsu_pmp_addr_start,
187 594149 : output logic [31:0] lsu_pmp_addr_end,
188 167732 : input logic lsu_pmp_error_start,
189 167732 : input logic lsu_pmp_error_end,
190 1065445 : output logic lsu_pmp_we,
191 1424320 : output logic lsu_pmp_re
192 :
193 : );
194 :
195 561000 : logic lsu_dccm_rden_m;
196 561000 : logic lsu_dccm_rden_r;
197 81386 : logic [31:0] store_data_m;
198 56474 : logic [31:0] store_data_r;
199 91102 : logic [31:0] store_data_hi_r, store_data_lo_r;
200 62394 : logic [31:0] store_datafn_hi_r, store_datafn_lo_r;
201 47172 : logic [31:0] sec_data_lo_m, sec_data_hi_m;
202 2 : logic [31:0] sec_data_lo_r, sec_data_hi_r;
203 :
204 54452 : logic [31:0] lsu_ld_data_m;
205 47172 : logic [31:0] dccm_rdata_hi_m, dccm_rdata_lo_m;
206 154095 : logic [6:0] dccm_data_ecc_hi_m, dccm_data_ecc_lo_m;
207 4 : logic lsu_single_ecc_error_m;
208 4 : logic lsu_double_ecc_error_m;
209 :
210 0 : logic [31:0] lsu_ld_data_r;
211 24694 : logic [31:0] lsu_ld_data_corr_r;
212 0 : logic [31:0] dccm_rdata_hi_r, dccm_rdata_lo_r;
213 0 : logic [6:0] dccm_data_ecc_hi_r, dccm_data_ecc_lo_r;
214 4 : logic single_ecc_error_hi_r, single_ecc_error_lo_r;
215 4 : logic lsu_single_ecc_error_r;
216 4 : logic lsu_double_ecc_error_r;
217 4 : logic ld_single_ecc_error_r, ld_single_ecc_error_r_ff;
218 : assign lsu_dccm_rd_ecc_single_err = lsu_single_ecc_error_r;
219 : assign lsu_dccm_rd_ecc_double_err = lsu_double_ecc_error_r;
220 :
221 0 : logic [31:0] picm_mask_data_m;
222 :
223 594109 : logic [31:0] lsu_addr_d, lsu_addr_m, lsu_addr_r;
224 594509 : logic [31:0] end_addr_d, end_addr_m, end_addr_r;
225 : assign lsu_pmp_addr_start = lsu_addr_d;
226 : assign lsu_pmp_addr_end = end_addr_d;
227 :
228 478181 : el2_lsu_pkt_t lsu_pkt_d, lsu_pkt_m, lsu_pkt_r;
229 0 : logic lsu_i0_valid_d, lsu_i0_valid_m, lsu_i0_valid_r;
230 : assign lsu_pmp_we = lsu_pkt_d.store & lsu_pkt_d.valid;
231 : assign lsu_pmp_re = lsu_pkt_d.load & lsu_pkt_d.valid;
232 :
233 : // Store Buffer signals
234 258930 : logic store_stbuf_reqvld_r;
235 258930 : logic ldst_stbuf_reqvld_r;
236 :
237 2279496 : logic lsu_commit_r;
238 60 : logic lsu_exc_m;
239 :
240 614420 : logic addr_in_dccm_d, addr_in_dccm_m, addr_in_dccm_r;
241 0 : logic addr_in_pic_d, addr_in_pic_m, addr_in_pic_r;
242 36568 : logic ldst_dual_d, ldst_dual_m, ldst_dual_r;
243 614746 : logic addr_external_m;
244 :
245 258446 : logic stbuf_reqvld_any;
246 0 : logic stbuf_reqvld_flushed_any;
247 18811 : logic [pt.LSU_SB_BITS-1:0] stbuf_addr_any;
248 7574 : logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_data_any;
249 50849 : logic [pt.DCCM_ECC_WIDTH-1:0] stbuf_ecc_any;
250 2 : logic [pt.DCCM_DATA_WIDTH-1:0] sec_data_lo_r_ff, sec_data_hi_r_ff;
251 50849 : logic [pt.DCCM_ECC_WIDTH-1:0] sec_data_ecc_hi_r_ff, sec_data_ecc_lo_r_ff;
252 :
253 614428 : logic lsu_cmpen_m;
254 5218 : logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_hi_m;
255 4892 : logic [pt.DCCM_DATA_WIDTH-1:0] stbuf_fwddata_lo_m;
256 4198 : logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_hi_m;
257 4202 : logic [pt.DCCM_BYTE_WIDTH-1:0] stbuf_fwdbyteen_lo_m;
258 :
259 262888 : logic lsu_stbuf_commit_any;
260 258763 : logic lsu_stbuf_empty_any; // This is for blocking loads
261 10324 : logic lsu_stbuf_full_any;
262 :
263 : // Bus signals
264 1659482 : logic lsu_busreq_r;
265 808157 : logic lsu_bus_buffer_pend_any;
266 1187701 : logic lsu_bus_buffer_empty_any;
267 49046 : logic lsu_bus_buffer_full_any;
268 1669696 : logic lsu_busreq_m;
269 200 : logic [31:0] bus_read_data_m;
270 :
271 29654 : logic flush_m_up, flush_r;
272 29240 : logic is_sideeffects_m;
273 12 : logic [2:0] dma_mem_tag_d, dma_mem_tag_m;
274 258930 : logic ldst_nodma_mtor;
275 0 : logic dma_dccm_wen, dma_pic_wen;
276 0 : logic [31:0] dma_dccm_wdata_lo, dma_dccm_wdata_hi;
277 0 : logic [pt.DCCM_ECC_WIDTH-1:0] dma_dccm_wdata_ecc_lo, dma_dccm_wdata_ecc_hi;
278 :
279 : // Clocks
280 1088274 : logic lsu_busm_clken;
281 2035983 : logic lsu_bus_obuf_c1_clken;
282 61843746 : logic lsu_c1_m_clk, lsu_c1_r_clk;
283 61843746 : logic lsu_c2_m_clk, lsu_c2_r_clk;
284 61843746 : logic lsu_store_c1_m_clk, lsu_store_c1_r_clk;
285 :
286 61843746 : logic lsu_stbuf_c1_clk;
287 61843746 : logic lsu_bus_ibuf_c1_clk, lsu_bus_obuf_c1_clk, lsu_bus_buf_c1_clk;
288 0 : logic lsu_busm_clk;
289 61843746 : logic lsu_free_c2_clk;
290 :
291 18834 : logic lsu_raw_fwd_lo_m, lsu_raw_fwd_hi_m;
292 18768 : logic lsu_raw_fwd_lo_r, lsu_raw_fwd_hi_r;
293 :
294 : assign lsu_raw_fwd_lo_m = (|stbuf_fwdbyteen_lo_m[pt.DCCM_BYTE_WIDTH-1:0]);
295 : assign lsu_raw_fwd_hi_m = (|stbuf_fwdbyteen_hi_m[pt.DCCM_BYTE_WIDTH-1:0]);
296 :
297 : el2_lsu_lsc_ctl #(.pt(pt)) lsu_lsc_ctl (.*);
298 :
299 : // block stores in decode - for either bus or stbuf reasons
300 : assign lsu_store_stall_any = lsu_stbuf_full_any | lsu_bus_buffer_full_any | ld_single_ecc_error_r_ff;
301 : assign lsu_load_stall_any = lsu_bus_buffer_full_any | ld_single_ecc_error_r_ff;
302 : assign lsu_fastint_stall_any = ld_single_ecc_error_r; // Stall the fastint in decode-1 stage
303 :
304 : // Ready to accept dma trxns
305 : // There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m
306 : assign dma_mem_tag_d[2:0] = dma_mem_tag[2:0];
307 : assign ldst_nodma_mtor = (lsu_pkt_m.valid & ~lsu_pkt_m.dma & (addr_in_dccm_m | addr_in_pic_m) & lsu_pkt_m.store);
308 :
309 : assign dccm_ready = ~(dec_lsu_valid_raw_d | ldst_nodma_mtor | ld_single_ecc_error_r_ff);
310 :
311 : assign dma_dccm_wen = dma_dccm_req & dma_mem_write & addr_in_dccm_d & dma_mem_sz[1]; // Perform DMA writes only for word/dword
312 : assign dma_pic_wen = dma_dccm_req & dma_mem_write & addr_in_pic_d;
313 : assign {dma_dccm_wdata_hi[31:0], dma_dccm_wdata_lo[31:0]} = 64'(dma_mem_wdata[63:0] >> {dma_mem_addr[2:0], 3'b000}); // Shift the dma data to lower bits to make it consistent to lsu stores
314 :
315 :
316 : // Generate per cycle flush signals
317 : assign flush_m_up = dec_tlu_flush_lower_r;
318 : assign flush_r = dec_tlu_i0_kill_writeb_r;
319 :
320 : // lsu idle
321 : // lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence.
322 : // Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error
323 : // Store buffer now have only non-dma dccm stores
324 : // stbuf_empty not needed since it has only dccm stores
325 : assign lsu_idle_any = ~((lsu_pkt_m.valid & ~lsu_pkt_m.dma) |
326 : (lsu_pkt_r.valid & ~lsu_pkt_r.dma)) &
327 : lsu_bus_buffer_empty_any;
328 :
329 : assign lsu_active = (lsu_pkt_m.valid | lsu_pkt_r.valid | ld_single_ecc_error_r_ff) | ~lsu_bus_buffer_empty_any; // This includes DMA. Used for gating top clock
330 :
331 : // Instantiate the store buffer
332 : assign store_stbuf_reqvld_r = lsu_pkt_r.valid & lsu_pkt_r.store & addr_in_dccm_r & ~flush_r & (~lsu_pkt_r.dma | ((lsu_pkt_r.by | lsu_pkt_r.half) & ~lsu_double_ecc_error_r));
333 :
334 : // Disable Forwarding for now
335 : assign lsu_cmpen_m = lsu_pkt_m.valid & (lsu_pkt_m.load | lsu_pkt_m.store) & (addr_in_dccm_m | addr_in_pic_m);
336 :
337 : // Bus signals
338 : assign lsu_busreq_m = lsu_pkt_m.valid & ((lsu_pkt_m.load | lsu_pkt_m.store) & addr_external_m) & ~flush_m_up & ~lsu_exc_m & ~lsu_pkt_m.fast_int;
339 :
340 : // Dual signals
341 : assign ldst_dual_d = (lsu_addr_d[2] != end_addr_d[2]);
342 : assign ldst_dual_m = (lsu_addr_m[2] != end_addr_m[2]);
343 : assign ldst_dual_r = (lsu_addr_r[2] != end_addr_r[2]);
344 :
345 : // PMU signals
346 : assign lsu_pmu_misaligned_m = lsu_pkt_m.valid & ((lsu_pkt_m.half & lsu_addr_m[0]) | (lsu_pkt_m.word & (|lsu_addr_m[1:0])));
347 : assign lsu_pmu_load_external_m = lsu_pkt_m.valid & lsu_pkt_m.load & addr_external_m;
348 : assign lsu_pmu_store_external_m = lsu_pkt_m.valid & lsu_pkt_m.store & addr_external_m;
349 :
350 : el2_lsu_dccm_ctl #(.pt(pt)) dccm_ctl (
351 : .lsu_addr_d(lsu_addr_d[31:0]),
352 : .end_addr_d(end_addr_d[pt.DCCM_BITS-1:0]),
353 : .lsu_addr_m(lsu_addr_m[pt.DCCM_BITS-1:0]),
354 : .lsu_addr_r(lsu_addr_r[31:0]),
355 :
356 : .end_addr_m(end_addr_m[pt.DCCM_BITS-1:0]),
357 : .end_addr_r(end_addr_r[pt.DCCM_BITS-1:0]),
358 : .*
359 : );
360 :
361 : el2_lsu_stbuf #(.pt(pt)) stbuf (
362 : .lsu_addr_d(lsu_addr_d[pt.LSU_SB_BITS-1:0]),
363 : .end_addr_d(end_addr_d[pt.LSU_SB_BITS-1:0]),
364 :
365 : .*
366 :
367 : );
368 :
369 : el2_lsu_ecc #(.pt(pt)) ecc (
370 : .lsu_addr_r(lsu_addr_r[pt.DCCM_BITS-1:0]),
371 : .end_addr_r(end_addr_r[pt.DCCM_BITS-1:0]),
372 : .lsu_addr_m(lsu_addr_m[pt.DCCM_BITS-1:0]),
373 : .end_addr_m(end_addr_m[pt.DCCM_BITS-1:0]),
374 : .*
375 : );
376 :
377 : el2_lsu_trigger #(.pt(pt)) trigger (
378 : .store_data_m(store_data_m[31:0]),
379 : .*
380 : );
381 :
382 : // Clk domain
383 : el2_lsu_clkdomain #(.pt(pt)) clkdomain (.*);
384 :
385 : // Bus interface
386 : el2_lsu_bus_intf #(.pt(pt)) bus_intf (
387 : .lsu_addr_m(lsu_addr_m[31:0] & {32{addr_external_m & lsu_pkt_m.valid}}),
388 : .lsu_addr_r(lsu_addr_r[31:0] & {32{lsu_busreq_r}}),
389 :
390 : .end_addr_m(end_addr_m[31:0] & {32{addr_external_m & lsu_pkt_m.valid}}),
391 : .end_addr_r(end_addr_r[31:0] & {32{lsu_busreq_r}}),
392 :
393 : .store_data_r(store_data_r[31:0] & {32{lsu_busreq_r}}),
394 : .*
395 : );
396 :
397 : //Flops
398 : rvdff #(3) dma_mem_tag_mff (.*, .din(dma_mem_tag_d[2:0]), .dout(dma_mem_tag_m[2:0]), .clk(lsu_c1_m_clk));
399 : rvdff #(2) lsu_raw_fwd_r_ff (.*, .din({lsu_raw_fwd_hi_m, lsu_raw_fwd_lo_m}), .dout({lsu_raw_fwd_hi_r, lsu_raw_fwd_lo_r}), .clk(lsu_c2_r_clk));
400 :
401 : `ifdef RV_ASSERT_ON
402 : logic [1:0] store_data_bypass_sel;
403 : assign store_data_bypass_sel[1:0] = {lsu_p.store_data_bypass_d, lsu_p.store_data_bypass_m};
404 :
405 : property exception_no_lsu_flush;
406 : @(posedge clk) disable iff(~rst_l) lsu_lsc_ctl.lsu_error_pkt_m.exc_valid |-> ##[1:2] (flush_r );
407 : endproperty
408 : assert_exception_no_lsu_flush: assert property (exception_no_lsu_flush) else
409 : $display("No flush within 2 cycles of exception");
410 :
411 : // offset should be zero for fast interrupt
412 : property offset_0_fastint;
413 : @(posedge clk) disable iff(~rst_l) (lsu_p.valid & lsu_p.fast_int) |-> (dec_lsu_offset_d[11:0] == 12'b0);
414 : endproperty
415 : assert_offset_0_fastint: assert property (offset_0_fastint) else
416 : $display("dec_tlu_offset_d not zero for fast interrupt redirect");
417 :
418 : // DMA req should assert dccm rden/wren
419 : property dmareq_dccm_wren_or_rden;
420 : @(posedge clk) disable iff(~rst_l) dma_dccm_req |-> (dccm_rden | dccm_wren | addr_in_pic_d);
421 : endproperty
422 : assert_dmareq_dccm_wren_or_rden: assert property(dmareq_dccm_wren_or_rden) else
423 : $display("dccm rden or wren not asserted during DMA request");
424 :
425 : // fastint_stall should cause load/store stall next cycle
426 : property fastint_stall_imply_loadstore_stall;
427 : @(posedge clk) disable iff(~rst_l) (lsu_fastint_stall_any & (lsu_commit_r | lsu_pkt_r.dma)) |-> ##1 ((lsu_load_stall_any | lsu_store_stall_any) | ~ld_single_ecc_error_r_ff);
428 : endproperty
429 : assert_fastint_stall_imply_loadstore_stall: assert property (fastint_stall_imply_loadstore_stall) else
430 : $display("fastint_stall should be followed by lsu_load/store_stall_any");
431 :
432 : // Single ECC error implies rfnpc flush
433 : property single_ecc_error_rfnpc_flush;
434 : @(posedge clk) disable iff(~rst_l) (lsu_error_pkt_r.single_ecc_error & lsu_pkt_r.load) |=> ~lsu_commit_r;
435 : endproperty
436 : assert_single_ecc_error_rfnpc_flush: assert property (single_ecc_error_rfnpc_flush) else
437 : $display("LSU commit next cycle after single ecc error");
438 :
439 : `endif
440 :
441 : endmodule // el2_lsu
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