Line data Source code
1 : //********************************************************************************
2 : // SPDX-License-Identifier: Apache-2.0
3 : // Copyright 2020 Western Digital Corporation or its affiliates.
4 : // Copyright (c) 2023 Antmicro <www.antmicro.com>
5 : //
6 : // Licensed under the Apache License, Version 2.0 (the "License");
7 : // you may not use this file except in compliance with the License.
8 : // You may obtain a copy of the License at
9 : //
10 : // http://www.apache.org/licenses/LICENSE-2.0
11 : //
12 : // Unless required by applicable law or agreed to in writing, software
13 : // distributed under the License is distributed on an "AS IS" BASIS,
14 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 : // See the License for the specific language governing permissions and
16 : // limitations under the License.
17 : //********************************************************************************
18 :
19 : //********************************************************************************
20 : // Icache closely coupled memory --- ICCM
21 : //********************************************************************************
22 :
23 : module el2_ifu_iccm_mem
24 : import el2_pkg::*;
25 : #(
26 : `include "el2_param.vh"
27 : )(
28 69894182 : input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
29 69894182 : input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
30 339 : input logic rst_l, // reset, active low
31 2 : input logic clk_override, // Override non-functional clock gating
32 :
33 1074 : input logic iccm_wren, // ICCM write enable
34 134206 : input logic iccm_rden, // ICCM read enable
35 160625 : input logic [pt.ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address
36 8 : input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
37 8 : input logic iccm_correction_state, // ICCM under a correction - This is needed to guard replacements when hit
38 1 : input logic [2:0] iccm_wr_size, // ICCM write size
39 249 : input logic [77:0] iccm_wr_data, // ICCM write data
40 :
41 : el2_mem_if.veer_iccm iccm_mem_export, // RAM repositioned in testbench and connected by this interface
42 :
43 136799 : output logic [63:0] iccm_rd_data, // ICCM read data
44 161531 : output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc
45 0 : input logic scan_mode // Scan mode control
46 :
47 : );
48 :
49 :
50 16 : logic [pt.ICCM_NUM_BANKS-1:0] wren_bank;
51 262048 : logic [pt.ICCM_NUM_BANKS-1:0] rden_bank;
52 262066 : logic [pt.ICCM_NUM_BANKS-1:0] iccm_clken;
53 160097 : logic [pt.ICCM_NUM_BANKS-1:0] [pt.ICCM_BITS-1:pt.ICCM_BANK_INDEX_LO] addr_bank;
54 :
55 22051 : logic [pt.ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_dout, iccm_bank_dout_fn;
56 248 : logic [pt.ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data;
57 159916 : logic [pt.ICCM_BITS-1:1] addr_bank_inc;
58 4259187 : logic [pt.ICCM_BANK_HI : 2] iccm_rd_addr_hi_q;
59 475984 : logic [pt.ICCM_BANK_HI : 1] iccm_rd_addr_lo_q;
60 161531 : logic [63:0] iccm_rd_data_pre;
61 136799 : logic [63:0] iccm_data;
62 1 : logic [1:0] addr_incr;
63 248 : logic [pt.ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data_vec;
64 :
65 : // logic to handle hard persisten faults
66 0 : logic [1:0] [pt.ICCM_BITS-1:2] redundant_address;
67 1 : logic [1:0] [38:0] redundant_data;
68 1 : logic [1:0] redundant_valid;
69 8 : logic [pt.ICCM_NUM_BANKS-1:0] sel_red1, sel_red0, sel_red1_q, sel_red0_q;
70 :
71 :
72 246 : logic [38:0] redundant_data0_in, redundant_data1_in;
73 5 : logic redundant_lru, redundant_lru_in, redundant_lru_en;
74 6 : logic redundant_data0_en;
75 6 : logic redundant_data1_en;
76 4 : logic r0_addr_en, r1_addr_en;
77 :
78 : // Testing persistent flip
79 : // logic [3:0] not_iccm_bank_dout;
80 : // logic [15:3] ecc_insert_flip_in, ecc_insert_flip;
81 : // logic flip_en, flip_match, flip_match_q;
82 : //
83 : // assign flip_in = (iccm_rw_addr[3:2] != 2'b00); // dont flip when bank0 - this is to make some progress in DMA streaming cases
84 : // assign flip_en = iccm_rden;
85 : //
86 : // rvdffs #(1) flipmatch (.*,
87 : // .clk(clk),
88 : // .din(flip_in),
89 : // .en(flip_en),
90 : // .dout(flip_match_q));
91 : //
92 : // end of testing flip
93 :
94 :
95 : assign addr_incr[1:0] = (iccm_wr_size[1:0] == 2'b11) ? 2'b10: 2'b01;
96 : assign addr_bank_inc[pt.ICCM_BITS-1 : 1] = iccm_rw_addr[pt.ICCM_BITS-1 : 1] + addr_incr[1:0];
97 :
98 : for (genvar i=0; i<pt.ICCM_NUM_BANKS/2; i++) begin: mem_bank_data
99 : assign iccm_bank_wr_data_vec[(2*i)] = iccm_wr_data[38:0];
100 : assign iccm_bank_wr_data_vec[(2*i)+1] = iccm_wr_data[77:39];
101 : end
102 :
103 1360 : for (genvar i=0; i<pt.ICCM_NUM_BANKS; i++) begin: mem_bank
104 : assign wren_bank[i] = iccm_wren & ((iccm_rw_addr[pt.ICCM_BANK_HI:2] == i) | (addr_bank_inc[pt.ICCM_BANK_HI:2] == i));
105 : assign iccm_bank_wr_data[i] = iccm_bank_wr_data_vec[i];
106 : assign rden_bank[i] = iccm_rden & ( (iccm_rw_addr[pt.ICCM_BANK_HI:2] == i) | (addr_bank_inc[pt.ICCM_BANK_HI:2] == i));
107 : assign iccm_clken[i] = wren_bank[i] | rden_bank[i] | clk_override;
108 : assign addr_bank[i][pt.ICCM_BITS-1 : pt.ICCM_BANK_INDEX_LO] = wren_bank[i] ? iccm_rw_addr[pt.ICCM_BITS-1 : pt.ICCM_BANK_INDEX_LO] :
109 : ((addr_bank_inc[pt.ICCM_BANK_HI:2] == i) ?
110 : addr_bank_inc[pt.ICCM_BITS-1 : pt.ICCM_BANK_INDEX_LO] :
111 : iccm_rw_addr[pt.ICCM_BITS-1 : pt.ICCM_BANK_INDEX_LO]);
112 :
113 1360 : always_comb begin
114 1360 : iccm_mem_export.iccm_clken[i] = iccm_clken[i];
115 1360 : iccm_mem_export.iccm_wren_bank[i] = wren_bank[i];
116 1360 : iccm_mem_export.iccm_addr_bank[i] = addr_bank[i];
117 1360 : iccm_mem_export.iccm_bank_wr_data[i] = iccm_bank_wr_data[i][31:0];
118 1360 : iccm_mem_export.iccm_bank_wr_ecc[i] = iccm_bank_wr_data[i][32+pt.ICCM_ECC_WIDTH-1:32];
119 1360 : iccm_bank_dout[i][31:0] = iccm_mem_export.iccm_bank_dout[i];
120 1360 : iccm_bank_dout[i][32+pt.ICCM_ECC_WIDTH-1:32] = iccm_mem_export.iccm_bank_ecc[i];
121 : end
122 :
123 : // match the redundant rows
124 : assign sel_red1[i] = (redundant_valid[1] & (((iccm_rw_addr[pt.ICCM_BITS-1:2] == redundant_address[1][pt.ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) |
125 : ((addr_bank_inc[pt.ICCM_BITS-1:2]== redundant_address[1][pt.ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
126 :
127 : assign sel_red0[i] = (redundant_valid[0] & (((iccm_rw_addr[pt.ICCM_BITS-1:2] == redundant_address[0][pt.ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) |
128 : ((addr_bank_inc[pt.ICCM_BITS-1:2]== redundant_address[0][pt.ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
129 :
130 : rvdff #(1) selred0 (.*,
131 : .clk(active_clk),
132 : .din(sel_red0[i]),
133 : .dout(sel_red0_q[i]));
134 :
135 : rvdff #(1) selred1 (.*,
136 : .clk(active_clk),
137 : .din(sel_red1[i]),
138 : .dout(sel_red1_q[i]));
139 :
140 :
141 : // muxing out the memory data with the redundant data if the address matches
142 : assign iccm_bank_dout_fn[i][38:0] = ({39{sel_red1_q[i]}} & redundant_data[1][38:0]) |
143 : ({39{sel_red0_q[i]}} & redundant_data[0][38:0]) |
144 : ({39{~sel_red0_q[i] & ~sel_red1_q[i]}} & iccm_bank_dout[i][38:0]);
145 :
146 : end : mem_bank
147 : // This section does the redundancy for tolerating single bit errors
148 : // 2x 39 bit data values with address[hi:2] and a valid bit is needed to CAM and sub out the reads/writes to the particular locations
149 : // Also a LRU flop is kept to decide which of the redundant element to replace.
150 : assign r0_addr_en = ~redundant_lru & iccm_buf_correct_ecc;
151 : assign r1_addr_en = redundant_lru & iccm_buf_correct_ecc;
152 : assign redundant_lru_en = iccm_buf_correct_ecc | (((|sel_red0[pt.ICCM_NUM_BANKS-1:0]) | (|sel_red1[pt.ICCM_NUM_BANKS-1:0])) & iccm_rden & iccm_correction_state);
153 : assign redundant_lru_in = iccm_buf_correct_ecc ? ~redundant_lru : (|sel_red0[pt.ICCM_NUM_BANKS-1:0]) ? 1'b1 : 1'b0;
154 :
155 : rvdffs #() red_lru (.*, // LRU flop for the redundant replacements
156 : .clk(active_clk),
157 : .en(redundant_lru_en),
158 : .din(redundant_lru_in),
159 : .dout(redundant_lru));
160 :
161 : rvdffs #(pt.ICCM_BITS-2) r0_address (.*, // Redundant Row 0 address
162 : .clk(active_clk),
163 : .en(r0_addr_en),
164 : .din(iccm_rw_addr[pt.ICCM_BITS-1:2]),
165 : .dout(redundant_address[0][pt.ICCM_BITS-1:2]));
166 :
167 : rvdffs #(pt.ICCM_BITS-2) r1_address (.*, // Redundant Row 0 address
168 : .clk(active_clk),
169 : .en(r1_addr_en),
170 : .din(iccm_rw_addr[pt.ICCM_BITS-1:2]),
171 : .dout(redundant_address[1][pt.ICCM_BITS-1:2]));
172 :
173 : rvdffs #(1) r0_valid (.*,
174 : .clk(active_clk), // Redundant Row 0 Valid
175 : .en(r0_addr_en),
176 : .din(1'b1),
177 : .dout(redundant_valid[0]));
178 :
179 : rvdffs #(1) r1_valid (.*, // Redundant Row 1 Valid
180 : .clk(active_clk),
181 : .en(r1_addr_en),
182 : .din(1'b1),
183 : .dout(redundant_valid[1]));
184 :
185 :
186 :
187 : // We will have to update the Redundant copies in addition to the memory on subsequent writes to this memory location.
188 : // The data gets updated on : 1) correction cycle, 2) Future writes - this could be W writes from DMA ( match up till addr[2]) or DW writes ( match till address[3])
189 : // The data to pick also depends on the current address[2], size and the addr[2] stored in the address field of the redundant flop. Correction cycle is always W write and the data is splat on both legs, so choosing lower Word
190 :
191 : assign redundant_data0_en = ((iccm_rw_addr[pt.ICCM_BITS-1:3] == redundant_address[0][pt.ICCM_BITS-1:3]) & ((iccm_rw_addr[2] == redundant_address[0][2]) | (iccm_wr_size[1:0] == 2'b11)) & redundant_valid[0] & iccm_wren) |
192 : (~redundant_lru & iccm_buf_correct_ecc);
193 :
194 : assign redundant_data0_in[38:0] = (((iccm_rw_addr[2] == redundant_address[0][2]) & iccm_rw_addr[2]) | (redundant_address[0][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
195 :
196 : rvdffs #(39) r0_data (.*, // Redundant Row 1 data
197 : .clk(active_clk),
198 : .en(redundant_data0_en),
199 : .din(redundant_data0_in[38:0]),
200 : .dout(redundant_data[0][38:0]));
201 :
202 : assign redundant_data1_en = ((iccm_rw_addr[pt.ICCM_BITS-1:3] == redundant_address[1][pt.ICCM_BITS-1:3]) & ((iccm_rw_addr[2] == redundant_address[1][2]) | (iccm_wr_size[1:0] == 2'b11)) & redundant_valid[1] & iccm_wren) |
203 : (redundant_lru & iccm_buf_correct_ecc);
204 :
205 : assign redundant_data1_in[38:0] = (((iccm_rw_addr[2] == redundant_address[1][2]) & iccm_rw_addr[2]) | (redundant_address[1][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
206 :
207 : rvdffs #(39) r1_data (.*, // Redundant Row 1 data
208 : .clk(active_clk),
209 : .en(redundant_data1_en),
210 : .din(redundant_data1_in[38:0]),
211 : .dout(redundant_data[1][38:0]));
212 :
213 :
214 : rvdffs #(pt.ICCM_BANK_HI) rd_addr_lo_ff (.*, .clk(active_clk), .din(iccm_rw_addr [pt.ICCM_BANK_HI:1]), .dout(iccm_rd_addr_lo_q[pt.ICCM_BANK_HI:1]), .en(1'b1)); // bit 0 of address is always 0
215 : rvdffs #(pt.ICCM_BANK_BITS) rd_addr_hi_ff (.*, .clk(active_clk), .din(addr_bank_inc[pt.ICCM_BANK_HI:2]), .dout(iccm_rd_addr_hi_q[pt.ICCM_BANK_HI:2]), .en(1'b1));
216 :
217 : assign iccm_rd_data_pre[63:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][31:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[pt.ICCM_BANK_HI:2]][31:0]};
218 : assign iccm_data[63:0] = 64'({16'b0, (iccm_rd_data_pre[63:0] >> (16*iccm_rd_addr_lo_q[1]))});
219 : assign iccm_rd_data[63:0] = {iccm_data[63:0]};
220 : assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[pt.ICCM_BANK_HI:2]][38:0]};
221 :
222 : endmodule // el2_ifu_iccm_mem
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