Line data Source code
1 : //********************************************************************************
2 : // SPDX-License-Identifier: Apache-2.0
3 : // Copyright 2020 Western Digital Corporation or its affiliates.
4 : //
5 : // Licensed under the Apache License, Version 2.0 (the "License");
6 : // you may not use this file except in compliance with the License.
7 : // You may obtain a copy of the License at
8 : //
9 : // http://www.apache.org/licenses/LICENSE-2.0
10 : //
11 : // Unless required by applicable law or agreed to in writing, software
12 : // distributed under the License is distributed on an "AS IS" BASIS,
13 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 : // See the License for the specific language governing permissions and
15 : // limitations under the License.
16 : //********************************************************************************
17 :
18 : // purpose of this file is to convert 16b RISCV compressed instruction into 32b equivalent
19 :
20 : module el2_ifu_compress_ctl
21 : import el2_pkg::*;
22 : #(
23 : `include "el2_param.vh"
24 : )
25 : (
26 535266 : input logic [15:0] din, // 16-bit compressed instruction
27 241481 : output logic [31:0] dout // 32-bit uncompressed instruction
28 : );
29 :
30 :
31 4318579 : logic legal;
32 :
33 535266 : logic [15:0] i;
34 :
35 986 : logic [31:0] o,l1,l2,l3;
36 :
37 :
38 : assign i[15:0] = din[15:0];
39 :
40 :
41 0 : logic [4:0] rs2d,rdd,rdpd,rs2pd;
42 :
43 3412966 : logic rdrd;
44 2809384 : logic rdrs1;
45 840288 : logic rs2rs2;
46 251899 : logic rdprd;
47 790601 : logic rdprs1;
48 237922 : logic rs2prs2;
49 4293927 : logic rs2prd;
50 4304261 : logic uimm9_2;
51 169468 : logic ulwimm6_2;
52 149356 : logic ulwspimm7_2;
53 37104 : logic rdeq2;
54 150290 : logic rdeq1;
55 4149425 : logic rs1eq2;
56 378614 : logic sbroffset8_1;
57 37104 : logic simm9_4;
58 2657641 : logic simm5_0;
59 281118 : logic sjaloffset11_1;
60 50558 : logic sluimm17_12;
61 160790 : logic uimm5_0;
62 86238 : logic uswimm6_2;
63 148790 : logic uswspimm7_2;
64 :
65 :
66 :
67 : // form the opcodes
68 :
69 : // formats
70 : //
71 : // c.add rd 11:7 rs2 6:2
72 : // c.and rdp 9:7 rs2p 4:2
73 : //
74 : // add rs2 24:20 rs1 19:15 rd 11:7
75 :
76 : assign rs2d[4:0] = i[6:2];
77 :
78 : assign rdd[4:0] = i[11:7];
79 :
80 : assign rdpd[4:0] = {2'b01, i[9:7]};
81 :
82 : assign rs2pd[4:0] = {2'b01, i[4:2]};
83 :
84 :
85 :
86 : // merge in rd, rs1, rs2
87 :
88 :
89 : // rd
90 : assign l1[6:0] = o[6:0];
91 :
92 : assign l1[11:7] = o[11:7] |
93 : ({5{rdrd}} & rdd[4:0]) |
94 : ({5{rdprd}} & rdpd[4:0]) |
95 : ({5{rs2prd}} & rs2pd[4:0]) |
96 : ({5{rdeq1}} & 5'd1) |
97 : ({5{rdeq2}} & 5'd2);
98 :
99 :
100 : // rs1
101 : assign l1[14:12] = o[14:12];
102 : assign l1[19:15] = o[19:15] |
103 : ({5{rdrs1}} & rdd[4:0]) |
104 : ({5{rdprs1}} & rdpd[4:0]) |
105 : ({5{rs1eq2}} & 5'd2);
106 :
107 :
108 : // rs2
109 : assign l1[24:20] = o[24:20] |
110 : ({5{rs2rs2}} & rs2d[4:0]) |
111 : ({5{rs2prs2}} & rs2pd[4:0]);
112 :
113 : assign l1[31:25] = o[31:25];
114 :
115 2439572 : logic [5:0] simm5d;
116 831616 : logic [9:2] uimm9d;
117 :
118 2439572 : logic [9:4] simm9d;
119 2394690 : logic [6:2] ulwimm6d;
120 2439574 : logic [7:2] ulwspimm7d;
121 2439572 : logic [5:0] uimm5d;
122 831596 : logic [20:1] sjald;
123 :
124 2439572 : logic [31:12] sluimmd;
125 :
126 : // merge in immediates + jal offset
127 :
128 : assign simm5d[5:0] = { i[12], i[6:2] };
129 :
130 : assign uimm9d[9:2] = { i[10:7], i[12:11], i[5], i[6] };
131 :
132 : assign simm9d[9:4] = { i[12], i[4:3], i[5], i[2], i[6] };
133 :
134 : assign ulwimm6d[6:2] = { i[5], i[12:10], i[6] };
135 :
136 : assign ulwspimm7d[7:2] = { i[3:2], i[12], i[6:4] };
137 :
138 : assign uimm5d[5:0] = { i[12], i[6:2] };
139 :
140 : assign sjald[11:1] = { i[12], i[8], i[10:9], i[6], i[7], i[2], i[11], i[5:4], i[3] };
141 :
142 : assign sjald[20:12] = {9{i[12]}};
143 :
144 :
145 :
146 : assign sluimmd[31:12] = { {15{i[12]}}, i[6:2] };
147 :
148 :
149 : assign l2[31:20] = ( l1[31:20] ) |
150 : ( {12{simm5_0}} & {{7{simm5d[5]}},simm5d[4:0]} ) |
151 : ( {12{uimm9_2}} & {2'b0,uimm9d[9:2],2'b0} ) |
152 : ( {12{simm9_4}} & {{3{simm9d[9]}},simm9d[8:4],4'b0} ) |
153 : ( {12{ulwimm6_2}} & {5'b0,ulwimm6d[6:2],2'b0} ) |
154 : ( {12{ulwspimm7_2}} & {4'b0,ulwspimm7d[7:2],2'b0} ) |
155 : ( {12{uimm5_0}} & {6'b0,uimm5d[5:0]} ) |
156 : ( {12{sjaloffset11_1}} & {sjald[20],sjald[10:1],sjald[11]} ) |
157 : ( {12{sluimm17_12}} & sluimmd[31:20] );
158 :
159 :
160 :
161 : assign l2[19:12] = ( l1[19:12] ) |
162 : ( {8{sjaloffset11_1}} & sjald[19:12] ) |
163 : ( {8{sluimm17_12}} & sluimmd[19:12] );
164 :
165 :
166 : assign l2[11:0] = l1[11:0];
167 :
168 :
169 : // merge in branch offset and store immediates
170 :
171 2387442 : logic [8:1] sbr8d;
172 2394690 : logic [6:2] uswimm6d;
173 835332 : logic [7:2] uswspimm7d;
174 :
175 :
176 : assign sbr8d[8:1] = { i[12], i[6], i[5], i[2], i[11], i[10], i[4], i[3] };
177 :
178 : assign uswimm6d[6:2] = { i[5], i[12:10], i[6] };
179 :
180 : assign uswspimm7d[7:2] = { i[8:7], i[12:9] };
181 :
182 : assign l3[31:25] = ( l2[31:25] ) |
183 : ( {7{sbroffset8_1}} & { {4{sbr8d[8]}},sbr8d[7:5] } ) |
184 : ( {7{uswimm6_2}} & { 5'b0, uswimm6d[6:5] } ) |
185 : ( {7{uswspimm7_2}} & { 4'b0, uswspimm7d[7:5] } );
186 :
187 :
188 : assign l3[24:12] = l2[24:12];
189 :
190 : assign l3[11:7] = ( l2[11:7] ) |
191 : ( {5{sbroffset8_1}} & { sbr8d[4:1], sbr8d[8] } ) |
192 : ( {5{uswimm6_2}} & { uswimm6d[4:2], 2'b0 } ) |
193 : ( {5{uswspimm7_2}} & { uswspimm7d[4:2], 2'b0 } );
194 :
195 : assign l3[6:0] = l2[6:0];
196 :
197 :
198 : assign dout[31:0] = l3[31:0] & {32{legal}};
199 :
200 :
201 : // file "cdecode" is human readable file that has all of the compressed instruction decodes defined and is part of git repo
202 : // modify this file as needed
203 :
204 : // to generate all the equations below from "cdecode" except legal equation:
205 :
206 : // 1) coredecode -in cdecode > cdecode.e
207 :
208 : // 2) espresso -Dso -oeqntott cdecode.e | addassign > compress_equations
209 :
210 : // to generate the legal (16b compressed instruction is legal) equation below:
211 :
212 : // 1) coredecode -in cdecode -legal > clegal.e
213 :
214 : // 2) espresso -Dso -oeqntott clegal.e | addassign > clegal_equation
215 :
216 :
217 :
218 :
219 :
220 : // espresso decodes
221 : assign rdrd = (!i[14]&i[6]&i[1]) | (!i[15]&i[14]&i[11]&i[0]) | (!i[14]&i[5]&i[1]) | (
222 : !i[15]&i[14]&i[10]&i[0]) | (!i[14]&i[4]&i[1]) | (!i[15]&i[14]&i[9]
223 : &i[0]) | (!i[14]&i[3]&i[1]) | (!i[15]&i[14]&!i[8]&i[0]) | (!i[14]
224 : &i[2]&i[1]) | (!i[15]&i[14]&i[7]&i[0]) | (!i[15]&i[1]) | (!i[15]
225 : &!i[13]&i[0]);
226 :
227 : assign rdrs1 = (!i[14]&i[12]&i[11]&i[1]) | (!i[14]&i[12]&i[10]&i[1]) | (!i[14]
228 : &i[12]&i[9]&i[1]) | (!i[14]&i[12]&i[8]&i[1]) | (!i[14]&i[12]&i[7]
229 : &i[1]) | (!i[14]&!i[12]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]
230 : &i[12]&i[6]&i[1]) | (!i[14]&i[12]&i[5]&i[1]) | (!i[14]&i[12]&i[4]
231 : &i[1]) | (!i[14]&i[12]&i[3]&i[1]) | (!i[14]&i[12]&i[2]&i[1]) | (
232 : !i[15]&!i[14]&!i[13]&i[0]) | (!i[15]&!i[14]&i[1]);
233 :
234 : assign rs2rs2 = (i[15]&i[6]&i[1]) | (i[15]&i[5]&i[1]) | (i[15]&i[4]&i[1]) | (
235 : i[15]&i[3]&i[1]) | (i[15]&i[2]&i[1]) | (i[15]&i[14]&i[1]);
236 :
237 : assign rdprd = (i[15]&!i[14]&!i[13]&i[0]);
238 :
239 : assign rdprs1 = (i[15]&!i[13]&i[0]) | (i[15]&i[14]&i[0]) | (i[14]&!i[1]&!i[0]);
240 :
241 : assign rs2prs2 = (i[15]&!i[14]&!i[13]&i[11]&i[10]&i[0]) | (i[15]&!i[1]&!i[0]);
242 :
243 : assign rs2prd = (!i[15]&!i[1]&!i[0]);
244 :
245 : assign uimm9_2 = (!i[14]&!i[1]&!i[0]);
246 :
247 : assign ulwimm6_2 = (!i[15]&i[14]&!i[1]&!i[0]);
248 :
249 : assign ulwspimm7_2 = (!i[15]&i[14]&i[1]);
250 :
251 : assign rdeq2 = (!i[15]&i[14]&i[13]&!i[11]&!i[10]&!i[9]&i[8]&!i[7]);
252 :
253 : assign rdeq1 = (!i[14]&i[12]&i[11]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]
254 : &i[12]&i[10]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[9]
255 : &!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[8]&!i[6]&!i[5]
256 : &!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[7]&!i[6]&!i[5]&!i[4]&!i[3]
257 : &!i[2]&i[1]) | (!i[15]&!i[14]&i[13]);
258 :
259 : assign rs1eq2 = (!i[15]&i[14]&i[13]&!i[11]&!i[10]&!i[9]&i[8]&!i[7]) | (i[14]
260 : &i[1]) | (!i[14]&!i[1]&!i[0]);
261 :
262 : assign sbroffset8_1 = (i[15]&i[14]&i[0]);
263 :
264 : assign simm9_4 = (!i[15]&i[14]&i[13]&!i[11]&!i[10]&!i[9]&i[8]&!i[7]);
265 :
266 : assign simm5_0 = (!i[14]&!i[13]&i[11]&!i[10]&i[0]) | (!i[15]&!i[13]&i[0]);
267 :
268 : assign sjaloffset11_1 = (!i[14]&i[13]);
269 :
270 : assign sluimm17_12 = (!i[15]&i[14]&i[13]&i[7]) | (!i[15]&i[14]&i[13]&!i[8]) | (
271 : !i[15]&i[14]&i[13]&i[9]) | (!i[15]&i[14]&i[13]&i[10]) | (!i[15]&i[14]
272 : &i[13]&i[11]);
273 :
274 : assign uimm5_0 = (i[15]&!i[14]&!i[13]&!i[11]&i[0]) | (!i[15]&!i[14]&i[1]);
275 :
276 : assign uswimm6_2 = (i[15]&!i[1]&!i[0]);
277 :
278 : assign uswspimm7_2 = (i[15]&i[14]&i[1]);
279 :
280 : assign o[31] = 1'b0;
281 :
282 : assign o[30] = (i[15]&!i[14]&!i[13]&i[10]&!i[6]&!i[5]&i[0]) | (i[15]&!i[14]
283 : &!i[13]&!i[11]&i[10]&i[0]);
284 :
285 : assign o[29] = 1'b0;
286 :
287 : assign o[28] = 1'b0;
288 :
289 : assign o[27] = 1'b0;
290 :
291 : assign o[26] = 1'b0;
292 :
293 : assign o[25] = 1'b0;
294 :
295 : assign o[24] = 1'b0;
296 :
297 : assign o[23] = 1'b0;
298 :
299 : assign o[22] = 1'b0;
300 :
301 : assign o[21] = 1'b0;
302 :
303 : assign o[20] = (!i[14]&i[12]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[6]&!i[5]&!i[4]
304 : &!i[3]&!i[2]&i[1]);
305 :
306 : assign o[19] = 1'b0;
307 :
308 : assign o[18] = 1'b0;
309 :
310 : assign o[17] = 1'b0;
311 :
312 : assign o[16] = 1'b0;
313 :
314 : assign o[15] = 1'b0;
315 :
316 : assign o[14] = (i[15]&!i[14]&!i[13]&!i[11]&i[0]) | (i[15]&!i[14]&!i[13]&!i[10]
317 : &i[0]) | (i[15]&!i[14]&!i[13]&i[6]&i[0]) | (i[15]&!i[14]&!i[13]&i[5]
318 : &i[0]);
319 :
320 : assign o[13] = (i[15]&!i[14]&!i[13]&i[11]&!i[10]&i[0]) | (i[15]&!i[14]&!i[13]
321 : &i[11]&i[6]&i[0]) | (i[14]&!i[0]);
322 :
323 : assign o[12] = (i[15]&!i[14]&!i[13]&i[6]&i[5]&i[0]) | (i[15]&!i[14]&!i[13]&!i[11]
324 : &i[0]) | (i[15]&!i[14]&!i[13]&!i[10]&i[0]) | (!i[15]&!i[14]&i[1]) | (
325 : i[15]&i[14]&i[13]);
326 :
327 : assign o[11] = 1'b0;
328 :
329 : assign o[10] = 1'b0;
330 :
331 : assign o[9] = 1'b0;
332 :
333 : assign o[8] = 1'b0;
334 :
335 : assign o[7] = 1'b0;
336 :
337 : assign o[6] = (i[15]&!i[14]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&!i[0]) | (!i[14]&i[13]) | (
338 : i[15]&i[14]&i[0]);
339 :
340 : assign o[5] = (i[15]&!i[0]) | (i[15]&i[11]&i[10]) | (i[13]&!i[8]) | (i[13]&i[7]) | (
341 : i[13]&i[9]) | (i[13]&i[10]) | (i[13]&i[11]) | (!i[14]&i[13]) | (
342 : i[15]&i[14]);
343 :
344 : assign o[4] = (!i[14]&!i[11]&!i[10]&!i[9]&!i[8]&!i[7]&!i[0]) | (!i[15]&!i[14]
345 : &!i[0]) | (!i[14]&i[6]&!i[0]) | (!i[15]&i[14]&i[0]) | (!i[14]&i[5]
346 : &!i[0]) | (!i[14]&i[4]&!i[0]) | (!i[14]&!i[13]&i[0]) | (!i[14]&i[3]
347 : &!i[0]) | (!i[14]&i[2]&!i[0]);
348 :
349 : assign o[3] = (!i[14]&i[13]);
350 :
351 : assign o[2] = (!i[14]&i[12]&i[11]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]
352 : &i[12]&i[10]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[9]
353 : &!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[8]&!i[6]&!i[5]
354 : &!i[4]&!i[3]&!i[2]&i[1]) | (!i[14]&i[12]&i[7]&!i[6]&!i[5]&!i[4]&!i[3]
355 : &!i[2]&i[1]) | (i[15]&!i[14]&!i[12]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]
356 : &!i[0]) | (!i[15]&i[13]&!i[8]) | (!i[15]&i[13]&i[7]) | (!i[15]&i[13]
357 : &i[9]) | (!i[15]&i[13]&i[10]) | (!i[15]&i[13]&i[11]) | (!i[14]&i[13]);
358 :
359 : // 32b instruction has lower two bits 2'b11
360 :
361 : assign o[1] = 1'b1;
362 :
363 : assign o[0] = 1'b1;
364 :
365 : assign legal = (!i[13]&!i[12]&i[11]&i[1]&!i[0]) | (!i[13]&!i[12]&i[10]&i[1]&!i[0]) | (
366 : !i[15]&!i[13]&i[11]&!i[1]) | (!i[13]&!i[12]&i[9]&i[1]&!i[0]) | (
367 : !i[13]&!i[12]&i[8]&i[1]&!i[0]) | (!i[15]&!i[13]&i[6]&!i[1]) | (i[15]
368 : &!i[12]&!i[1]&i[0]) | (!i[13]&!i[12]&i[7]&i[1]&!i[0]) | (!i[15]&!i[13]
369 : &i[5]&!i[1]) | (!i[12]&i[6]&!i[1]&i[0]) | (i[15]&!i[13]&i[6]&i[1]
370 : &!i[0]) | (!i[15]&!i[13]&i[10]&!i[1]) | (!i[12]&i[5]&!i[1]&i[0]) | (
371 : i[12]&i[11]&!i[10]&!i[1]&i[0]) | (i[15]&!i[13]&i[5]&i[1]&!i[0]) | (
372 : !i[15]&!i[13]&i[9]&!i[1]) | (i[13]&i[12]&!i[1]&i[0]) | (i[15]&!i[13]
373 : &i[4]&i[1]&!i[0]) | (!i[15]&!i[13]&i[8]&!i[1]) | (i[15]&!i[13]&i[3]
374 : &i[1]&!i[0]) | (i[13]&i[4]&!i[1]&i[0]) | (i[15]&!i[13]&i[2]&i[1]&!i[0]) | (
375 : !i[15]&!i[13]&i[7]&!i[1]) | (i[13]&i[3]&!i[1]&i[0]) | (i[13]&i[2]
376 : &!i[1]&i[0]) | (!i[14]&!i[12]&!i[1]&i[0]) | (i[15]&!i[13]&i[12]&i[1]
377 : &!i[0]) | (i[14]&!i[13]&i[7]&!i[0]) | (i[14]&!i[13]&i[8]&!i[0]) | (
378 : i[14]&!i[13]&i[9]&!i[0]) | (!i[15]&!i[14]&!i[13]&!i[12]&i[1]&!i[0]) | (
379 : i[14]&!i[13]&i[10]&!i[0]) | (i[14]&!i[13]&i[11]&!i[0]) | (!i[15]
380 : &!i[13]&i[12]&!i[1]) | (i[15]&i[14]&!i[13]&!i[0]) | (i[14]&!i[13]
381 : &!i[1]);
382 :
383 :
384 :
385 :
386 : endmodule
|
