Line data Source code
1 : //********************************************************************************
2 : // SPDX-License-Identifier: Apache-2.0
3 : // Copyright 2020 Western Digital Corporation or its affiliates.
4 : //
5 : // Licensed under the Apache License, Version 2.0 (the "License");
6 : // you may not use this file except in compliance with the License.
7 : // You may obtain a copy of the License at
8 : //
9 : // http://www.apache.org/licenses/LICENSE-2.0
10 : //
11 : // Unless required by applicable law or agreed to in writing, software
12 : // distributed under the License is distributed on an "AS IS" BASIS,
13 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 : // See the License for the specific language governing permissions and
15 : // limitations under the License.
16 : //********************************************************************************
17 : //********************************************************************************
18 : // Function: Top level file for Icache, Fetch, Branch prediction & Aligner
19 : // BFF -> F1 -> F2 -> A
20 : //********************************************************************************
21 :
22 : module el2_ifu
23 : import el2_pkg::*;
24 : #(
25 : `include "el2_param.vh"
26 : )
27 : (
28 69890155 : input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.
29 69890155 : input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
30 69890155 : input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
31 338 : input logic rst_l, // reset, active low
32 :
33 6203297 : input logic dec_i0_decode_d, // Valid instruction at D and not blocked
34 :
35 674202 : input logic exu_flush_final, // flush, includes upper and lower
36 6173148 : input logic dec_tlu_i0_commit_cmt , // committed i0
37 8 : input logic dec_tlu_flush_err_wb , // flush due to parity error.
38 230 : input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final
39 227634 : input logic [31:1] exu_flush_path_final, // flush fetch address
40 :
41 0 : input logic [31:0] dec_tlu_mrac_ff ,// Side_effect , cacheable for each region
42 18868 : input logic dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final
43 0 : input logic dec_tlu_flush_leak_one_wb, // ignore bp for leak one fetches
44 :
45 0 : input logic dec_tlu_bpred_disable, // disable all branch prediction
46 8 : input logic dec_tlu_core_ecc_disable, // disable ecc checking and flagging
47 0 : input logic dec_tlu_force_halt, // force halt
48 :
49 : //-------------------------- IFU AXI signals--------------------------
50 : // AXI Write Channels
51 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
52 : /*verilator coverage_off*/
53 : output logic ifu_axi_awvalid,
54 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_awid,
55 : output logic [31:0] ifu_axi_awaddr,
56 : output logic [3:0] ifu_axi_awregion,
57 : output logic [7:0] ifu_axi_awlen,
58 : output logic [2:0] ifu_axi_awsize,
59 : output logic [1:0] ifu_axi_awburst,
60 : output logic ifu_axi_awlock,
61 : output logic [3:0] ifu_axi_awcache,
62 : output logic [2:0] ifu_axi_awprot,
63 : output logic [3:0] ifu_axi_awqos,
64 :
65 : output logic ifu_axi_wvalid,
66 : output logic [63:0] ifu_axi_wdata,
67 : output logic [7:0] ifu_axi_wstrb,
68 : output logic ifu_axi_wlast,
69 :
70 : output logic ifu_axi_bready,
71 : /*verilator coverage_on*/
72 :
73 : // AXI Read Channels
74 5895462 : output logic ifu_axi_arvalid,
75 10364845 : input logic ifu_axi_arready,
76 3590406 : output logic [pt.IFU_BUS_TAG-1:0] ifu_axi_arid,
77 2455058 : output logic [31:0] ifu_axi_araddr,
78 545 : output logic [3:0] ifu_axi_arregion,
79 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
80 : /*verilator coverage_off*/
81 : output logic [7:0] ifu_axi_arlen,
82 : output logic [2:0] ifu_axi_arsize,
83 : output logic [1:0] ifu_axi_arburst,
84 : output logic ifu_axi_arlock,
85 : output logic [3:0] ifu_axi_arcache,
86 : output logic [2:0] ifu_axi_arprot,
87 : output logic [3:0] ifu_axi_arqos,
88 : /*verilator coverage_on*/
89 :
90 11810469 : input logic ifu_axi_rvalid,
91 : /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
92 : /*verilator coverage_off*/
93 : output logic ifu_axi_rready,
94 : /*verilator coverage_on*/
95 1182850 : input logic [pt.IFU_BUS_TAG-1:0] ifu_axi_rid,
96 985567 : input logic [63:0] ifu_axi_rdata,
97 20 : input logic [1:0] ifu_axi_rresp,
98 :
99 338 : input logic ifu_bus_clk_en,
100 :
101 66 : input logic dma_iccm_req,
102 0 : input logic [31:0] dma_mem_addr,
103 0 : input logic [2:0] dma_mem_sz,
104 22 : input logic dma_mem_write,
105 12 : input logic [63:0] dma_mem_wdata,
106 12 : input logic [2:0] dma_mem_tag, // DMA Buffer entry number
107 :
108 :
109 26 : input logic dma_iccm_stall_any,
110 4 : output logic iccm_dma_ecc_error,
111 0 : output logic iccm_dma_rvalid,
112 0 : output logic [63:0] iccm_dma_rdata,
113 12 : output logic [2:0] iccm_dma_rtag, // Tag of the DMA req
114 638334 : output logic iccm_ready,
115 :
116 6203297 : output logic ifu_pmu_instr_aligned,
117 615078 : output logic ifu_pmu_fetch_stall,
118 0 : output logic ifu_ic_error_start, // has all of the I$ ecc/parity for data/tag
119 :
120 : // I$ & ITAG Ports
121 490 : output logic [31:1] ic_rw_addr, // Read/Write addresss to the Icache.
122 10432 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en, // Icache write enable, when filling the Icache.
123 680962 : output logic ic_rd_en, // Icache read enable.
124 :
125 560643 : output logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
126 2137120 : input logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
127 231589 : input logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
128 0 : input logic [25:0] ictag_debug_rd_data,// Debug icache tag.
129 0 : output logic [70:0] ic_debug_wr_data, // Debug wr cache.
130 :
131 0 : output logic [70:0] ifu_ic_debug_rd_data,
132 :
133 0 : input logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, //
134 0 : input logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
135 1738700 : output logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
136 5605966 : output logic ic_sel_premux_data, // Select the premux data.
137 :
138 0 : output logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
139 0 : output logic ic_debug_rd_en, // Icache debug rd
140 0 : output logic ic_debug_wr_en, // Icache debug wr
141 0 : output logic ic_debug_tag_array, // Debug tag array
142 0 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
143 :
144 :
145 255918 : output logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid bits when accessing the Icache. One valid bit per way. F2 stage
146 :
147 109586 : input logic [pt.ICACHE_NUM_WAYS-1:0] ic_rd_hit, // Compare hits from Icache tags. Per way. F2 stage
148 0 : input logic ic_tag_perr, // Icache Tag parity error
149 :
150 :
151 : // ICCM ports
152 160275 : output logic [pt.ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address.
153 74 : output logic iccm_wren, // ICCM write enable (through the DMA)
154 133206 : output logic iccm_rden, // ICCM read enable.
155 14 : output logic [77:0] iccm_wr_data, // ICCM write data.
156 0 : output logic [2:0] iccm_wr_size, // ICCM write location within DW.
157 :
158 136532 : input logic [63:0] iccm_rd_data, // Data read from ICCM.
159 161264 : input logic [77:0] iccm_rd_data_ecc, // Data + ECC read from ICCM.
160 :
161 : // ICCM ECC status
162 0 : output logic ifu_iccm_dma_rd_ecc_single_err, // This fetch has a single ICCM DMA ECC error.
163 8 : output logic ifu_iccm_rd_ecc_single_err, // This fetch has a single ICCM ECC error.
164 4 : output logic ifu_iccm_rd_ecc_double_err, // This fetch has a double ICCM ECC error.
165 :
166 : // Perf counter sigs
167 5895668 : output logic ifu_pmu_ic_miss, // ic miss
168 745274 : output logic ifu_pmu_ic_hit, // ic hit
169 10 : output logic ifu_pmu_bus_error, // iside bus error
170 4468867 : output logic ifu_pmu_bus_busy, // iside bus busy
171 10364514 : output logic ifu_pmu_bus_trxn, // iside bus transactions
172 :
173 :
174 208 : output logic ifu_i0_icaf, // Instruction 0 access fault. From Aligner to Decode
175 274 : output logic [1:0] ifu_i0_icaf_type, // Instruction 0 access fault type
176 :
177 6018075 : output logic ifu_i0_valid, // Instruction 0 valid. From Aligner to Decode
178 86 : output logic ifu_i0_icaf_second, // Instruction 0 has access fault on second 2B of 4B inst
179 2 : output logic ifu_i0_dbecc, // Instruction 0 has double bit ecc error
180 0 : output logic iccm_dma_sb_error, // Single Bit ECC error from a DMA access
181 468826 : output logic[31:0] ifu_i0_instr, // Instruction 0 . From Aligner to Decode
182 1322 : output logic[31:1] ifu_i0_pc, // Instruction 0 pc. From Aligner to Decode
183 5774060 : output logic ifu_i0_pc4, // Instruction 0 is 4 byte. From Aligner to Decode
184 :
185 5894674 : output logic ifu_miss_state_idle, // There is no outstanding miss. Cache miss state is idle.
186 :
187 206674 : output el2_br_pkt_t i0_brp, // Instruction 0 branch packet. From Aligner to Decode
188 651206 : output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
189 631071 : output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
190 21223 : output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
191 0 : output logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index
192 :
193 34482 : input el2_predict_pkt_t exu_mp_pkt, // mispredict packet
194 300192 : input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
195 379120 : input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr, // Mispredict fghr
196 196224 : input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index, // Mispredict index
197 115620 : input logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag, // Mispredict btag
198 :
199 782419 : input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
200 367244 : input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
201 187591 : input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
202 0 : input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
203 :
204 59238 : input dec_tlu_flush_lower_wb,
205 :
206 1428516 : output logic [15:0] ifu_i0_cinst,
207 :
208 444 : output logic [31:1] ifu_pmp_addr,
209 110 : input logic ifu_pmp_error,
210 :
211 : /// Icache debug
212 0 : input el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt ,
213 0 : output logic ifu_ic_debug_rd_data_valid,
214 8 : output logic iccm_buf_correct_ecc,
215 8 : output logic iccm_correction_state,
216 :
217 0 : input logic scan_mode
218 : );
219 :
220 : localparam TAGWIDTH = 2 ;
221 : localparam IDWIDTH = 2 ;
222 :
223 257680 : logic ifu_fb_consume1, ifu_fb_consume2;
224 444 : logic [31:1] ifc_fetch_addr_f;
225 444 : logic [31:1] ifc_fetch_addr_bf;
226 : assign ifu_pmp_addr = ifc_fetch_addr_bf;
227 :
228 6340267 : logic [1:0] ifu_fetch_val; // valids on a 2B boundary, left justified [7] implies valid fetch
229 444 : logic [31:1] ifu_fetch_pc; // starting pc of fetch
230 :
231 0 : logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start;
232 : assign ifu_iccm_dma_rd_ecc_single_err = iccm_dma_rd_ecc_single_err;
233 : assign ifu_iccm_rd_ecc_single_err = iccm_rd_ecc_single_err;
234 : assign ifu_ic_error_start = ic_error_start;
235 :
236 :
237 2635450 : logic ic_write_stall;
238 16 : logic ic_dma_active;
239 640775 : logic ifc_dma_access_ok;
240 182 : logic [1:0] ic_access_fault_f;
241 172 : logic [1:0] ic_access_fault_type_f;
242 5916062 : logic ifu_ic_mb_empty;
243 :
244 6789925 : logic ic_hit_f;
245 :
246 2375527 : logic [1:0] ifu_bp_way_f; // way indication; right justified
247 3171757 : logic ifu_bp_hit_taken_f; // kill next fetch; taken target found
248 518791 : logic [31:1] ifu_bp_btb_target_f; // predicted target PC
249 2405225 : logic ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
250 2025808 : logic [1:0] ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
251 1824638 : logic [1:0] ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
252 2177331 : logic [11:0] ifu_bp_poffset_f; // predicted target
253 70466 : logic [1:0] ifu_bp_ret_f; // predicted ret ; right justified
254 408833 : logic [1:0] ifu_bp_pc4_f; // pc4 indication; right justified
255 957477 : logic [1:0] ifu_bp_valid_f; // branch valid, right justified
256 376935 : logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
257 0 : logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
258 :
259 :
260 6340267 : logic [1:0] ic_fetch_val_f;
261 2168046 : logic [31:0] ic_data_f;
262 2168046 : logic [31:0] ifu_fetch_data_f;
263 3717922 : logic ifc_fetch_req_f;
264 0 : logic ifc_fetch_req_f_raw;
265 0 : logic iccm_dma_rd_ecc_double_err;
266 4 : logic [1:0] iccm_rd_ecc_double_err; // This fetch has an iccm double error.
267 : assign ifu_iccm_rd_ecc_double_err = |iccm_rd_ecc_double_err || |iccm_dma_rd_ecc_double_err;
268 :
269 8 : logic ifu_async_error_start;
270 :
271 :
272 : assign ifu_fetch_data_f[31:0] = ic_data_f[31:0];
273 : assign ifu_fetch_val[1:0] = ic_fetch_val_f[1:0];
274 : assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
275 :
276 375 : logic ifc_fetch_uncacheable_bf; // The fetch request is uncacheable space. BF stage
277 3717960 : logic ifc_fetch_req_bf; // Fetch request. Comes with the address. BF stage
278 566 : logic ifc_fetch_req_bf_raw; // Fetch request without some qualifications. Used for clock-gating. BF stage
279 84 : logic ifc_iccm_access_bf; // This request is to the ICCM. Do not generate misses to the bus.
280 2 : logic ifc_region_acc_fault_bf; // Access fault. in ICCM region but offset is outside defined ICCM.
281 :
282 : // fetch control
283 : el2_ifu_ifc_ctl #(.pt(pt)) ifc (.*
284 : );
285 :
286 : // branch predictor
287 : if (pt.BTB_ENABLE==1) begin : bpred
288 : el2_ifu_bp_ctl #(.pt(pt)) bp (.*);
289 : end
290 : else begin : bpred
291 : assign ifu_bp_hit_taken_f = '0;
292 : // verif wires
293 : logic btb_wr_en_way0, btb_wr_en_way1,dec_tlu_error_wb;
294 : logic [16+pt.BTB_BTAG_SIZE:0] btb_wr_data;
295 : assign btb_wr_en_way0 = '0;
296 : assign btb_wr_en_way1 = '0;
297 : assign btb_wr_data = '0;
298 : assign dec_tlu_error_wb ='0;
299 : assign ifu_bp_inst_mask_f = 1'b1;
300 : end
301 :
302 :
303 :
304 : // aligner
305 :
306 : el2_ifu_aln_ctl #(.pt(pt)) aln (
307 : .*
308 : );
309 :
310 :
311 : // icache
312 : el2_ifu_mem_ctl #(.pt(pt)) mem_ctl
313 : (.*,
314 : .ic_data_f(ic_data_f[31:0])
315 : );
316 :
317 :
318 :
319 : // Performance debug info
320 : //
321 : //
322 : `ifdef DUMP_BTB_ON
323 : logic exu_mp_valid; // conditional branch mispredict
324 : logic exu_mp_way; // conditional branch mispredict
325 : logic exu_mp_ataken; // direction is actual taken
326 : logic exu_mp_boffset; // branch offsett
327 : logic exu_mp_pc4; // branch is a 4B inst
328 : logic exu_mp_call; // branch is a call inst
329 : logic exu_mp_ret; // branch is a ret inst
330 : logic exu_mp_ja; // branch is a jump always
331 : logic [1:0] exu_mp_hist; // new history
332 : logic [11:0] exu_mp_tgt; // target offset
333 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
334 :
335 : assign exu_mp_valid = exu_mp_pkt.misp; // conditional branch mispredict
336 : assign exu_mp_ataken = exu_mp_pkt.ataken; // direction is actual taken
337 : assign exu_mp_boffset = exu_mp_pkt.boffset; // branch offset
338 : assign exu_mp_pc4 = exu_mp_pkt.pc4; // branch is a 4B inst
339 : assign exu_mp_call = exu_mp_pkt.pcall; // branch is a call inst
340 : assign exu_mp_ret = exu_mp_pkt.pret; // branch is a ret inst
341 : assign exu_mp_ja = exu_mp_pkt.pja; // branch is a jump always
342 : assign exu_mp_way = exu_mp_pkt.way; // branch is a jump always
343 : assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0]; // new history
344 : assign exu_mp_tgt[11:0] = exu_mp_pkt.toffset[11:0] ; // target offset
345 : assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ; // BTB/BHT address
346 :
347 : logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_f;
348 : `define DEC `CPU_TOP.dec
349 : `define EXU `CPU_TOP.exu
350 : el2_btb_addr_hash f2hash(.pc(ifc_fetch_addr_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]), .hash(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));
351 : logic [31:0] mppc_ns, mppc;
352 : logic exu_flush_final_d1;
353 : assign mppc_ns[31:1] = `EXU.i0_flush_upper_x ? `EXU.exu_i0_pc_x : `EXU.dec_i0_pc_d;
354 : assign mppc_ns[0] = 1'b0;
355 : rvdff #(33) junk_ff (.*, .clk(active_clk), .din({mppc_ns[31:0], exu_flush_final}), .dout({mppc[31:0], exu_flush_final_d1}));
356 : logic tmp_bnk;
357 : assign tmp_bnk = bpred.bp.btb_sel_f[1];
358 :
359 : always @(negedge clk) begin
360 : if(`DEC.tlu.mcyclel[31:0] == 32'h0000_0010) begin
361 : $display("BTB_CONFIG: %d",pt.BTB_SIZE);
362 : `ifndef BP_NOGSHARE
363 : $display("BHT_CONFIG: %d gshare: 1",pt.BHT_SIZE);
364 : `else
365 : $display("BHT_CONFIG: %d gshare: 0",pt.BHT_SIZE);
366 : `endif
367 : $display("RS_CONFIG: %d", pt.RET_STACK_SIZE);
368 : end
369 : if(exu_flush_final_d1 & ~(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error) & (exu_mp_pkt.misp | exu_mp_pkt.ataken))
370 : $display("%7d BTB_MP : index: %0h bank: %0h call: %b ret: %b ataken: %b hist: %h valid: %b tag: %h targ: %h eghr: %b pred: %b ghr_index: %h brpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha, exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO], 1'b0, exu_mp_call, exu_mp_ret, exu_mp_ataken, exu_mp_hist[1:0], exu_mp_valid, exu_mp_btag[pt.BTB_BTAG_SIZE-1:0], {exu_flush_path_final[31:1], 1'b0}, exu_mp_eghr[pt.BHT_GHR_SIZE-1:0], exu_mp_valid, bpred.bp.bht_wr_addr0, mppc[31:0], exu_mp_pkt.way);
371 :
372 : for(int i = 0; i < 8; i++) begin
373 : if(ifu_bp_valid_f[i] & ifc_fetch_req_f)
374 : $display("%7d BTB_HIT : index: %0h bank: %0h call: %b ret: %b taken: %b strength: %b tag: %h targ: %0h ghr: %4b ghr_index: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],bpred.bp.btb_sel_f[1], bpred.bp.btb_rd_call_f, bpred.bp.btb_rd_ret_f, ifu_bp_hist1_f[tmp_bnk], ifu_bp_hist0_f[tmp_bnk], bpred.bp.fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0], {ifu_bp_btb_target_f[31:1], 1'b0}, bpred.bp.fghr[pt.BHT_GHR_SIZE-1:0], bpred.bp.bht_rd_addr_f, ifu_bp_way_f[tmp_bnk]);
375 : end
376 : if(dec_tlu_br0_r_pkt.valid & ~(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error))
377 : $display("%7d BTB_UPD0: ghr_index: %0h bank: %0h hist: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,bpred.bp.br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO],{dec_tlu_br0_r_pkt.middle}, dec_tlu_br0_r_pkt.hist, dec_tlu_br0_r_pkt.way);
378 :
379 : if(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error)
380 : $display("%7d BTB_ERR0: index: %0h bank: %0h start: %b rfpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,exu_i0_br_index_r[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],1'b0, dec_tlu_br0_r_pkt.br_start_error, {exu_flush_path_final[31:1], 1'b0}, dec_tlu_br0_r_pkt.way);
381 : end // always @ (negedge clk)
382 : function [1:0] encode4_2;
383 : input [3:0] in;
384 :
385 : encode4_2[1] = in[3] | in[2];
386 : encode4_2[0] = in[3] | in[1];
387 :
388 : endfunction
389 : `endif
390 : endmodule // el2_ifu
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