Project Full coverage report
Current view: Cores-VeeR-EL2—Cores-VeeR-EL2—design—ifu—el2_ifu.sv Coverage Hit Total
Test Date: 21-11-2024 Toggle 82.3% 121 147
Test: all Branch 0.0% 0 0

            Line data    Source code
       1              : //********************************************************************************
       2              : // SPDX-License-Identifier: Apache-2.0
       3              : // Copyright 2020 Western Digital Corporation or its affiliates.
       4              : //
       5              : // Licensed under the Apache License, Version 2.0 (the "License");
       6              : // you may not use this file except in compliance with the License.
       7              : // You may obtain a copy of the License at
       8              : //
       9              : // http://www.apache.org/licenses/LICENSE-2.0
      10              : //
      11              : // Unless required by applicable law or agreed to in writing, software
      12              : // distributed under the License is distributed on an "AS IS" BASIS,
      13              : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      14              : // See the License for the specific language governing permissions and
      15              : // limitations under the License.
      16              : //********************************************************************************
      17              : //********************************************************************************
      18              : // Function: Top level file for Icache, Fetch, Branch prediction & Aligner
      19              : // BFF -> F1 -> F2 -> A
      20              : //********************************************************************************
      21              : 
      22              : module el2_ifu
      23              : import el2_pkg::*;
      24              : #(
      25              : `include "el2_param.vh"
      26              :  )
      27              :   (
      28     69840565 :    input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
      29     69840565 :    input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
      30     69840565 :    input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
      31          338 :    input logic rst_l,                        // reset, active low
      32              : 
      33      6195679 :    input logic dec_i0_decode_d,              // Valid instruction at D and not blocked
      34              : 
      35       673974 :    input logic exu_flush_final, // flush, includes upper and lower
      36      6165278 :    input logic dec_tlu_i0_commit_cmt , // committed i0
      37            8 :    input logic dec_tlu_flush_err_wb , // flush due to parity error.
      38          232 :    input logic dec_tlu_flush_noredir_wb, // don't fetch, validated with exu_flush_final
      39       227566 :    input logic [31:1] exu_flush_path_final, // flush fetch address
      40              : 
      41            0 :    input logic [31:0]  dec_tlu_mrac_ff ,// Side_effect , cacheable for each region
      42        18868 :    input logic         dec_tlu_fence_i_wb, // fence.i, invalidate icache, validated with exu_flush_final
      43            2 :    input logic         dec_tlu_flush_leak_one_wb, // ignore bp for leak one fetches
      44              : 
      45            0 :    input logic                       dec_tlu_bpred_disable,     // disable all branch prediction
      46            8 :    input logic                       dec_tlu_core_ecc_disable,  // disable ecc checking and flagging
      47            0 :    input logic                       dec_tlu_force_halt,        // force halt
      48              : 
      49              :   //-------------------------- IFU AXI signals--------------------------
      50              :    // AXI Write Channels
      51              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
      52              :    /*verilator coverage_off*/
      53              :    output logic                            ifu_axi_awvalid,
      54              :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_awid,
      55              :    output logic [31:0]                     ifu_axi_awaddr,
      56              :    output logic [3:0]                      ifu_axi_awregion,
      57              :    output logic [7:0]                      ifu_axi_awlen,
      58              :    output logic [2:0]                      ifu_axi_awsize,
      59              :    output logic [1:0]                      ifu_axi_awburst,
      60              :    output logic                            ifu_axi_awlock,
      61              :    output logic [3:0]                      ifu_axi_awcache,
      62              :    output logic [2:0]                      ifu_axi_awprot,
      63              :    output logic [3:0]                      ifu_axi_awqos,
      64              : 
      65              :    output logic                            ifu_axi_wvalid,
      66              :    output logic [63:0]                     ifu_axi_wdata,
      67              :    output logic [7:0]                      ifu_axi_wstrb,
      68              :    output logic                            ifu_axi_wlast,
      69              : 
      70              :    output logic                            ifu_axi_bready,
      71              :    /*verilator coverage_on*/
      72              : 
      73              :    // AXI Read Channels
      74      5888189 :    output logic                            ifu_axi_arvalid,
      75     10350288 :    input  logic                            ifu_axi_arready,
      76      3584842 :    output logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_arid,
      77      2453330 :    output logic [31:0]                     ifu_axi_araddr,
      78          545 :    output logic [3:0]                      ifu_axi_arregion,
      79              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
      80              :    /*verilator coverage_off*/
      81              :    output logic [7:0]                      ifu_axi_arlen,
      82              :    output logic [2:0]                      ifu_axi_arsize,
      83              :    output logic [1:0]                      ifu_axi_arburst,
      84              :    output logic                            ifu_axi_arlock,
      85              :    output logic [3:0]                      ifu_axi_arcache,
      86              :    output logic [2:0]                      ifu_axi_arprot,
      87              :    output logic [3:0]                      ifu_axi_arqos,
      88              :    /*verilator coverage_on*/
      89              : 
      90     11795912 :    input  logic                            ifu_axi_rvalid,
      91              :    /* exclude signals that are tied to constant value in el2_ifu_mem_ctl.sv */
      92              :    /*verilator coverage_off*/
      93              :    output logic                            ifu_axi_rready,
      94              :    /*verilator coverage_on*/
      95      1180635 :    input  logic [pt.IFU_BUS_TAG-1:0]       ifu_axi_rid,
      96       984815 :    input  logic [63:0]                     ifu_axi_rdata,
      97           14 :    input  logic [1:0]                      ifu_axi_rresp,
      98              : 
      99          338 :    input  logic                      ifu_bus_clk_en,
     100              : 
     101           66 :    input  logic                      dma_iccm_req,
     102            0 :    input  logic [31:0]               dma_mem_addr,
     103            0 :    input  logic [2:0]                dma_mem_sz,
     104           22 :    input  logic                      dma_mem_write,
     105           12 :    input  logic [63:0]               dma_mem_wdata,
     106           12 :    input  logic [2:0]                dma_mem_tag,       //  DMA Buffer entry number
     107              : 
     108              : 
     109           26 :    input  logic                      dma_iccm_stall_any,
     110            4 :    output logic                      iccm_dma_ecc_error,
     111            0 :    output logic                      iccm_dma_rvalid,
     112            0 :    output logic [63:0]               iccm_dma_rdata,
     113           12 :    output logic [2:0]                iccm_dma_rtag,     //   Tag of the DMA req
     114       638114 :    output logic                      iccm_ready,
     115              : 
     116      6195679 :    output logic       ifu_pmu_instr_aligned,
     117       614908 :    output logic       ifu_pmu_fetch_stall,
     118            0 :    output logic       ifu_ic_error_start,     // has all of the I$ ecc/parity for data/tag
     119              : 
     120              : //   I$ & ITAG Ports
     121          489 :    output logic [31:1]               ic_rw_addr,         // Read/Write addresss to the Icache.
     122        10432 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_wr_en,           // Icache write enable, when filling the Icache.
     123       680948 :    output logic                      ic_rd_en,           // Icache read  enable.
     124              : 
     125       560245 :    output logic [pt.ICACHE_BANKS_WAY-1:0][70:0]               ic_wr_data,         // Data to fill to the Icache. With ECC
     126      2135818 :    input  logic [63:0]              ic_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
     127       231591 :    input  logic [70:0]              ic_debug_rd_data ,        // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
     128            0 :    input  logic [25:0]                     ictag_debug_rd_data,// Debug icache tag.
     129            0 :    output logic [70:0]               ic_debug_wr_data,   // Debug wr cache.
     130              : 
     131            0 :    output logic [70:0]               ifu_ic_debug_rd_data,
     132              : 
     133            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr,    //
     134            0 :    input  logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr,
     135      1737398 :    output logic [63:0]               ic_premux_data,     // Premux data to be muxed with each way of the Icache.
     136      5599841 :    output logic                      ic_sel_premux_data, // Select the premux data.
     137              : 
     138            0 :    output logic [pt.ICACHE_INDEX_HI:3]               ic_debug_addr,      // Read/Write addresss to the Icache.
     139           20 :    output logic                      ic_debug_rd_en,     // Icache debug rd
     140           20 :    output logic                      ic_debug_wr_en,     // Icache debug wr
     141            8 :    output logic                      ic_debug_tag_array, // Debug tag array
     142            0 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_debug_way,       // Debug way. Rd or Wr.
     143              : 
     144              : 
     145       255918 :    output logic [pt.ICACHE_NUM_WAYS-1:0]                ic_tag_valid,       // Valid bits when accessing the Icache. One valid bit per way. F2 stage
     146              : 
     147       109586 :    input  logic [pt.ICACHE_NUM_WAYS-1:0]                ic_rd_hit,          // Compare hits from Icache tags. Per way.  F2 stage
     148            0 :    input  logic                      ic_tag_perr,        // Icache Tag parity error
     149              : 
     150              : 
     151              :    // ICCM ports
     152       160236 :    output logic [pt.ICCM_BITS-1:1]               iccm_rw_addr,       // ICCM read/write address.
     153           74 :    output logic                      iccm_wren,          // ICCM write enable (through the DMA)
     154       133206 :    output logic                      iccm_rden,          // ICCM read enable.
     155           14 :    output logic [77:0]               iccm_wr_data,       // ICCM write data.
     156            0 :    output logic [2:0]                iccm_wr_size,       // ICCM write location within DW.
     157              : 
     158       136532 :    input  logic [63:0]               iccm_rd_data,       // Data read from ICCM.
     159       161264 :    input  logic [77:0]               iccm_rd_data_ecc,   // Data + ECC read from ICCM.
     160              : 
     161              :    // ICCM ECC status
     162            0 :    output logic                      ifu_iccm_dma_rd_ecc_single_err, // This fetch has a single ICCM DMA ECC error.
     163            8 :    output logic                      ifu_iccm_rd_ecc_single_err,     // This fetch has a single ICCM ECC error.
     164            4 :    output logic                      ifu_iccm_rd_ecc_double_err,     // This fetch has a double ICCM ECC error.
     165              : 
     166              : // Perf counter sigs
     167      5888394 :    output logic       ifu_pmu_ic_miss, // ic miss
     168       745248 :    output logic       ifu_pmu_ic_hit, // ic hit
     169            8 :    output logic       ifu_pmu_bus_error, // iside bus error
     170      4461583 :    output logic       ifu_pmu_bus_busy,  // iside bus busy
     171     10349957 :    output logic       ifu_pmu_bus_trxn, // iside bus transactions
     172              : 
     173              : 
     174          206 :    output logic       ifu_i0_icaf,         // Instruction 0 access fault. From Aligner to Decode
     175          274 :    output logic [1:0] ifu_i0_icaf_type, // Instruction 0 access fault type
     176              : 
     177      6010401 :    output logic  ifu_i0_valid,        // Instruction 0 valid. From Aligner to Decode
     178           86 :    output logic  ifu_i0_icaf_second,  // Instruction 0 has access fault on second 2B of 4B inst
     179            2 :    output logic  ifu_i0_dbecc,        // Instruction 0 has double bit ecc error
     180            0 :    output logic  iccm_dma_sb_error,   // Single Bit ECC error from a DMA access
     181       468702 :    output logic[31:0] ifu_i0_instr,   // Instruction 0 . From Aligner to Decode
     182         1321 :    output logic[31:1] ifu_i0_pc,      // Instruction 0 pc. From Aligner to Decode
     183      5770511 :    output logic ifu_i0_pc4,           // Instruction 0 is 4 byte. From Aligner to Decode
     184              : 
     185      5887400 :    output logic ifu_miss_state_idle,   // There is no outstanding miss. Cache miss state is idle.
     186              : 
     187       206055 :    output el2_br_pkt_t i0_brp,           // Instruction 0 branch packet. From Aligner to Decode
     188       651059 :    output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
     189       628591 :    output logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
     190        21223 :    output logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
     191            0 :    output logic [$clog2(pt.BTB_SIZE)-1:0]         ifu_i0_fa_index,          // Fully associt btb index
     192              : 
     193        34486 :    input el2_predict_pkt_t  exu_mp_pkt, // mispredict packet
     194       300064 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // execute ghr
     195       378616 :    input logic [pt.BHT_GHR_SIZE-1:0]  exu_mp_fghr,                    // Mispredict fghr
     196       196152 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  exu_mp_index,         // Mispredict index
     197       115620 :    input logic [pt.BTB_BTAG_SIZE-1:0]  exu_mp_btag,                   // Mispredict btag
     198              : 
     199       782023 :    input el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // slot0 update/error pkt
     200       366738 :    input logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // fghr to bp
     201       187560 :    input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // bp index
     202            0 :    input logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
     203              : 
     204        59220 :    input dec_tlu_flush_lower_wb,
     205              : 
     206      1427480 :    output logic [15:0] ifu_i0_cinst,
     207              : 
     208          443 :     output logic [31:1] ifu_pmp_addr,
     209          110 :     input  logic        ifu_pmp_error,
     210              : 
     211              : /// Icache debug
     212            0 :    input  el2_cache_debug_pkt_t        dec_tlu_ic_diag_pkt ,
     213           20 :    output logic                    ifu_ic_debug_rd_data_valid,
     214            8 :    output logic                                iccm_buf_correct_ecc,
     215            8 :    output logic                                iccm_correction_state,
     216              : 
     217              :    // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
     218              :    /*verilator coverage_off*/
     219              :    input logic scan_mode
     220              :    /*verilator coverage_on*/
     221              :    );
     222              : 
     223              :    localparam TAGWIDTH = 2 ;
     224              :    localparam IDWIDTH  = 2 ;
     225              : 
     226       256964 :    logic                   ifu_fb_consume1, ifu_fb_consume2;
     227          443 :    logic [31:1]            ifc_fetch_addr_f;
     228          443 :    logic [31:1]            ifc_fetch_addr_bf;
     229              :   assign ifu_pmp_addr = ifc_fetch_addr_bf;
     230              : 
     231      6333593 :    logic [1:0]   ifu_fetch_val;  // valids on a 2B boundary, left justified [7] implies valid fetch
     232          443 :    logic [31:1]  ifu_fetch_pc;   // starting pc of fetch
     233              : 
     234            0 :    logic iccm_rd_ecc_single_err, iccm_dma_rd_ecc_single_err, ic_error_start;
     235              :    assign ifu_iccm_dma_rd_ecc_single_err = iccm_dma_rd_ecc_single_err;
     236              :    assign ifu_iccm_rd_ecc_single_err = iccm_rd_ecc_single_err;
     237              :    assign ifu_ic_error_start = ic_error_start;
     238              : 
     239              : 
     240      2632580 :    logic        ic_write_stall;
     241           16 :    logic        ic_dma_active;
     242       640547 :    logic        ifc_dma_access_ok;
     243          180 :    logic [1:0]  ic_access_fault_f;
     244          172 :    logic [1:0]  ic_access_fault_type_f;
     245      5908764 :    logic        ifu_ic_mb_empty;
     246              : 
     247      6782653 :    logic ic_hit_f;
     248              : 
     249      2374031 :    logic [1:0] ifu_bp_way_f; // way indication; right justified
     250      3170544 :    logic       ifu_bp_hit_taken_f; // kill next fetch; taken target found
     251       518479 :    logic [31:1] ifu_bp_btb_target_f; //  predicted target PC
     252      2404958 :    logic        ifu_bp_inst_mask_f; // tell ic which valids to kill because of a taken branch; right justified
     253      2024478 :    logic [1:0]  ifu_bp_hist1_f; // history counters for all 4 potential branches; right justified
     254      1823494 :    logic [1:0]  ifu_bp_hist0_f; // history counters for all 4 potential branches; right justified
     255      2176718 :    logic [11:0] ifu_bp_poffset_f; // predicted target
     256        70446 :    logic [1:0]  ifu_bp_ret_f; // predicted ret ; right justified
     257       408365 :    logic [1:0]  ifu_bp_pc4_f; // pc4 indication; right justified
     258       956919 :    logic [1:0]  ifu_bp_valid_f; // branch valid, right justified
     259       376431 :    logic [pt.BHT_GHR_SIZE-1:0] ifu_bp_fghr_f;
     260            0 :    logic [1:0] [$clog2(pt.BTB_SIZE)-1:0] ifu_bp_fa_index_f;
     261              : 
     262              : 
     263      6333593 :    logic [1:0]   ic_fetch_val_f;
     264      2166762 :    logic [31:0] ic_data_f;
     265      2166762 :    logic [31:0] ifu_fetch_data_f;
     266      3714536 :    logic ifc_fetch_req_f;
     267            0 :    logic ifc_fetch_req_f_raw;
     268            0 :    logic iccm_dma_rd_ecc_double_err;
     269            4 :    logic [1:0] iccm_rd_ecc_double_err;  // This fetch has an iccm double error.
     270              :    assign ifu_iccm_rd_ecc_double_err = |iccm_rd_ecc_double_err || |iccm_dma_rd_ecc_double_err;
     271              : 
     272            8 :    logic ifu_async_error_start;
     273              : 
     274              : 
     275              :    assign ifu_fetch_data_f[31:0] = ic_data_f[31:0];
     276              :    assign ifu_fetch_val[1:0] = ic_fetch_val_f[1:0];
     277              :    assign ifu_fetch_pc[31:1] = ifc_fetch_addr_f[31:1];
     278              : 
     279          375 :  logic                       ifc_fetch_uncacheable_bf;      // The fetch request is uncacheable space. BF stage
     280      3714574 :  logic                       ifc_fetch_req_bf;              // Fetch request. Comes with the address.  BF stage
     281          568 :  logic                       ifc_fetch_req_bf_raw;          // Fetch request without some qualifications. Used for clock-gating. BF stage
     282           84 :  logic                       ifc_iccm_access_bf;            // This request is to the ICCM. Do not generate misses to the bus.
     283            2 :  logic                       ifc_region_acc_fault_bf;       // Access fault. in ICCM region but offset is outside defined ICCM.
     284              : 
     285              :    // fetch control
     286              :    el2_ifu_ifc_ctl #(.pt(pt)) ifc (.*
     287              :                     );
     288              : 
     289              :    // branch predictor
     290              :    if (pt.BTB_ENABLE==1) begin  : bpred
     291              :       el2_ifu_bp_ctl #(.pt(pt)) bp (.*);
     292              :    end
     293              :    else begin : bpred
     294              :       assign ifu_bp_hit_taken_f = '0;
     295              :       // verif wires
     296              :       logic btb_wr_en_way0, btb_wr_en_way1,dec_tlu_error_wb;
     297              :       logic [16+pt.BTB_BTAG_SIZE:0] btb_wr_data;
     298              :       assign btb_wr_en_way0 = '0;
     299              :       assign btb_wr_en_way1 = '0;
     300              :       assign btb_wr_data = '0;
     301              :       assign dec_tlu_error_wb ='0;
     302              :       assign ifu_bp_inst_mask_f = 1'b1;
     303              :    end
     304              : 
     305              : 
     306              : 
     307              :    // aligner
     308              : 
     309              :    el2_ifu_aln_ctl #(.pt(pt)) aln (
     310              :                                     .*
     311              :                                     );
     312              : 
     313              : 
     314              :    // icache
     315              :    el2_ifu_mem_ctl #(.pt(pt)) mem_ctl
     316              :      (.*,
     317              :       .ic_data_f(ic_data_f[31:0])
     318              :       );
     319              : 
     320              : 
     321              : 
     322              :    // Performance debug info
     323              :    //
     324              :    //
     325              : `ifdef DUMP_BTB_ON
     326              :    logic              exu_mp_valid; // conditional branch mispredict
     327              :    logic exu_mp_way; // conditional branch mispredict
     328              :    logic exu_mp_ataken; // direction is actual taken
     329              :    logic exu_mp_boffset; // branch offsett
     330              :    logic exu_mp_pc4; // branch is a 4B inst
     331              :    logic exu_mp_call; // branch is a call inst
     332              :    logic exu_mp_ret; // branch is a ret inst
     333              :    logic exu_mp_ja; // branch is a jump always
     334              :    logic [1:0] exu_mp_hist; // new history
     335              :    logic [11:0] exu_mp_tgt; // target offset
     336              :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_addr; // BTB/BHT address
     337              : 
     338              :    assign exu_mp_valid = exu_mp_pkt.misp; // conditional branch mispredict
     339              :    assign exu_mp_ataken = exu_mp_pkt.ataken;  // direction is actual taken
     340              :    assign exu_mp_boffset = exu_mp_pkt.boffset;  // branch offset
     341              :    assign exu_mp_pc4 = exu_mp_pkt.pc4;  // branch is a 4B inst
     342              :    assign exu_mp_call = exu_mp_pkt.pcall;  // branch is a call inst
     343              :    assign exu_mp_ret = exu_mp_pkt.pret;  // branch is a ret inst
     344              :    assign exu_mp_ja = exu_mp_pkt.pja;  // branch is a jump always
     345              :    assign exu_mp_way = exu_mp_pkt.way;  // branch is a jump always
     346              :    assign exu_mp_hist[1:0] = exu_mp_pkt.hist[1:0];  // new history
     347              :    assign exu_mp_tgt[11:0]  = exu_mp_pkt.toffset[11:0] ;  // target offset
     348              :    assign exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]  = exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ;  // BTB/BHT address
     349              : 
     350              :    logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] btb_rd_addr_f;
     351              :  `define DEC `CPU_TOP.dec
     352              :  `define EXU `CPU_TOP.exu
     353              :    el2_btb_addr_hash f2hash(.pc(ifc_fetch_addr_f[pt.BTB_INDEX3_HI:pt.BTB_INDEX1_LO]), .hash(btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]));
     354              :    logic [31:0] mppc_ns, mppc;
     355              :    logic        exu_flush_final_d1;
     356              :    assign mppc_ns[31:1] = `EXU.i0_flush_upper_x ? `EXU.exu_i0_pc_x : `EXU.dec_i0_pc_d;
     357              :    assign mppc_ns[0] = 1'b0;
     358              :    rvdff #(33)  junk_ff (.*, .clk(active_clk), .din({mppc_ns[31:0], exu_flush_final}), .dout({mppc[31:0], exu_flush_final_d1}));
     359              :    logic  tmp_bnk;
     360              :    assign tmp_bnk = bpred.bp.btb_sel_f[1];
     361              : 
     362              :    always @(negedge clk) begin
     363              :       if(`DEC.tlu.mcyclel[31:0] == 32'h0000_0010) begin
     364              :          $display("BTB_CONFIG: %d",pt.BTB_SIZE);
     365              :          `ifndef BP_NOGSHARE
     366              :          $display("BHT_CONFIG: %d gshare: 1",pt.BHT_SIZE);
     367              :          `else
     368              :          $display("BHT_CONFIG: %d gshare: 0",pt.BHT_SIZE);
     369              :          `endif
     370              :          $display("RS_CONFIG: %d", pt.RET_STACK_SIZE);
     371              :       end
     372              :        if(exu_flush_final_d1 & ~(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error) & (exu_mp_pkt.misp | exu_mp_pkt.ataken))
     373              :          $display("%7d BTB_MP  : index: %0h bank: %0h call: %b ret: %b ataken: %b hist: %h valid: %b tag: %h targ: %h eghr: %b pred: %b ghr_index: %h brpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha, exu_mp_addr[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO], 1'b0, exu_mp_call, exu_mp_ret, exu_mp_ataken, exu_mp_hist[1:0], exu_mp_valid, exu_mp_btag[pt.BTB_BTAG_SIZE-1:0], {exu_flush_path_final[31:1], 1'b0}, exu_mp_eghr[pt.BHT_GHR_SIZE-1:0], exu_mp_valid, bpred.bp.bht_wr_addr0, mppc[31:0], exu_mp_pkt.way);
     374              : 
     375              :      for(int i = 0; i < 8; i++) begin
     376              :       if(ifu_bp_valid_f[i] & ifc_fetch_req_f)
     377              :         $display("%7d BTB_HIT : index: %0h bank: %0h call: %b ret: %b taken: %b strength: %b tag: %h targ: %0h ghr: %4b ghr_index: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,btb_rd_addr_f[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],bpred.bp.btb_sel_f[1], bpred.bp.btb_rd_call_f, bpred.bp.btb_rd_ret_f, ifu_bp_hist1_f[tmp_bnk], ifu_bp_hist0_f[tmp_bnk], bpred.bp.fetch_rd_tag_f[pt.BTB_BTAG_SIZE-1:0], {ifu_bp_btb_target_f[31:1], 1'b0}, bpred.bp.fghr[pt.BHT_GHR_SIZE-1:0], bpred.bp.bht_rd_addr_f, ifu_bp_way_f[tmp_bnk]);
     378              :      end
     379              :       if(dec_tlu_br0_r_pkt.valid & ~(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error))
     380              :         $display("%7d BTB_UPD0: ghr_index: %0h bank: %0h hist: %h  way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,bpred.bp.br0_hashed_wb[pt.BHT_ADDR_HI:pt.BHT_ADDR_LO],{dec_tlu_br0_r_pkt.middle}, dec_tlu_br0_r_pkt.hist, dec_tlu_br0_r_pkt.way);
     381              : 
     382              :       if(dec_tlu_br0_r_pkt.br_error | dec_tlu_br0_r_pkt.br_start_error)
     383              :         $display("%7d BTB_ERR0: index: %0h bank: %0h start: %b rfpc: %h way: %h", `DEC.tlu.mcyclel[31:0]+32'ha,exu_i0_br_index_r[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],1'b0, dec_tlu_br0_r_pkt.br_start_error, {exu_flush_path_final[31:1], 1'b0}, dec_tlu_br0_r_pkt.way);
     384              :    end // always @ (negedge clk)
     385              :       function [1:0] encode4_2;
     386              :       input [3:0] in;
     387              : 
     388              :       encode4_2[1] = in[3] | in[2];
     389              :       encode4_2[0] = in[3] | in[1];
     390              : 
     391              :    endfunction
     392              : `endif
     393              : endmodule // el2_ifu