Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 :
17 : module el2_exu
18 : import el2_pkg::*;
19 : #(
20 : `include "el2_param.vh"
21 : )
22 : (
23 69890155 : input logic clk, // Top level clock
24 338 : input logic rst_l, // Reset
25 0 : input logic scan_mode, // Scan control
26 :
27 6202681 : input logic [1:0] dec_data_en, // Clock enable {x,r}, one cycle pulse
28 5996949 : input logic [1:0] dec_ctl_en, // Clock enable {x,r}, two cycle pulse
29 120 : input logic [31:0] dbg_cmd_wrdata, // Debug data to primary I0 RS1
30 1460 : input el2_alu_pkt_t i0_ap, // DEC alu {valid,predecodes}
31 :
32 56 : input logic dec_debug_wdata_rs1_d, // Debug select to primary I0 RS1
33 :
34 506495 : input el2_predict_pkt_t dec_i0_predict_p_d, // DEC branch predict packet
35 631071 : input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // DEC predict fghr
36 651206 : input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index
37 21223 : input logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // DEC predict branch tag
38 :
39 45891 : input logic [31:0] lsu_result_m, // Load result M-stage
40 71610 : input logic [31:0] lsu_nonblock_load_data, // nonblock load data
41 5141434 : input logic dec_i0_rs1_en_d, // Qualify GPR RS1 data
42 3573430 : input logic dec_i0_rs2_en_d, // Qualify GPR RS2 data
43 407928 : input logic [31:0] gpr_i0_rs1_d, // DEC data gpr
44 598866 : input logic [31:0] gpr_i0_rs2_d, // DEC data gpr
45 2170403 : input logic [31:0] dec_i0_immed_d, // DEC data immediate
46 314093 : input logic [31:0] dec_i0_result_r, // DEC result in R-stage
47 123668 : input logic [12:1] dec_i0_br_immed_d, // Branch immediate
48 5414203 : input logic dec_i0_alu_decode_d, // Valid to X-stage ALU
49 3885938 : input logic dec_i0_branch_d, // Branch in D-stage
50 555855 : input logic dec_i0_select_pc_d, // PC select to RS1
51 1322 : input logic [31:1] dec_i0_pc_d, // Instruction PC
52 80590 : input logic [3:0] dec_i0_rs1_bypass_en_d, // DEC bypass select 1 - X-stage, 0 - dec bypass data
53 8620 : input logic [3:0] dec_i0_rs2_bypass_en_d, // DEC bypass select 1 - X-stage, 0 - dec bypass data
54 77236 : input logic dec_csr_ren_d, // CSR read select
55 8786 : input logic [31:0] dec_csr_rddata_d, // CSR read data
56 :
57 5496598 : input logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands
58 0 : input el2_mul_pkt_t mul_p, // DEC {valid, operand signs, low, operand bypass}
59 78134 : input el2_div_pkt_t div_p, // DEC {valid, unsigned, rem}
60 2628 : input logic dec_div_cancel, // Cancel the divide operation
61 :
62 139118 : input logic [31:1] pred_correct_npc_x, // DEC NPC for correctly predicted branch
63 :
64 59238 : input logic dec_tlu_flush_lower_r, // Flush divide and secondary ALUs
65 24770 : input logic [31:1] dec_tlu_flush_path_r, // Redirect target
66 :
67 :
68 0 : input logic dec_extint_stall, // External stall mux select
69 0 : input logic [31:2] dec_tlu_meihap, // External stall mux data
70 :
71 :
72 413433 : output logic [31:0] exu_lsu_rs1_d, // LSU operand
73 81510 : output logic [31:0] exu_lsu_rs2_d, // LSU operand
74 :
75 674202 : output logic exu_flush_final, // Pipe is being flushed this cycle
76 227634 : output logic [31:1] exu_flush_path_final, // Target for the oldest flush source
77 :
78 614723 : output logic [31:0] exu_i0_result_x, // Primary ALU result to DEC
79 340 : output logic [31:1] exu_i0_pc_x, // Primary PC result to DEC
80 3978 : output logic [31:0] exu_csr_rs1_x, // RS1 source for a CSR instruction
81 :
82 345 : output logic [31:1] exu_npc_r, // Divide NPC
83 2722695 : output logic [1:0] exu_i0_br_hist_r, // to DEC I0 branch history
84 26468 : output logic exu_i0_br_error_r, // to DEC I0 branch error
85 9608 : output logic exu_i0_br_start_error_r, // to DEC I0 branch start error
86 187591 : output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // to DEC I0 branch index
87 3014311 : output logic exu_i0_br_valid_r, // to DEC I0 branch valid
88 410724 : output logic exu_i0_br_mp_r, // to DEC I0 branch mispredict
89 2382215 : output logic exu_i0_br_middle_r, // to DEC I0 branch middle
90 367244 : output logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // to DEC I0 branch fghr
91 2111116 : output logic exu_i0_br_way_r, // to DEC I0 branch way
92 :
93 34482 : output el2_predict_pkt_t exu_mp_pkt, // Mispredict branch packet
94 300192 : output logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // Mispredict global history
95 379120 : output logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr, // Mispredict fghr
96 196224 : output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index, // Mispredict index
97 115620 : output logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag, // Mispredict btag
98 :
99 :
100 410724 : output logic exu_pmu_i0_br_misp, // to PMU - I0 E4 branch mispredict
101 2912139 : output logic exu_pmu_i0_br_ataken, // to PMU - I0 E4 taken
102 3496082 : output logic exu_pmu_i0_pc4, // to PMU - I0 E4 PC
103 :
104 :
105 24784 : output logic [31:0] exu_div_result, // Divide result
106 156860 : output logic exu_div_wren // Divide write enable to GPR
107 : );
108 :
109 :
110 :
111 :
112 62185 : logic [31:0] i0_rs1_bypass_data_d;
113 13156 : logic [31:0] i0_rs2_bypass_data_d;
114 909754 : logic i0_rs1_bypass_en_d;
115 469647 : logic i0_rs2_bypass_en_d;
116 417192 : logic [31:0] i0_rs1_d, i0_rs2_d;
117 357851 : logic [31:0] muldiv_rs1_d;
118 139111 : logic [31:1] pred_correct_npc_r;
119 2964805 : logic i0_pred_correct_upper_r;
120 345 : logic [31:1] i0_flush_path_upper_r;
121 170323 : logic x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
122 5996949 : logic x_ctl_en, r_ctl_en;
123 :
124 382278 : logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
125 382278 : logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
126 3101064 : logic i0_taken_d;
127 3101036 : logic i0_taken_x;
128 3128972 : logic i0_valid_d;
129 3128944 : logic i0_valid_x;
130 379120 : logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
131 :
132 31508 : el2_predict_pkt_t final_predict_mp;
133 506495 : el2_predict_pkt_t i0_predict_newp_d;
134 :
135 0 : logic flush_in_d;
136 568387 : logic [31:0] alu_result_x;
137 :
138 250948 : logic mul_valid_x;
139 17509 : logic [31:0] mul_result_x;
140 :
141 350199 : el2_predict_pkt_t i0_pp_r;
142 :
143 615012 : logic i0_flush_upper_d;
144 2492 : logic [31:1] i0_flush_path_d;
145 506495 : el2_predict_pkt_t i0_predict_p_d;
146 2964840 : logic i0_pred_correct_upper_d;
147 :
148 615012 : logic i0_flush_upper_x;
149 345 : logic [31:1] i0_flush_path_x;
150 350199 : el2_predict_pkt_t i0_predict_p_x;
151 2964815 : logic i0_pred_correct_upper_x;
152 3885910 : logic i0_branch_x;
153 :
154 : localparam PREDPIPESIZE = pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1+pt.BHT_GHR_SIZE+pt.BTB_BTAG_SIZE;
155 55511 : logic [PREDPIPESIZE-1:0] predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
156 :
157 :
158 :
159 :
160 : rvdffpcie #(31) i_flush_path_x_ff (.*, .clk(clk), .en ( x_data_en ), .din ( i0_flush_path_d[31:1] ), .dout( i0_flush_path_x[31:1] ) );
161 : rvdffe #(32) i_csr_rs1_x_ff (.*, .clk(clk), .en ( x_data_en_q1 ), .din ( i0_rs1_d[31:0] ), .dout( exu_csr_rs1_x[31:0] ) );
162 : rvdffppe #($bits(el2_predict_pkt_t)) i_predictpacket_x_ff (.*, .clk(clk), .en ( x_data_en ), .din ( i0_predict_p_d ), .dout( i0_predict_p_x ) );
163 : rvdffe #(PREDPIPESIZE) i_predpipe_x_ff (.*, .clk(clk), .en ( x_data_en_q2 ), .din ( predpipe_d ), .dout( predpipe_x ) );
164 : rvdffe #(PREDPIPESIZE) i_predpipe_r_ff (.*, .clk(clk), .en ( r_data_en_q2 ), .din ( predpipe_x ), .dout( predpipe_r ) );
165 :
166 : rvdffe #(4+pt.BHT_GHR_SIZE) i_x_ff (.*, .clk(clk), .en ( x_ctl_en ), .din ({i0_valid_d,i0_taken_d,i0_flush_upper_d,i0_pred_correct_upper_d,ghr_x_ns[pt.BHT_GHR_SIZE-1:0]} ),
167 : .dout({i0_valid_x,i0_taken_x,i0_flush_upper_x,i0_pred_correct_upper_x,ghr_x[pt.BHT_GHR_SIZE-1:0]} ) );
168 :
169 : rvdffppe #($bits(el2_predict_pkt_t)+1) i_r_ff0 (.*, .clk(clk), .en ( r_ctl_en ), .din ({i0_pred_correct_upper_x, i0_predict_p_x}),
170 : .dout({i0_pred_correct_upper_r, i0_pp_r }) );
171 :
172 : rvdffpcie #(31) i_flush_r_ff (.*, .clk(clk), .en ( r_data_en ), .din ( i0_flush_path_x[31:1] ), .dout( i0_flush_path_upper_r[31:1]) );
173 : rvdffpcie #(31) i_npc_r_ff (.*, .clk(clk), .en ( r_data_en ), .din ( pred_correct_npc_x[31:1] ), .dout( pred_correct_npc_r[31:1] ) );
174 :
175 : rvdffie #(pt.BHT_GHR_SIZE+2,1) i_misc_ff (.*, .clk(clk), .din ({ghr_d_ns[pt.BHT_GHR_SIZE-1:0], mul_p.valid, dec_i0_branch_d}),
176 : .dout({ghr_d[pt.BHT_GHR_SIZE-1:0] , mul_valid_x, i0_branch_x}) );
177 :
178 :
179 :
180 :
181 :
182 : assign predpipe_d[PREDPIPESIZE-1:0]
183 : = {i0_predict_fghr_d, i0_predict_index_d, i0_predict_btag_d};
184 :
185 :
186 : assign i0_rs1_bypass_en_d = dec_i0_rs1_bypass_en_d[0] | dec_i0_rs1_bypass_en_d[1] | dec_i0_rs1_bypass_en_d[2] | dec_i0_rs1_bypass_en_d[3];
187 : assign i0_rs2_bypass_en_d = dec_i0_rs2_bypass_en_d[0] | dec_i0_rs2_bypass_en_d[1] | dec_i0_rs2_bypass_en_d[2] | dec_i0_rs2_bypass_en_d[3];
188 :
189 : assign i0_rs1_bypass_data_d[31:0]=({32{dec_i0_rs1_bypass_en_d[0]}} & dec_i0_result_r[31:0] ) |
190 : ({32{dec_i0_rs1_bypass_en_d[1]}} & lsu_result_m[31:0] ) |
191 : ({32{dec_i0_rs1_bypass_en_d[2]}} & exu_i0_result_x[31:0] ) |
192 : ({32{dec_i0_rs1_bypass_en_d[3]}} & lsu_nonblock_load_data[31:0]);
193 :
194 : assign i0_rs2_bypass_data_d[31:0]=({32{dec_i0_rs2_bypass_en_d[0]}} & dec_i0_result_r[31:0] ) |
195 : ({32{dec_i0_rs2_bypass_en_d[1]}} & lsu_result_m[31:0] ) |
196 : ({32{dec_i0_rs2_bypass_en_d[2]}} & exu_i0_result_x[31:0] ) |
197 : ({32{dec_i0_rs2_bypass_en_d[3]}} & lsu_nonblock_load_data[31:0]);
198 :
199 :
200 : assign i0_rs1_d[31:0] = ({32{ i0_rs1_bypass_en_d }} & i0_rs1_bypass_data_d[31:0]) |
201 : ({32{~i0_rs1_bypass_en_d & dec_i0_select_pc_d }} & {dec_i0_pc_d[31:1],1'b0} ) | // for jal's
202 : ({32{~i0_rs1_bypass_en_d & dec_debug_wdata_rs1_d }} & dbg_cmd_wrdata[31:0] ) |
203 : ({32{~i0_rs1_bypass_en_d & ~dec_debug_wdata_rs1_d & dec_i0_rs1_en_d}} & gpr_i0_rs1_d[31:0] );
204 :
205 : assign i0_rs2_d[31:0] = ({32{~i0_rs2_bypass_en_d & dec_i0_rs2_en_d}} & gpr_i0_rs2_d[31:0] ) |
206 : ({32{~i0_rs2_bypass_en_d }} & dec_i0_immed_d[31:0] ) |
207 : ({32{ i0_rs2_bypass_en_d }} & i0_rs2_bypass_data_d[31:0]);
208 :
209 :
210 : assign exu_lsu_rs1_d[31:0] = ({32{~i0_rs1_bypass_en_d & ~dec_extint_stall & dec_i0_rs1_en_d & dec_qual_lsu_d}} & gpr_i0_rs1_d[31:0] ) |
211 : ({32{ i0_rs1_bypass_en_d & ~dec_extint_stall & dec_qual_lsu_d}} & i0_rs1_bypass_data_d[31:0]) |
212 : ({32{ dec_extint_stall & dec_qual_lsu_d}} & {dec_tlu_meihap[31:2],2'b0});
213 :
214 : assign exu_lsu_rs2_d[31:0] = ({32{~i0_rs2_bypass_en_d & ~dec_extint_stall & dec_i0_rs2_en_d & dec_qual_lsu_d}} & gpr_i0_rs2_d[31:0] ) |
215 : ({32{ i0_rs2_bypass_en_d & ~dec_extint_stall & dec_qual_lsu_d}} & i0_rs2_bypass_data_d[31:0]);
216 :
217 :
218 : assign muldiv_rs1_d[31:0] = ({32{~i0_rs1_bypass_en_d & dec_i0_rs1_en_d}} & gpr_i0_rs1_d[31:0] ) |
219 : ({32{ i0_rs1_bypass_en_d }} & i0_rs1_bypass_data_d[31:0]);
220 :
221 :
222 : assign x_data_en = dec_data_en[1];
223 : assign x_data_en_q1 = dec_data_en[1] & dec_csr_ren_d;
224 : assign x_data_en_q2 = dec_data_en[1] & dec_i0_branch_d;
225 : assign r_data_en = dec_data_en[0];
226 : assign r_data_en_q2 = dec_data_en[0] & i0_branch_x;
227 : assign x_ctl_en = dec_ctl_en[1];
228 : assign r_ctl_en = dec_ctl_en[0];
229 :
230 :
231 :
232 :
233 : el2_exu_alu_ctl #(.pt(pt)) i_alu (.*,
234 : .enable ( x_data_en ), // I
235 : .pp_in ( i0_predict_newp_d ), // I
236 : .valid_in ( dec_i0_alu_decode_d ), // I
237 : .flush_upper_x ( i0_flush_upper_x ), // I
238 : .flush_lower_r ( dec_tlu_flush_lower_r ), // I
239 : .a_in ( i0_rs1_d[31:0] ), // I
240 : .b_in ( i0_rs2_d[31:0] ), // I
241 : .pc_in ( dec_i0_pc_d[31:1] ), // I
242 : .brimm_in ( dec_i0_br_immed_d[12:1] ), // I
243 : .ap ( i0_ap ), // I
244 : .csr_ren_in ( dec_csr_ren_d ), // I
245 : .csr_rddata_in ( dec_csr_rddata_d[31:0] ), // I
246 : .result_ff ( alu_result_x[31:0] ), // O
247 : .flush_upper_out ( i0_flush_upper_d ), // O
248 : .flush_final_out ( exu_flush_final ), // O
249 : .flush_path_out ( i0_flush_path_d[31:1] ), // O
250 : .predict_p_out ( i0_predict_p_d ), // O
251 : .pred_correct_out ( i0_pred_correct_upper_d ), // O
252 : .pc_ff ( exu_i0_pc_x[31:1] )); // O
253 :
254 :
255 :
256 : el2_exu_mul_ctl #(.pt(pt)) i_mul (.*,
257 : .mul_p ( mul_p & {$bits(el2_mul_pkt_t){mul_p.valid}} ), // I
258 : .rs1_in ( muldiv_rs1_d[31:0] & {32{mul_p.valid}} ), // I
259 : .rs2_in ( i0_rs2_d[31:0] & {32{mul_p.valid}} ), // I
260 : .result_x ( mul_result_x[31:0] )); // O
261 :
262 :
263 :
264 : el2_exu_div_ctl #(.pt(pt)) i_div (.*,
265 : .cancel ( dec_div_cancel ), // I
266 : .dp ( div_p ), // I
267 : .dividend ( muldiv_rs1_d[31:0] ), // I
268 : .divisor ( i0_rs2_d[31:0] ), // I
269 : .finish_dly ( exu_div_wren ), // O
270 : .out ( exu_div_result[31:0] )); // O
271 :
272 :
273 :
274 : assign exu_i0_result_x[31:0] = (mul_valid_x) ? mul_result_x[31:0] : alu_result_x[31:0];
275 :
276 :
277 :
278 :
279 339 : always_comb begin
280 339 : i0_predict_newp_d = dec_i0_predict_p_d;
281 339 : i0_predict_newp_d.boffset = dec_i0_pc_d[1]; // from the start of inst
282 : end
283 :
284 :
285 : assign exu_pmu_i0_br_misp = i0_pp_r.misp;
286 : assign exu_pmu_i0_br_ataken = i0_pp_r.ataken;
287 : assign exu_pmu_i0_pc4 = i0_pp_r.pc4;
288 :
289 :
290 : assign i0_valid_d = i0_predict_p_d.valid & dec_i0_alu_decode_d & ~dec_tlu_flush_lower_r;
291 : assign i0_taken_d = (i0_predict_p_d.ataken & dec_i0_alu_decode_d);
292 :
293 : if(pt.BTB_ENABLE==1) begin
294 : // maintain GHR at D
295 : assign ghr_d_ns[pt.BHT_GHR_SIZE-1:0]
296 : = ({pt.BHT_GHR_SIZE{~dec_tlu_flush_lower_r & i0_valid_d}} & {ghr_d[pt.BHT_GHR_SIZE-2:0], i0_taken_d}) |
297 : ({pt.BHT_GHR_SIZE{~dec_tlu_flush_lower_r & ~i0_valid_d}} & ghr_d[pt.BHT_GHR_SIZE-1:0] ) |
298 : ({pt.BHT_GHR_SIZE{ dec_tlu_flush_lower_r }} & ghr_x[pt.BHT_GHR_SIZE-1:0] );
299 :
300 : // maintain GHR at X
301 : assign ghr_x_ns[pt.BHT_GHR_SIZE-1:0]
302 : = ({pt.BHT_GHR_SIZE{ i0_valid_x}} & {ghr_x[pt.BHT_GHR_SIZE-2:0], i0_taken_x}) |
303 : ({pt.BHT_GHR_SIZE{~i0_valid_x}} & ghr_x[pt.BHT_GHR_SIZE-1:0] ) ;
304 :
305 :
306 : assign exu_i0_br_valid_r = i0_pp_r.valid;
307 : assign exu_i0_br_mp_r = i0_pp_r.misp;
308 : assign exu_i0_br_way_r = i0_pp_r.way;
309 : assign exu_i0_br_hist_r[1:0] = {2{i0_pp_r.valid}} & i0_pp_r.hist[1:0];
310 : assign exu_i0_br_error_r = i0_pp_r.br_error;
311 : assign exu_i0_br_middle_r = i0_pp_r.pc4 ^ i0_pp_r.boffset;
312 : assign exu_i0_br_start_error_r = i0_pp_r.br_start_error;
313 :
314 : assign {exu_i0_br_fghr_r[pt.BHT_GHR_SIZE-1:0],
315 : exu_i0_br_index_r[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]}= predpipe_r[PREDPIPESIZE-1:pt.BTB_BTAG_SIZE];
316 :
317 :
318 : assign final_predict_mp = (i0_flush_upper_x) ? i0_predict_p_x : '0;
319 :
320 : assign final_predpipe_mp[PREDPIPESIZE-1:0] = (i0_flush_upper_x) ? predpipe_x : '0;
321 :
322 : assign after_flush_eghr[pt.BHT_GHR_SIZE-1:0] = (i0_flush_upper_x & ~dec_tlu_flush_lower_r) ? ghr_d[pt.BHT_GHR_SIZE-1:0] : ghr_x[pt.BHT_GHR_SIZE-1:0];
323 :
324 :
325 : assign exu_mp_pkt.valid = final_predict_mp.valid;
326 : assign exu_mp_pkt.way = final_predict_mp.way;
327 : assign exu_mp_pkt.misp = final_predict_mp.misp;
328 : assign exu_mp_pkt.pcall = final_predict_mp.pcall;
329 : assign exu_mp_pkt.pja = final_predict_mp.pja;
330 : assign exu_mp_pkt.pret = final_predict_mp.pret;
331 : assign exu_mp_pkt.ataken = final_predict_mp.ataken;
332 : assign exu_mp_pkt.boffset = final_predict_mp.boffset;
333 : assign exu_mp_pkt.pc4 = final_predict_mp.pc4;
334 : assign exu_mp_pkt.hist[1:0] = final_predict_mp.hist[1:0];
335 : assign exu_mp_pkt.toffset[11:0] = final_predict_mp.toffset[11:0];
336 :
337 : assign exu_mp_fghr[pt.BHT_GHR_SIZE-1:0] = after_flush_eghr[pt.BHT_GHR_SIZE-1:0];
338 :
339 : assign {exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],
340 : exu_mp_btag[pt.BTB_BTAG_SIZE-1:0]} = final_predpipe_mp[PREDPIPESIZE-pt.BHT_GHR_SIZE-1:0];
341 :
342 : assign exu_mp_eghr[pt.BHT_GHR_SIZE-1:0] = final_predpipe_mp[PREDPIPESIZE-1:pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+pt.BTB_BTAG_SIZE+1]; // mp ghr for bht write
343 : end // if (pt.BTB_ENABLE==1)
344 : else begin
345 : assign ghr_d_ns = '0;
346 : assign ghr_x_ns = '0;
347 : assign exu_mp_pkt = '0;
348 : assign exu_mp_eghr = '0;
349 : assign exu_mp_fghr = '0;
350 : assign exu_mp_index = '0;
351 : assign exu_mp_btag = '0;
352 : assign exu_i0_br_hist_r = '0;
353 : assign exu_i0_br_error_r = '0;
354 : assign exu_i0_br_start_error_r = '0;
355 : assign exu_i0_br_index_r = '0;
356 : assign exu_i0_br_valid_r = '0;
357 : assign exu_i0_br_mp_r = '0;
358 : assign exu_i0_br_middle_r = '0;
359 : assign exu_i0_br_fghr_r = '0;
360 : assign exu_i0_br_way_r = '0;
361 : end // else: !if(pt.BTB_ENABLE==1)
362 :
363 : assign exu_flush_path_final[31:1] = ( {31{ dec_tlu_flush_lower_r }} & dec_tlu_flush_path_r[31:1] ) |
364 : ( {31{~dec_tlu_flush_lower_r & i0_flush_upper_d}} & i0_flush_path_d[31:1] );
365 :
366 : assign exu_npc_r[31:1] = (i0_pred_correct_upper_r) ? pred_correct_npc_r[31:1] : i0_flush_path_upper_r[31:1];
367 :
368 :
369 : endmodule // el2_exu
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