Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 :
17 : module el2_exu
18 : import el2_pkg::*;
19 : #(
20 : `include "el2_param.vh"
21 : )
22 : (
23 69840565 : input logic clk, // Top level clock
24 338 : input logic rst_l, // Reset
25 : // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
26 : /*verilator coverage_off*/
27 : input logic scan_mode, // Scan control
28 : /*verilator coverage_on*/
29 :
30 6195062 : input logic [1:0] dec_data_en, // Clock enable {x,r}, one cycle pulse
31 5989940 : input logic [1:0] dec_ctl_en, // Clock enable {x,r}, two cycle pulse
32 128 : input logic [31:0] dbg_cmd_wrdata, // Debug data to primary I0 RS1
33 1460 : input el2_alu_pkt_t i0_ap, // DEC alu {valid,predecodes}
34 :
35 168 : input logic dec_debug_wdata_rs1_d, // Debug select to primary I0 RS1
36 :
37 506166 : input el2_predict_pkt_t dec_i0_predict_p_d, // DEC branch predict packet
38 628591 : input logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // DEC predict fghr
39 651059 : input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // DEC predict index
40 21223 : input logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // DEC predict branch tag
41 :
42 45313 : input logic [31:0] lsu_result_m, // Load result M-stage
43 71598 : input logic [31:0] lsu_nonblock_load_data, // nonblock load data
44 5134863 : input logic dec_i0_rs1_en_d, // Qualify GPR RS1 data
45 3569581 : input logic dec_i0_rs2_en_d, // Qualify GPR RS2 data
46 407934 : input logic [31:0] gpr_i0_rs1_d, // DEC data gpr
47 598866 : input logic [31:0] gpr_i0_rs2_d, // DEC data gpr
48 2170592 : input logic [31:0] dec_i0_immed_d, // DEC data immediate
49 314101 : input logic [31:0] dec_i0_result_r, // DEC result in R-stage
50 123462 : input logic [12:1] dec_i0_br_immed_d, // Branch immediate
51 5407994 : input logic dec_i0_alu_decode_d, // Valid to X-stage ALU
52 3883757 : input logic dec_i0_branch_d, // Branch in D-stage
53 555609 : input logic dec_i0_select_pc_d, // PC select to RS1
54 1321 : input logic [31:1] dec_i0_pc_d, // Instruction PC
55 80402 : input logic [3:0] dec_i0_rs1_bypass_en_d, // DEC bypass select 1 - X-stage, 0 - dec bypass data
56 8620 : input logic [3:0] dec_i0_rs2_bypass_en_d, // DEC bypass select 1 - X-stage, 0 - dec bypass data
57 77278 : input logic dec_csr_ren_d, // CSR read select
58 7157 : input logic [31:0] dec_csr_rddata_d, // CSR read data
59 :
60 5490327 : input logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands
61 0 : input el2_mul_pkt_t mul_p, // DEC {valid, operand signs, low, operand bypass}
62 78130 : input el2_div_pkt_t div_p, // DEC {valid, unsigned, rem}
63 2628 : input logic dec_div_cancel, // Cancel the divide operation
64 :
65 138906 : input logic [31:1] pred_correct_npc_x, // DEC NPC for correctly predicted branch
66 :
67 59220 : input logic dec_tlu_flush_lower_r, // Flush divide and secondary ALUs
68 24762 : input logic [31:1] dec_tlu_flush_path_r, // Redirect target
69 :
70 :
71 0 : input logic dec_extint_stall, // External stall mux select
72 0 : input logic [31:2] dec_tlu_meihap, // External stall mux data
73 :
74 :
75 413043 : output logic [31:0] exu_lsu_rs1_d, // LSU operand
76 81488 : output logic [31:0] exu_lsu_rs2_d, // LSU operand
77 :
78 673974 : output logic exu_flush_final, // Pipe is being flushed this cycle
79 227566 : output logic [31:1] exu_flush_path_final, // Target for the oldest flush source
80 :
81 614539 : output logic [31:0] exu_i0_result_x, // Primary ALU result to DEC
82 339 : output logic [31:1] exu_i0_pc_x, // Primary PC result to DEC
83 3978 : output logic [31:0] exu_csr_rs1_x, // RS1 source for a CSR instruction
84 :
85 344 : output logic [31:1] exu_npc_r, // Divide NPC
86 2721663 : output logic [1:0] exu_i0_br_hist_r, // to DEC I0 branch history
87 26468 : output logic exu_i0_br_error_r, // to DEC I0 branch error
88 9608 : output logic exu_i0_br_start_error_r, // to DEC I0 branch start error
89 187560 : output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_i0_br_index_r, // to DEC I0 branch index
90 3012693 : output logic exu_i0_br_valid_r, // to DEC I0 branch valid
91 410552 : output logic exu_i0_br_mp_r, // to DEC I0 branch mispredict
92 2380332 : output logic exu_i0_br_middle_r, // to DEC I0 branch middle
93 366738 : output logic [pt.BHT_GHR_SIZE-1:0] exu_i0_br_fghr_r, // to DEC I0 branch fghr
94 2110720 : output logic exu_i0_br_way_r, // to DEC I0 branch way
95 :
96 34486 : output el2_predict_pkt_t exu_mp_pkt, // Mispredict branch packet
97 300064 : output logic [pt.BHT_GHR_SIZE-1:0] exu_mp_eghr, // Mispredict global history
98 378616 : output logic [pt.BHT_GHR_SIZE-1:0] exu_mp_fghr, // Mispredict fghr
99 196152 : output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] exu_mp_index, // Mispredict index
100 115620 : output logic [pt.BTB_BTAG_SIZE-1:0] exu_mp_btag, // Mispredict btag
101 :
102 :
103 410552 : output logic exu_pmu_i0_br_misp, // to PMU - I0 E4 branch mispredict
104 2911037 : output logic exu_pmu_i0_br_ataken, // to PMU - I0 E4 taken
105 3495269 : output logic exu_pmu_i0_pc4, // to PMU - I0 E4 PC
106 :
107 :
108 24784 : output logic [31:0] exu_div_result, // Divide result
109 156852 : output logic exu_div_wren // Divide write enable to GPR
110 : );
111 :
112 :
113 :
114 :
115 62131 : logic [31:0] i0_rs1_bypass_data_d;
116 13180 : logic [31:0] i0_rs2_bypass_data_d;
117 909107 : logic i0_rs1_bypass_en_d;
118 469016 : logic i0_rs2_bypass_en_d;
119 417765 : logic [31:0] i0_rs1_d, i0_rs2_d;
120 357857 : logic [31:0] muldiv_rs1_d;
121 138899 : logic [31:1] pred_correct_npc_r;
122 2963186 : logic i0_pred_correct_upper_r;
123 344 : logic [31:1] i0_flush_path_upper_r;
124 170365 : logic x_data_en, x_data_en_q1, x_data_en_q2, r_data_en, r_data_en_q2;
125 5989940 : logic x_ctl_en, r_ctl_en;
126 :
127 381774 : logic [pt.BHT_GHR_SIZE-1:0] ghr_d_ns, ghr_d;
128 381774 : logic [pt.BHT_GHR_SIZE-1:0] ghr_x_ns, ghr_x;
129 3099955 : logic i0_taken_d;
130 3099928 : logic i0_taken_x;
131 3127355 : logic i0_valid_d;
132 3127328 : logic i0_valid_x;
133 378616 : logic [pt.BHT_GHR_SIZE-1:0] after_flush_eghr;
134 :
135 31512 : el2_predict_pkt_t final_predict_mp;
136 506166 : el2_predict_pkt_t i0_predict_newp_d;
137 :
138 0 : logic flush_in_d;
139 568203 : logic [31:0] alu_result_x;
140 :
141 250948 : logic mul_valid_x;
142 17509 : logic [31:0] mul_result_x;
143 :
144 349931 : el2_predict_pkt_t i0_pp_r;
145 :
146 614802 : logic i0_flush_upper_d;
147 2461 : logic [31:1] i0_flush_path_d;
148 506166 : el2_predict_pkt_t i0_predict_p_d;
149 2963219 : logic i0_pred_correct_upper_d;
150 :
151 614802 : logic i0_flush_upper_x;
152 344 : logic [31:1] i0_flush_path_x;
153 349931 : el2_predict_pkt_t i0_predict_p_x;
154 2963195 : logic i0_pred_correct_upper_x;
155 3883730 : logic i0_branch_x;
156 :
157 : localparam PREDPIPESIZE = pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+1+pt.BHT_GHR_SIZE+pt.BTB_BTAG_SIZE;
158 55441 : logic [PREDPIPESIZE-1:0] predpipe_d, predpipe_x, predpipe_r, final_predpipe_mp;
159 :
160 :
161 :
162 :
163 : rvdffpcie #(31) i_flush_path_x_ff (.*, .clk(clk), .en ( x_data_en ), .din ( i0_flush_path_d[31:1] ), .dout( i0_flush_path_x[31:1] ) );
164 : rvdffe #(32) i_csr_rs1_x_ff (.*, .clk(clk), .en ( x_data_en_q1 ), .din ( i0_rs1_d[31:0] ), .dout( exu_csr_rs1_x[31:0] ) );
165 : rvdffppe #($bits(el2_predict_pkt_t)) i_predictpacket_x_ff (.*, .clk(clk), .en ( x_data_en ), .din ( i0_predict_p_d ), .dout( i0_predict_p_x ) );
166 : rvdffe #(PREDPIPESIZE) i_predpipe_x_ff (.*, .clk(clk), .en ( x_data_en_q2 ), .din ( predpipe_d ), .dout( predpipe_x ) );
167 : rvdffe #(PREDPIPESIZE) i_predpipe_r_ff (.*, .clk(clk), .en ( r_data_en_q2 ), .din ( predpipe_x ), .dout( predpipe_r ) );
168 :
169 : rvdffe #(4+pt.BHT_GHR_SIZE) i_x_ff (.*, .clk(clk), .en ( x_ctl_en ), .din ({i0_valid_d,i0_taken_d,i0_flush_upper_d,i0_pred_correct_upper_d,ghr_x_ns[pt.BHT_GHR_SIZE-1:0]} ),
170 : .dout({i0_valid_x,i0_taken_x,i0_flush_upper_x,i0_pred_correct_upper_x,ghr_x[pt.BHT_GHR_SIZE-1:0]} ) );
171 :
172 : rvdffppe #($bits(el2_predict_pkt_t)+1) i_r_ff0 (.*, .clk(clk), .en ( r_ctl_en ), .din ({i0_pred_correct_upper_x, i0_predict_p_x}),
173 : .dout({i0_pred_correct_upper_r, i0_pp_r }) );
174 :
175 : rvdffpcie #(31) i_flush_r_ff (.*, .clk(clk), .en ( r_data_en ), .din ( i0_flush_path_x[31:1] ), .dout( i0_flush_path_upper_r[31:1]) );
176 : rvdffpcie #(31) i_npc_r_ff (.*, .clk(clk), .en ( r_data_en ), .din ( pred_correct_npc_x[31:1] ), .dout( pred_correct_npc_r[31:1] ) );
177 :
178 : rvdffie #(pt.BHT_GHR_SIZE+2,1) i_misc_ff (.*, .clk(clk), .din ({ghr_d_ns[pt.BHT_GHR_SIZE-1:0], mul_p.valid, dec_i0_branch_d}),
179 : .dout({ghr_d[pt.BHT_GHR_SIZE-1:0] , mul_valid_x, i0_branch_x}) );
180 :
181 :
182 :
183 :
184 :
185 : assign predpipe_d[PREDPIPESIZE-1:0]
186 : = {i0_predict_fghr_d, i0_predict_index_d, i0_predict_btag_d};
187 :
188 :
189 : assign i0_rs1_bypass_en_d = dec_i0_rs1_bypass_en_d[0] | dec_i0_rs1_bypass_en_d[1] | dec_i0_rs1_bypass_en_d[2] | dec_i0_rs1_bypass_en_d[3];
190 : assign i0_rs2_bypass_en_d = dec_i0_rs2_bypass_en_d[0] | dec_i0_rs2_bypass_en_d[1] | dec_i0_rs2_bypass_en_d[2] | dec_i0_rs2_bypass_en_d[3];
191 :
192 : assign i0_rs1_bypass_data_d[31:0]=({32{dec_i0_rs1_bypass_en_d[0]}} & dec_i0_result_r[31:0] ) |
193 : ({32{dec_i0_rs1_bypass_en_d[1]}} & lsu_result_m[31:0] ) |
194 : ({32{dec_i0_rs1_bypass_en_d[2]}} & exu_i0_result_x[31:0] ) |
195 : ({32{dec_i0_rs1_bypass_en_d[3]}} & lsu_nonblock_load_data[31:0]);
196 :
197 : assign i0_rs2_bypass_data_d[31:0]=({32{dec_i0_rs2_bypass_en_d[0]}} & dec_i0_result_r[31:0] ) |
198 : ({32{dec_i0_rs2_bypass_en_d[1]}} & lsu_result_m[31:0] ) |
199 : ({32{dec_i0_rs2_bypass_en_d[2]}} & exu_i0_result_x[31:0] ) |
200 : ({32{dec_i0_rs2_bypass_en_d[3]}} & lsu_nonblock_load_data[31:0]);
201 :
202 :
203 : assign i0_rs1_d[31:0] = ({32{ i0_rs1_bypass_en_d }} & i0_rs1_bypass_data_d[31:0]) |
204 : ({32{~i0_rs1_bypass_en_d & dec_i0_select_pc_d }} & {dec_i0_pc_d[31:1],1'b0} ) | // for jal's
205 : ({32{~i0_rs1_bypass_en_d & dec_debug_wdata_rs1_d }} & dbg_cmd_wrdata[31:0] ) |
206 : ({32{~i0_rs1_bypass_en_d & ~dec_debug_wdata_rs1_d & dec_i0_rs1_en_d}} & gpr_i0_rs1_d[31:0] );
207 :
208 : assign i0_rs2_d[31:0] = ({32{~i0_rs2_bypass_en_d & dec_i0_rs2_en_d}} & gpr_i0_rs2_d[31:0] ) |
209 : ({32{~i0_rs2_bypass_en_d }} & dec_i0_immed_d[31:0] ) |
210 : ({32{ i0_rs2_bypass_en_d }} & i0_rs2_bypass_data_d[31:0]);
211 :
212 :
213 : assign exu_lsu_rs1_d[31:0] = ({32{~i0_rs1_bypass_en_d & ~dec_extint_stall & dec_i0_rs1_en_d & dec_qual_lsu_d}} & gpr_i0_rs1_d[31:0] ) |
214 : ({32{ i0_rs1_bypass_en_d & ~dec_extint_stall & dec_qual_lsu_d}} & i0_rs1_bypass_data_d[31:0]) |
215 : ({32{ dec_extint_stall & dec_qual_lsu_d}} & {dec_tlu_meihap[31:2],2'b0});
216 :
217 : assign exu_lsu_rs2_d[31:0] = ({32{~i0_rs2_bypass_en_d & ~dec_extint_stall & dec_i0_rs2_en_d & dec_qual_lsu_d}} & gpr_i0_rs2_d[31:0] ) |
218 : ({32{ i0_rs2_bypass_en_d & ~dec_extint_stall & dec_qual_lsu_d}} & i0_rs2_bypass_data_d[31:0]);
219 :
220 :
221 : assign muldiv_rs1_d[31:0] = ({32{~i0_rs1_bypass_en_d & dec_i0_rs1_en_d}} & gpr_i0_rs1_d[31:0] ) |
222 : ({32{ i0_rs1_bypass_en_d }} & i0_rs1_bypass_data_d[31:0]);
223 :
224 :
225 : assign x_data_en = dec_data_en[1];
226 : assign x_data_en_q1 = dec_data_en[1] & dec_csr_ren_d;
227 : assign x_data_en_q2 = dec_data_en[1] & dec_i0_branch_d;
228 : assign r_data_en = dec_data_en[0];
229 : assign r_data_en_q2 = dec_data_en[0] & i0_branch_x;
230 : assign x_ctl_en = dec_ctl_en[1];
231 : assign r_ctl_en = dec_ctl_en[0];
232 :
233 :
234 :
235 :
236 : el2_exu_alu_ctl #(.pt(pt)) i_alu (.*,
237 : .enable ( x_data_en ), // I
238 : .pp_in ( i0_predict_newp_d ), // I
239 : .valid_in ( dec_i0_alu_decode_d ), // I
240 : .flush_upper_x ( i0_flush_upper_x ), // I
241 : .flush_lower_r ( dec_tlu_flush_lower_r ), // I
242 : .a_in ( i0_rs1_d[31:0] ), // I
243 : .b_in ( i0_rs2_d[31:0] ), // I
244 : .pc_in ( dec_i0_pc_d[31:1] ), // I
245 : .brimm_in ( dec_i0_br_immed_d[12:1] ), // I
246 : .ap ( i0_ap ), // I
247 : .csr_ren_in ( dec_csr_ren_d ), // I
248 : .csr_rddata_in ( dec_csr_rddata_d[31:0] ), // I
249 : .result_ff ( alu_result_x[31:0] ), // O
250 : .flush_upper_out ( i0_flush_upper_d ), // O
251 : .flush_final_out ( exu_flush_final ), // O
252 : .flush_path_out ( i0_flush_path_d[31:1] ), // O
253 : .predict_p_out ( i0_predict_p_d ), // O
254 : .pred_correct_out ( i0_pred_correct_upper_d ), // O
255 : .pc_ff ( exu_i0_pc_x[31:1] )); // O
256 :
257 :
258 :
259 : el2_exu_mul_ctl #(.pt(pt)) i_mul (.*,
260 : .mul_p ( mul_p & {$bits(el2_mul_pkt_t){mul_p.valid}} ), // I
261 : .rs1_in ( muldiv_rs1_d[31:0] & {32{mul_p.valid}} ), // I
262 : .rs2_in ( i0_rs2_d[31:0] & {32{mul_p.valid}} ), // I
263 : .result_x ( mul_result_x[31:0] )); // O
264 :
265 :
266 :
267 : el2_exu_div_ctl #(.pt(pt)) i_div (.*,
268 : .cancel ( dec_div_cancel ), // I
269 : .dp ( div_p ), // I
270 : .dividend ( muldiv_rs1_d[31:0] ), // I
271 : .divisor ( i0_rs2_d[31:0] ), // I
272 : .finish_dly ( exu_div_wren ), // O
273 : .out ( exu_div_result[31:0] )); // O
274 :
275 :
276 :
277 : assign exu_i0_result_x[31:0] = (mul_valid_x) ? mul_result_x[31:0] : alu_result_x[31:0];
278 :
279 :
280 :
281 :
282 339 : always_comb begin
283 339 : i0_predict_newp_d = dec_i0_predict_p_d;
284 339 : i0_predict_newp_d.boffset = dec_i0_pc_d[1]; // from the start of inst
285 : end
286 :
287 :
288 : assign exu_pmu_i0_br_misp = i0_pp_r.misp;
289 : assign exu_pmu_i0_br_ataken = i0_pp_r.ataken;
290 : assign exu_pmu_i0_pc4 = i0_pp_r.pc4;
291 :
292 :
293 : assign i0_valid_d = i0_predict_p_d.valid & dec_i0_alu_decode_d & ~dec_tlu_flush_lower_r;
294 : assign i0_taken_d = (i0_predict_p_d.ataken & dec_i0_alu_decode_d);
295 :
296 : if(pt.BTB_ENABLE==1) begin
297 : // maintain GHR at D
298 : assign ghr_d_ns[pt.BHT_GHR_SIZE-1:0]
299 : = ({pt.BHT_GHR_SIZE{~dec_tlu_flush_lower_r & i0_valid_d}} & {ghr_d[pt.BHT_GHR_SIZE-2:0], i0_taken_d}) |
300 : ({pt.BHT_GHR_SIZE{~dec_tlu_flush_lower_r & ~i0_valid_d}} & ghr_d[pt.BHT_GHR_SIZE-1:0] ) |
301 : ({pt.BHT_GHR_SIZE{ dec_tlu_flush_lower_r }} & ghr_x[pt.BHT_GHR_SIZE-1:0] );
302 :
303 : // maintain GHR at X
304 : assign ghr_x_ns[pt.BHT_GHR_SIZE-1:0]
305 : = ({pt.BHT_GHR_SIZE{ i0_valid_x}} & {ghr_x[pt.BHT_GHR_SIZE-2:0], i0_taken_x}) |
306 : ({pt.BHT_GHR_SIZE{~i0_valid_x}} & ghr_x[pt.BHT_GHR_SIZE-1:0] ) ;
307 :
308 :
309 : assign exu_i0_br_valid_r = i0_pp_r.valid;
310 : assign exu_i0_br_mp_r = i0_pp_r.misp;
311 : assign exu_i0_br_way_r = i0_pp_r.way;
312 : assign exu_i0_br_hist_r[1:0] = {2{i0_pp_r.valid}} & i0_pp_r.hist[1:0];
313 : assign exu_i0_br_error_r = i0_pp_r.br_error;
314 : assign exu_i0_br_middle_r = i0_pp_r.pc4 ^ i0_pp_r.boffset;
315 : assign exu_i0_br_start_error_r = i0_pp_r.br_start_error;
316 :
317 : assign {exu_i0_br_fghr_r[pt.BHT_GHR_SIZE-1:0],
318 : exu_i0_br_index_r[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO]}= predpipe_r[PREDPIPESIZE-1:pt.BTB_BTAG_SIZE];
319 :
320 :
321 : assign final_predict_mp = (i0_flush_upper_x) ? i0_predict_p_x : '0;
322 :
323 : assign final_predpipe_mp[PREDPIPESIZE-1:0] = (i0_flush_upper_x) ? predpipe_x : '0;
324 :
325 : assign after_flush_eghr[pt.BHT_GHR_SIZE-1:0] = (i0_flush_upper_x & ~dec_tlu_flush_lower_r) ? ghr_d[pt.BHT_GHR_SIZE-1:0] : ghr_x[pt.BHT_GHR_SIZE-1:0];
326 :
327 :
328 : assign exu_mp_pkt.valid = final_predict_mp.valid;
329 : assign exu_mp_pkt.way = final_predict_mp.way;
330 : assign exu_mp_pkt.misp = final_predict_mp.misp;
331 : assign exu_mp_pkt.pcall = final_predict_mp.pcall;
332 : assign exu_mp_pkt.pja = final_predict_mp.pja;
333 : assign exu_mp_pkt.pret = final_predict_mp.pret;
334 : assign exu_mp_pkt.ataken = final_predict_mp.ataken;
335 : assign exu_mp_pkt.boffset = final_predict_mp.boffset;
336 : assign exu_mp_pkt.pc4 = final_predict_mp.pc4;
337 : assign exu_mp_pkt.hist[1:0] = final_predict_mp.hist[1:0];
338 : assign exu_mp_pkt.toffset[11:0] = final_predict_mp.toffset[11:0];
339 :
340 : assign exu_mp_fghr[pt.BHT_GHR_SIZE-1:0] = after_flush_eghr[pt.BHT_GHR_SIZE-1:0];
341 :
342 : assign {exu_mp_index[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO],
343 : exu_mp_btag[pt.BTB_BTAG_SIZE-1:0]} = final_predpipe_mp[PREDPIPESIZE-pt.BHT_GHR_SIZE-1:0];
344 :
345 : assign exu_mp_eghr[pt.BHT_GHR_SIZE-1:0] = final_predpipe_mp[PREDPIPESIZE-1:pt.BTB_ADDR_HI-pt.BTB_ADDR_LO+pt.BTB_BTAG_SIZE+1]; // mp ghr for bht write
346 : end // if (pt.BTB_ENABLE==1)
347 : else begin
348 : assign ghr_d_ns = '0;
349 : assign ghr_x_ns = '0;
350 : assign exu_mp_pkt = '0;
351 : assign exu_mp_eghr = '0;
352 : assign exu_mp_fghr = '0;
353 : assign exu_mp_index = '0;
354 : assign exu_mp_btag = '0;
355 : assign exu_i0_br_hist_r = '0;
356 : assign exu_i0_br_error_r = '0;
357 : assign exu_i0_br_start_error_r = '0;
358 : assign exu_i0_br_index_r = '0;
359 : assign exu_i0_br_valid_r = '0;
360 : assign exu_i0_br_mp_r = '0;
361 : assign exu_i0_br_middle_r = '0;
362 : assign exu_i0_br_fghr_r = '0;
363 : assign exu_i0_br_way_r = '0;
364 : end // else: !if(pt.BTB_ENABLE==1)
365 :
366 : assign exu_flush_path_final[31:1] = ( {31{ dec_tlu_flush_lower_r }} & dec_tlu_flush_path_r[31:1] ) |
367 : ( {31{~dec_tlu_flush_lower_r & i0_flush_upper_d}} & i0_flush_path_d[31:1] );
368 :
369 : assign exu_npc_r[31:1] = (i0_pred_correct_upper_r) ? pred_correct_npc_r[31:1] : i0_flush_path_upper_r[31:1];
370 :
371 :
372 : endmodule // el2_exu
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