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Current view: Cores-VeeR-EL2—Cores-VeeR-EL2—design—el2_dma_ctrl.sv Coverage Hit Total
Test Date: 08-11-2024 Toggle 90.1% 146 162
Test: all Branch 100.0% 4 4

            Line data    Source code
       1              : // SPDX-License-Identifier: Apache-2.0
       2              : // Copyright 2020 Western Digital Corporation or its affiliates.
       3              : //
       4              : // Licensed under the Apache License, Version 2.0 (the "License");
       5              : // you may not use this file except in compliance with the License.
       6              : // You may obtain a copy of the License at
       7              : //
       8              : // http://www.apache.org/licenses/LICENSE-2.0
       9              : //
      10              : // Unless required by applicable law or agreed to in writing, software
      11              : // distributed under the License is distributed on an "AS IS" BASIS,
      12              : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      13              : // See the License for the specific language governing permissions and
      14              : // limitations under the License.
      15              : 
      16              : //********************************************************************************
      17              : // $Id$
      18              : //
      19              : // Function: Top level VeeR core file
      20              : // Comments:
      21              : //
      22              : //********************************************************************************
      23              : 
      24              : module el2_dma_ctrl 
      25              : import el2_pkg::*;
      26              : #(
      27              : `include "el2_param.vh"
      28              :  )(
      29     69934465 :    input logic         clk,
      30     69934465 :    input logic         free_clk,
      31          362 :    input logic         rst_l,
      32          346 :    input logic         dma_bus_clk_en, // slave bus clock enable
      33            2 :    input logic         clk_override,
      34            0 :    input logic         scan_mode,
      35              : 
      36              :    // Debug signals
      37           49 :    input logic [31:0]  dbg_cmd_addr,
      38          267 :    input logic [31:0]  dbg_cmd_wrdata,
      39         3708 :    input logic         dbg_cmd_valid,
      40          321 :    input logic         dbg_cmd_write, // 1: write command, 0: read_command
      41         1462 :    input logic [1:0]   dbg_cmd_type, // 0:gpr 1:csr 2: memory
      42         1165 :    input logic [1:0]   dbg_cmd_size, // size of the abstract mem access debug command
      43              : 
      44         3534 :    input  logic        dbg_dma_bubble,   // Debug needs a bubble to send a valid
      45         4452 :    output logic        dma_dbg_ready,    // DMA is ready to accept debug request
      46              : 
      47         1404 :    output logic        dma_dbg_cmd_done,
      48          204 :    output logic        dma_dbg_cmd_fail,
      49         1225 :    output logic [31:0] dma_dbg_rddata,
      50              : 
      51              :    // Core side signals
      52         1292 :    output logic        dma_dccm_req,  // DMA dccm request (only one of dccm/iccm will be set)
      53         1380 :    output logic        dma_iccm_req,  // DMA iccm request
      54          611 :    output logic [2:0]  dma_mem_tag,   // DMA Buffer entry number
      55          291 :    output logic [31:0] dma_mem_addr,  // DMA request address
      56           64 :    output logic [2:0]  dma_mem_sz,    // DMA request size
      57          276 :    output logic        dma_mem_write, // DMA write to dccm/iccm
      58          909 :    output logic [63:0] dma_mem_wdata, // DMA write data
      59              : 
      60          684 :    input logic         dccm_dma_rvalid,    // dccm data valid for DMA read
      61           31 :    input logic         dccm_dma_ecc_error, // ECC error on DMA read
      62          159 :    input logic [2:0]   dccm_dma_rtag,      // Tag of the DMA req
      63        39694 :    input logic [63:0]  dccm_dma_rdata,     // dccm data for DMA read
      64          716 :    input logic         iccm_dma_rvalid,    // iccm data valid for DMA read
      65           30 :    input logic         iccm_dma_ecc_error, // ECC error on DMA read
      66          140 :    input logic [2:0]   iccm_dma_rtag,      // Tag of the DMA req
      67          146 :    input logic [63:0]  iccm_dma_rdata,     // iccm data for DMA read
      68              : 
      69         2513 :    output logic        dma_active,         // DMA is busy
      70         1240 :    output logic        dma_dccm_stall_any, // stall dccm pipe (bubble) so that DMA can proceed
      71         1298 :    output logic        dma_iccm_stall_any, // stall iccm pipe (bubble) so that DMA can proceed
      72      2235377 :    input logic         dccm_ready, // dccm ready to accept DMA request
      73       639491 :    input logic         iccm_ready, // iccm ready to accept DMA request
      74          345 :    input logic [2:0]   dec_tlu_dma_qos_prty,    // DMA QoS priority coming from MFDC [18:15]
      75              : 
      76              :    // PMU signals
      77          710 :    output logic        dma_pmu_dccm_read,
      78          582 :    output logic        dma_pmu_dccm_write,
      79         1450 :    output logic        dma_pmu_any_read,
      80         1206 :    output logic        dma_pmu_any_write,
      81              : 
      82              :    // AXI Write Channels
      83          760 :    input  logic                        dma_axi_awvalid,
      84         1040 :    output logic                        dma_axi_awready,
      85          327 :    input  logic [pt.DMA_BUS_TAG-1:0]   dma_axi_awid,
      86          301 :    input  logic [31:0]                 dma_axi_awaddr,
      87            2 :    input  logic [2:0]                  dma_axi_awsize,
      88              : 
      89              : 
      90          760 :    input  logic                        dma_axi_wvalid,
      91          544 :    output logic                        dma_axi_wready,
      92        29939 :    input  logic [63:0]                 dma_axi_wdata,
      93       185763 :    input  logic [7:0]                  dma_axi_wstrb,
      94              : 
      95          658 :    output logic                        dma_axi_bvalid,
      96           94 :    input  logic                        dma_axi_bready,
      97          504 :    output logic [1:0]                  dma_axi_bresp,
      98          426 :    output logic [pt.DMA_BUS_TAG-1:0]   dma_axi_bid,
      99              : 
     100              :    // AXI Read Channels
     101          906 :    input  logic                        dma_axi_arvalid,
     102          647 :    output logic                        dma_axi_arready,
     103            3 :    input  logic [pt.DMA_BUS_TAG-1:0]   dma_axi_arid,
     104          305 :    input  logic [31:0]                 dma_axi_araddr,
     105            3 :    input  logic [2:0]                  dma_axi_arsize,
     106              : 
     107          906 :    output logic                        dma_axi_rvalid,
     108          926 :    input  logic                        dma_axi_rready,
     109          426 :    output logic [pt.DMA_BUS_TAG-1:0]   dma_axi_rid,
     110         1220 :    output logic [63:0]                 dma_axi_rdata,
     111          504 :    output logic [1:0]                  dma_axi_rresp,
     112          347 :    output logic                        dma_axi_rlast
     113              : );
     114              : 
     115              : 
     116              :    localparam DEPTH = pt.DMA_BUF_DEPTH;
     117              :    localparam DEPTH_PTR = $clog2(DEPTH);
     118              :    localparam NACK_COUNT = 7;
     119              : 
     120          610 :    logic [DEPTH-1:0]        fifo_valid;
     121           80 :    logic [DEPTH-1:0][1:0]   fifo_error;
     122           94 :    logic [DEPTH-1:0]        fifo_error_bus;
     123          280 :    logic [DEPTH-1:0]        fifo_rpend;
     124          610 :    logic [DEPTH-1:0]        fifo_done;      // DMA trxn is done in core
     125          610 :    logic [DEPTH-1:0]        fifo_done_bus;  // DMA trxn is done in core but synced to bus clock
     126           37 :    logic [DEPTH-1:0][31:0]  fifo_addr;
     127           12 :    logic [DEPTH-1:0][2:0]   fifo_sz;
     128            7 :    logic [DEPTH-1:0][7:0]   fifo_byteen;
     129           30 :    logic [DEPTH-1:0]        fifo_write;
     130            0 :    logic [DEPTH-1:0]        fifo_posted_write;
     131           11 :    logic [DEPTH-1:0]        fifo_dbg;
     132              :    logic [DEPTH-1:0][63:0]  fifo_data;
     133           66 :    logic [DEPTH-1:0][pt.DMA_BUS_TAG-1:0]  fifo_tag;
     134            0 :    logic [DEPTH-1:0][pt.DMA_BUS_ID-1:0]   fifo_mid;
     135            0 :    logic [DEPTH-1:0][pt.DMA_BUS_PRTY-1:0] fifo_prty;
     136              : 
     137          890 :    logic [DEPTH-1:0]        fifo_cmd_en;
     138          730 :    logic [DEPTH-1:0]        fifo_data_en;
     139          280 :    logic [DEPTH-1:0]        fifo_pend_en;
     140          612 :    logic [DEPTH-1:0]        fifo_done_en;
     141          612 :    logic [DEPTH-1:0]        fifo_done_bus_en;
     142           94 :    logic [DEPTH-1:0]        fifo_error_en;
     143           94 :    logic [DEPTH-1:0]        fifo_error_bus_en;
     144          610 :    logic [DEPTH-1:0]        fifo_reset;
     145          404 :    logic [DEPTH-1:0][1:0]   fifo_error_in;
     146              :    logic [DEPTH-1:0][63:0]  fifo_data_in;
     147              : 
     148         1529 :    logic                    fifo_write_in;
     149            0 :    logic                    fifo_posted_write_in;
     150         3708 :    logic                    fifo_dbg_in;
     151         3082 :    logic [31:0]             fifo_addr_in;
     152          606 :    logic [2:0]              fifo_sz_in;
     153           34 :    logic [7:0]              fifo_byteen_in;
     154              : 
     155          611 :    logic [DEPTH_PTR-1:0]    RspPtr, NxtRspPtr;
     156          611 :    logic [DEPTH_PTR-1:0]    WrPtr, NxtWrPtr;
     157          611 :    logic [DEPTH_PTR-1:0]    RdPtr, NxtRdPtr;
     158         2968 :    logic                    WrPtrEn, RdPtrEn, RspPtrEn;
     159              : 
     160          153 :    logic [1:0]              dma_dbg_sz;
     161            0 :    logic [1:0]              dma_dbg_addr;
     162         1237 :    logic [31:0]             dma_dbg_mem_rddata;
     163          317 :    logic [31:0]             dma_dbg_mem_wrdata;
     164          204 :    logic                    dma_dbg_cmd_error;
     165         1404 :    logic                    dma_dbg_cmd_done_q;
     166              : 
     167         3247 :    logic                    fifo_full, fifo_full_spec, fifo_empty;
     168            0 :    logic                    dma_address_error, dma_alignment_error;
     169            0 :    logic [3:0]              num_fifo_vld;
     170         2548 :    logic                    dma_mem_req;
     171          291 :    logic [31:0]             dma_mem_addr_int;
     172           64 :    logic [2:0]              dma_mem_sz_int;
     173           54 :    logic [7:0]              dma_mem_byteen;
     174          524 :    logic                    dma_mem_addr_in_dccm;
     175          553 :    logic                    dma_mem_addr_in_iccm;
     176            0 :    logic                    dma_mem_addr_in_pic;
     177          550 :    logic                    dma_mem_addr_in_pic_region_nc;
     178          550 :    logic                    dma_mem_addr_in_dccm_region_nc;
     179          593 :    logic                    dma_mem_addr_in_iccm_region_nc;
     180              : 
     181          345 :    logic [2:0]              dma_nack_count, dma_nack_count_d, dma_nack_count_csr;
     182              : 
     183         5375 :    logic                    dma_buffer_c1_clken;
     184         5183 :    logic                    dma_free_clken;
     185     69902702 :    logic                    dma_buffer_c1_clk;
     186     69921650 :    logic                    dma_free_clk;
     187        44310 :    logic                    dma_bus_clk;
     188              : 
     189         1564 :    logic                    bus_rsp_valid, bus_rsp_sent;
     190         1664 :    logic                    bus_cmd_valid, bus_cmd_sent;
     191            0 :    logic                    bus_cmd_write, bus_cmd_posted_write;
     192           34 :    logic [7:0]              bus_cmd_byteen;
     193          606 :    logic [2:0]              bus_cmd_sz;
     194          368 :    logic [31:0]             bus_cmd_addr;
     195          156 :    logic [63:0]             bus_cmd_wdata;
     196          372 :    logic [pt.DMA_BUS_TAG-1:0]  bus_cmd_tag;
     197            0 :    logic [pt.DMA_BUS_ID-1:0]   bus_cmd_mid;
     198            0 :    logic [pt.DMA_BUS_PRTY-1:0] bus_cmd_prty;
     199            0 :    logic                    bus_posted_write_done;
     200              : 
     201            0 :    logic                    fifo_full_spec_bus;
     202         3538 :    logic                    dbg_dma_bubble_bus;
     203            0 :    logic                    stall_dma_in;
     204         3885 :    logic                    dma_fifo_ready;
     205              : 
     206          760 :    logic                       wrbuf_en, wrbuf_data_en;
     207          758 :    logic                       wrbuf_cmd_sent, wrbuf_rst, wrbuf_data_rst;
     208          759 :    logic                       wrbuf_vld, wrbuf_data_vld;
     209          327 :    logic [pt.DMA_BUS_TAG-1:0]  wrbuf_tag;
     210            6 :    logic [2:0]                 wrbuf_sz;
     211           23 :    logic [31:0]                wrbuf_addr;
     212          156 :    logic [63:0]                wrbuf_data;
     213           34 :    logic [7:0]                 wrbuf_byteen;
     214              : 
     215          906 :    logic                       rdbuf_en;
     216          906 :    logic                       rdbuf_cmd_sent, rdbuf_rst;
     217          906 :    logic                       rdbuf_vld;
     218            7 :    logic [pt.DMA_BUS_TAG-1:0]  rdbuf_tag;
     219            7 :    logic [2:0]                 rdbuf_sz;
     220           27 :    logic [31:0]                rdbuf_addr;
     221              : 
     222          838 :    logic                       axi_mstr_prty_in, axi_mstr_prty_en;
     223          832 :    logic                       axi_mstr_priority;
     224          759 :    logic                       axi_mstr_sel;
     225              : 
     226            0 :    logic                       axi_rsp_valid, axi_rsp_sent;
     227          276 :    logic                       axi_rsp_write;
     228          426 :    logic [pt.DMA_BUS_TAG-1:0]  axi_rsp_tag;
     229          504 :    logic [1:0]                 axi_rsp_error;
     230         1220 :    logic [63:0]                axi_rsp_rdata;
     231              : 
     232              :    //------------------------LOGIC STARTS HERE---------------------------------
     233              : 
     234              :    // FIFO inputs
     235              :    assign fifo_addr_in[31:0]    = dbg_cmd_valid ? dbg_cmd_addr[31:0] : bus_cmd_addr[31:0];
     236              :    assign fifo_byteen_in[7:0]   = {8{~dbg_cmd_valid}} & bus_cmd_byteen[7:0];    // Byte enable is used only for bus requests
     237              :    assign fifo_sz_in[2:0]       = dbg_cmd_valid ? {1'b0,dbg_cmd_size[1:0]} : bus_cmd_sz[2:0];
     238              :    assign fifo_write_in         = dbg_cmd_valid ? dbg_cmd_write : bus_cmd_write;
     239              :    assign fifo_posted_write_in  = ~dbg_cmd_valid & bus_cmd_posted_write;
     240              :    assign fifo_dbg_in           = dbg_cmd_valid;
     241              : 
     242              :    for (genvar i=0 ;i<DEPTH; i++) begin: GenFifo
     243              :       assign fifo_cmd_en[i]   = ((bus_cmd_sent & dma_bus_clk_en) | (dbg_cmd_valid & dbg_cmd_type[1])) & (i == WrPtr[DEPTH_PTR-1:0]);
     244              :       assign fifo_data_en[i] = (((bus_cmd_sent & fifo_write_in & dma_bus_clk_en) | (dbg_cmd_valid & dbg_cmd_type[1] & dbg_cmd_write))  & (i == WrPtr[DEPTH_PTR-1:0])) |
     245              :                                ((dma_address_error | dma_alignment_error) & (i == RdPtr[DEPTH_PTR-1:0])) |
     246              :                                (dccm_dma_rvalid & (i == DEPTH_PTR'(dccm_dma_rtag[2:0]))) |
     247              :                                (iccm_dma_rvalid & (i == DEPTH_PTR'(iccm_dma_rtag[2:0])));
     248              :       assign fifo_pend_en[i] = (dma_dccm_req | dma_iccm_req) & ~dma_mem_write & (i == RdPtr[DEPTH_PTR-1:0]);
     249              :       assign fifo_error_en[i] = ((dma_address_error | dma_alignment_error | dma_dbg_cmd_error) & (i == RdPtr[DEPTH_PTR-1:0])) |
     250              :                                 ((dccm_dma_rvalid & dccm_dma_ecc_error) & (i == DEPTH_PTR'(dccm_dma_rtag[2:0]))) |
     251              :                                 ((iccm_dma_rvalid & iccm_dma_ecc_error) & (i == DEPTH_PTR'(iccm_dma_rtag[2:0])));
     252              :       assign fifo_error_bus_en[i] = (((|fifo_error_in[i][1:0]) & fifo_error_en[i]) | (|fifo_error[i])) & dma_bus_clk_en;
     253              :       assign fifo_done_en[i] = ((|fifo_error[i] | fifo_error_en[i] | ((dma_dccm_req | dma_iccm_req) & dma_mem_write)) & (i == RdPtr[DEPTH_PTR-1:0])) |
     254              :                                (dccm_dma_rvalid & (i == DEPTH_PTR'(dccm_dma_rtag[2:0]))) |
     255              :                                (iccm_dma_rvalid & (i == DEPTH_PTR'(iccm_dma_rtag[2:0])));
     256              :       assign fifo_done_bus_en[i] = (fifo_done_en[i] | fifo_done[i]) & dma_bus_clk_en;
     257              :       assign fifo_reset[i] = (((bus_rsp_sent | bus_posted_write_done) & dma_bus_clk_en) | dma_dbg_cmd_done) & (i == RspPtr[DEPTH_PTR-1:0]);
     258              :       assign fifo_error_in[i]   = (dccm_dma_rvalid & (i == DEPTH_PTR'(dccm_dma_rtag[2:0]))) ? {1'b0,dccm_dma_ecc_error} : (iccm_dma_rvalid & (i == DEPTH_PTR'(iccm_dma_rtag[2:0]))) ? {1'b0,iccm_dma_ecc_error}  :
     259              :                                                                                                                 {(dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error};
     260              :       assign fifo_data_in[i]   = (fifo_error_en[i] & (|fifo_error_in[i])) ? {32'b0,fifo_addr[i]} :
     261              :                                                         ((dccm_dma_rvalid & (i == DEPTH_PTR'(dccm_dma_rtag[2:0])))  ? dccm_dma_rdata[63:0] : (iccm_dma_rvalid & (i == DEPTH_PTR'(iccm_dma_rtag[2:0]))) ? iccm_dma_rdata[63:0] :
     262              :                                                                                                                                                        (dbg_cmd_valid ? {2{dma_dbg_mem_wrdata[31:0]}} : bus_cmd_wdata[63:0]));
     263              : 
     264              :       rvdffsc #(1) fifo_valid_dff (.din(1'b1), .dout(fifo_valid[i]), .en(fifo_cmd_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
     265              :       rvdffsc #(2) fifo_error_dff (.din(fifo_error_in[i]), .dout(fifo_error[i]), .en(fifo_error_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
     266              :       rvdffsc #(1) fifo_error_bus_dff (.din(1'b1), .dout(fifo_error_bus[i]), .en(fifo_error_bus_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
     267              :       rvdffsc #(1) fifo_rpend_dff (.din(1'b1), .dout(fifo_rpend[i]), .en(fifo_pend_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
     268              :       rvdffsc #(1) fifo_done_dff (.din(1'b1), .dout(fifo_done[i]), .en(fifo_done_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
     269              :       rvdffsc #(1) fifo_done_bus_dff (.din(1'b1), .dout(fifo_done_bus[i]), .en(fifo_done_bus_en[i]), .clear(fifo_reset[i]), .clk(dma_free_clk), .*);
     270              :       rvdffe  #(32) fifo_addr_dff (.din(fifo_addr_in[31:0]), .dout(fifo_addr[i]), .en(fifo_cmd_en[i]), .*);
     271              :       rvdffs  #(3) fifo_sz_dff (.din(fifo_sz_in[2:0]), .dout(fifo_sz[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
     272              :       rvdffs  #(8) fifo_byteen_dff (.din(fifo_byteen_in[7:0]), .dout(fifo_byteen[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
     273              :       rvdffs  #(1) fifo_write_dff (.din(fifo_write_in), .dout(fifo_write[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
     274              :       rvdffs  #(1) fifo_posted_write_dff (.din(fifo_posted_write_in), .dout(fifo_posted_write[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
     275              :       rvdffs  #(1) fifo_dbg_dff (.din(fifo_dbg_in), .dout(fifo_dbg[i]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
     276              :       rvdffe  #(64) fifo_data_dff (.din(fifo_data_in[i]), .dout(fifo_data[i]), .en(fifo_data_en[i]), .*);
     277              :       rvdffs  #(pt.DMA_BUS_TAG) fifo_tag_dff(.din(bus_cmd_tag[pt.DMA_BUS_TAG-1:0]), .dout(fifo_tag[i][pt.DMA_BUS_TAG-1:0]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
     278              :       rvdffs  #(pt.DMA_BUS_ID) fifo_mid_dff(.din(bus_cmd_mid[pt.DMA_BUS_ID-1:0]), .dout(fifo_mid[i][pt.DMA_BUS_ID-1:0]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
     279              :       rvdffs  #(pt.DMA_BUS_PRTY) fifo_prty_dff(.din(bus_cmd_prty[pt.DMA_BUS_PRTY-1:0]), .dout(fifo_prty[i][pt.DMA_BUS_PRTY-1:0]), .en(fifo_cmd_en[i]), .clk(dma_buffer_c1_clk), .*);
     280              :    end
     281              : 
     282              :    // Pointer logic
     283              :    assign NxtWrPtr[DEPTH_PTR-1:0] = (WrPtr[DEPTH_PTR-1:0] == (DEPTH-1)) ? '0 : WrPtr[DEPTH_PTR-1:0] + 1'b1;
     284              :    assign NxtRdPtr[DEPTH_PTR-1:0] = (RdPtr[DEPTH_PTR-1:0] == (DEPTH-1)) ? '0 : RdPtr[DEPTH_PTR-1:0] + 1'b1;
     285              :    assign NxtRspPtr[DEPTH_PTR-1:0] = (RspPtr[DEPTH_PTR-1:0] == (DEPTH-1)) ? '0 : RspPtr[DEPTH_PTR-1:0] + 1'b1;
     286              : 
     287              :    assign WrPtrEn = |fifo_cmd_en[DEPTH-1:0];
     288              :    assign RdPtrEn = dma_dccm_req | dma_iccm_req | (dma_address_error | dma_alignment_error | dma_dbg_cmd_error);
     289              :    assign RspPtrEn = (dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & dma_bus_clk_en);
     290              : 
     291              :    rvdffs #(DEPTH_PTR) WrPtr_dff(.din(NxtWrPtr[DEPTH_PTR-1:0]), .dout(WrPtr[DEPTH_PTR-1:0]), .en(WrPtrEn), .clk(dma_free_clk), .*);
     292              :    rvdffs #(DEPTH_PTR) RdPtr_dff(.din(NxtRdPtr[DEPTH_PTR-1:0]), .dout(RdPtr[DEPTH_PTR-1:0]), .en(RdPtrEn), .clk(dma_free_clk), .*);
     293              :    rvdffs #(DEPTH_PTR) RspPtr_dff(.din(NxtRspPtr[DEPTH_PTR-1:0]), .dout(RspPtr[DEPTH_PTR-1:0]), .en(RspPtrEn), .clk(dma_free_clk), .*);
     294              : 
     295              :    // Miscellaneous signals
     296              :    assign fifo_full = fifo_full_spec_bus;
     297              : 
     298          347 :    always_comb begin
     299          347 :       num_fifo_vld[3:0] = {3'b0,bus_cmd_sent} - {3'b0,bus_rsp_sent};
     300          347 :       for (int i=0; i<DEPTH; i++) begin
     301         1735 :          num_fifo_vld[3:0] += {3'b0,fifo_valid[i]};
     302              :       end
     303              :    end
     304              :    assign fifo_full_spec          = (num_fifo_vld[3:0] >= DEPTH);
     305              : 
     306              :    assign dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus);
     307              : 
     308              :    // Error logic
     309              :    assign dma_address_error = fifo_valid[RdPtr] & ~fifo_done[RdPtr] & ~fifo_dbg[RdPtr] & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm));    // request not for ICCM or DCCM
     310              :    assign dma_alignment_error = fifo_valid[RdPtr] & ~fifo_done[RdPtr] & ~fifo_dbg[RdPtr] & ~dma_address_error &
     311              :                                 (((dma_mem_sz_int[2:0] == 3'h1) & dma_mem_addr_int[0])                                                             |    // HW size but unaligned
     312              :                                  ((dma_mem_sz_int[2:0] == 3'h2) & (|dma_mem_addr_int[1:0]))                                                        |    // W size but unaligned
     313              :                                  ((dma_mem_sz_int[2:0] == 3'h3) & (|dma_mem_addr_int[2:0]))                                                        |    // DW size but unaligned
     314              :                                  (dma_mem_addr_in_iccm & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11)))                       |    // ICCM access not word size
     315              :                                  (dma_mem_addr_in_dccm & dma_mem_write & ~((dma_mem_sz_int[1:0] == 2'b10) | (dma_mem_sz_int[1:0] == 2'b11)))       |    // DCCM write not word size
     316              :                                  (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2) & (dma_mem_addr_int[2:0] == 3'h0) & (dma_mem_byteen[3:0] != 4'hf)) |    // Write byte enables not aligned for word store
     317              :                                  (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h2) & (dma_mem_addr_int[2:0] == 3'h4) & (dma_mem_byteen[7:4] != 4'hf)) |    // Write byte enables not aligned for word store
     318              :                                  (dma_mem_write & (dma_mem_sz_int[2:0] == 3'h3) & ~((dma_mem_byteen[7:0] == 8'h0f) | (dma_mem_byteen[7:0] == 8'hf0) | (dma_mem_byteen[7:0] == 8'hff)))); // Write byte enables not aligned for dword store
     319              : 
     320              : 
     321              :    //Dbg outputs
     322              :    assign dma_dbg_ready    = fifo_empty & dbg_dma_bubble;
     323              :    assign dma_dbg_cmd_done = (fifo_valid[RspPtr] & fifo_dbg[RspPtr] & fifo_done[RspPtr]);
     324              :    assign dma_dbg_cmd_fail     = (|fifo_error[RspPtr] & dma_dbg_cmd_done) ;
     325              : 
     326              :    assign dma_dbg_sz[1:0]          = fifo_sz[RspPtr][1:0];
     327              :    assign dma_dbg_addr[1:0]        = fifo_addr[RspPtr][1:0];
     328              :    assign dma_dbg_mem_rddata[31:0] = fifo_addr[RspPtr][2] ? fifo_data[RspPtr][63:32] : fifo_data[RspPtr][31:0];
     329              :    assign dma_dbg_rddata[31:0]     = ({32{(dma_dbg_sz[1:0] == 2'h0)}} & ((dma_dbg_mem_rddata[31:0] >> 8*dma_dbg_addr[1:0]) & 32'hff)) |
     330              :                                      ({32{(dma_dbg_sz[1:0] == 2'h1)}} & ((dma_dbg_mem_rddata[31:0] >> 16*dma_dbg_addr[1]) & 32'hffff)) |
     331              :                                      ({32{(dma_dbg_sz[1:0] == 2'h2)}} & dma_dbg_mem_rddata[31:0]);
     332              : 
     333              :    assign dma_dbg_cmd_error = fifo_valid[RdPtr] & ~fifo_done[RdPtr] & fifo_dbg[RdPtr] &
     334              :                                  ((~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm | dma_mem_addr_in_pic)) |             // Address outside of ICCM/DCCM/PIC
     335              :                                   ((dma_mem_addr_in_iccm | dma_mem_addr_in_pic) & (dma_mem_sz_int[1:0] != 2'b10)));    // Only word accesses allowed for ICCM/PIC
     336              : 
     337              :    assign dma_dbg_mem_wrdata[31:0] = ({32{dbg_cmd_size[1:0] == 2'h0}} & {4{dbg_cmd_wrdata[7:0]}}) |
     338              :                                      ({32{dbg_cmd_size[1:0] == 2'h1}} & {2{dbg_cmd_wrdata[15:0]}}) |
     339              :                                      ({32{dbg_cmd_size[1:0] == 2'h2}} & dbg_cmd_wrdata[31:0]);
     340              : 
     341              :    // Block the decode if fifo full
     342              :    assign dma_dccm_stall_any = dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr);
     343              :    assign dma_iccm_stall_any = dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr);
     344              : 
     345              :    // Used to indicate ready to debug
     346              :    assign fifo_empty     = ~((|(fifo_valid[DEPTH-1:0])) | bus_cmd_sent);
     347              : 
     348              :    // Nack counter, stall the lsu pipe if 7 nacks
     349              :    assign dma_nack_count_csr[2:0] = dec_tlu_dma_qos_prty[2:0];
     350              :    assign dma_nack_count_d[2:0] = (dma_nack_count[2:0] >= dma_nack_count_csr[2:0]) ? ({3{~(dma_dccm_req | dma_iccm_req)}} & dma_nack_count[2:0]) :
     351              :                                                                                     (dma_mem_req & ~(dma_dccm_req | dma_iccm_req)) ? (dma_nack_count[2:0] + 1'b1) : 3'b0;
     352              : 
     353              :    rvdffs #(3) nack_count_dff(.din(dma_nack_count_d[2:0]), .dout(dma_nack_count[2:0]), .en(dma_mem_req), .clk(dma_free_clk), .*);
     354              : 
     355              :    // Core outputs
     356              :    assign dma_mem_req         = fifo_valid[RdPtr] & ~fifo_rpend[RdPtr] & ~fifo_done[RdPtr] & ~(dma_address_error | dma_alignment_error | dma_dbg_cmd_error);
     357              :    assign dma_dccm_req        = dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & dccm_ready;
     358              :    assign dma_iccm_req        = dma_mem_req & dma_mem_addr_in_iccm & iccm_ready;
     359              :    assign dma_mem_tag[2:0]    = 3'(RdPtr);
     360              :    assign dma_mem_addr_int[31:0] = fifo_addr[RdPtr];
     361              :    assign dma_mem_sz_int[2:0] = fifo_sz[RdPtr];
     362              :    assign dma_mem_addr[31:0]  = (dma_mem_write & ~fifo_dbg[RdPtr] & (dma_mem_byteen[7:0] == 8'hf0)) ? {dma_mem_addr_int[31:3],1'b1,dma_mem_addr_int[1:0]} : dma_mem_addr_int[31:0];
     363              :    assign dma_mem_sz[2:0]     = (dma_mem_write & ~fifo_dbg[RdPtr] & ((dma_mem_byteen[7:0] == 8'h0f) | (dma_mem_byteen[7:0] == 8'hf0))) ? 3'h2 : dma_mem_sz_int[2:0];
     364              :    assign dma_mem_byteen[7:0] = fifo_byteen[RdPtr];
     365              :    assign dma_mem_write       = fifo_write[RdPtr];
     366              :    assign dma_mem_wdata[63:0] = fifo_data[RdPtr];
     367              : 
     368              :    // PMU outputs
     369              :    assign dma_pmu_dccm_read   = dma_dccm_req & ~dma_mem_write;
     370              :    assign dma_pmu_dccm_write  = dma_dccm_req & dma_mem_write;
     371              :    assign dma_pmu_any_read    = (dma_dccm_req | dma_iccm_req) & ~dma_mem_write;
     372              :    assign dma_pmu_any_write   = (dma_dccm_req | dma_iccm_req) & dma_mem_write;
     373              : 
     374              :    // Address check  dccm
     375              :    if (pt.DCCM_ENABLE) begin: Gen_dccm_enable
     376              :       rvrangecheck #(.CCM_SADR(pt.DCCM_SADR),
     377              :                      .CCM_SIZE(pt.DCCM_SIZE)) addr_dccm_rangecheck (
     378              :          .addr(dma_mem_addr_int[31:0]),
     379              :          .in_range(dma_mem_addr_in_dccm),
     380              :          .in_region(dma_mem_addr_in_dccm_region_nc)
     381              :       );
     382              :    end else begin: Gen_dccm_disable
     383              :       assign dma_mem_addr_in_dccm = '0;
     384              :       assign dma_mem_addr_in_dccm_region_nc = '0;
     385              :    end // else: !if(pt.ICCM_ENABLE)
     386              : 
     387              :    // Address check  iccm
     388              :    if (pt.ICCM_ENABLE) begin: Gen_iccm_enable
     389              :       rvrangecheck #(.CCM_SADR(pt.ICCM_SADR),
     390              :                      .CCM_SIZE(pt.ICCM_SIZE)) addr_iccm_rangecheck (
     391              :          .addr(dma_mem_addr_int[31:0]),
     392              :          .in_range(dma_mem_addr_in_iccm),
     393              :          .in_region(dma_mem_addr_in_iccm_region_nc)
     394              :       );
     395              :    end else begin: Gen_iccm_disable
     396              :       assign dma_mem_addr_in_iccm = '0;
     397              :       assign dma_mem_addr_in_iccm_region_nc = '0;
     398              :    end // else: !if(pt.ICCM_ENABLE)
     399              : 
     400              : 
     401              :    // PIC memory address check
     402              :    rvrangecheck #(.CCM_SADR(pt.PIC_BASE_ADDR),
     403              :                   .CCM_SIZE(pt.PIC_SIZE)) addr_pic_rangecheck (
     404              :       .addr(dma_mem_addr_int[31:0]),
     405              :       .in_range(dma_mem_addr_in_pic),
     406              :       .in_region(dma_mem_addr_in_pic_region_nc)
     407              :     );
     408              : 
     409              :    // Inputs
     410              :    rvdff_fpga #(1) fifo_full_bus_ff     (.din(fifo_full_spec),   .dout(fifo_full_spec_bus), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
     411              :    rvdff_fpga #(1) dbg_dma_bubble_ff    (.din(dbg_dma_bubble),   .dout(dbg_dma_bubble_bus), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
     412              :    rvdff      #(1) dma_dbg_cmd_doneff   (.din(dma_dbg_cmd_done), .dout(dma_dbg_cmd_done_q), .clk(free_clk), .*);
     413              : 
     414              :    // Clock Gating logic
     415              :    assign dma_buffer_c1_clken = (bus_cmd_valid & dma_bus_clk_en) | dbg_cmd_valid | clk_override;
     416              :    assign dma_free_clken = (bus_cmd_valid | bus_rsp_valid | dbg_cmd_valid | dma_dbg_cmd_done | dma_dbg_cmd_done_q | (|fifo_valid[DEPTH-1:0]) | clk_override);
     417              : 
     418              :    rvoclkhdr dma_buffer_c1cgc ( .en(dma_buffer_c1_clken), .l1clk(dma_buffer_c1_clk), .* );
     419              :    rvoclkhdr dma_free_cgc (.en(dma_free_clken), .l1clk(dma_free_clk), .*);
     420              : 
     421              : `ifdef RV_FPGA_OPTIMIZE
     422              :    assign dma_bus_clk = 1'b0;
     423              : `else
     424              :    rvclkhdr  dma_bus_cgc (.en(dma_bus_clk_en), .l1clk(dma_bus_clk), .*);
     425              : `endif
     426              : 
     427              :    // Write channel buffer
     428              :    assign wrbuf_en       = dma_axi_awvalid & dma_axi_awready;
     429              :    assign wrbuf_data_en  = dma_axi_wvalid & dma_axi_wready;
     430              :    assign wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write;
     431              :    assign wrbuf_rst      = wrbuf_cmd_sent & ~wrbuf_en;
     432              :    assign wrbuf_data_rst = wrbuf_cmd_sent & ~wrbuf_data_en;
     433              : 
     434              :    rvdffsc_fpga  #(.WIDTH(1))              wrbuf_vldff       (.din(1'b1), .dout(wrbuf_vld),      .en(wrbuf_en),      .clear(wrbuf_rst),      .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
     435              :    rvdffsc_fpga  #(.WIDTH(1))              wrbuf_data_vldff  (.din(1'b1), .dout(wrbuf_data_vld), .en(wrbuf_data_en), .clear(wrbuf_data_rst), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
     436              :    rvdffs_fpga   #(.WIDTH(pt.DMA_BUS_TAG)) wrbuf_tagff       (.din(dma_axi_awid[pt.DMA_BUS_TAG-1:0]), .dout(wrbuf_tag[pt.DMA_BUS_TAG-1:0]), .en(wrbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
     437              :    rvdffs_fpga   #(.WIDTH(3))              wrbuf_szff        (.din(dma_axi_awsize[2:0]),  .dout(wrbuf_sz[2:0]),     .en(wrbuf_en),                  .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
     438              :    rvdffe        #(.WIDTH(32))             wrbuf_addrff      (.din(dma_axi_awaddr[31:0]), .dout(wrbuf_addr[31:0]),  .en(wrbuf_en & dma_bus_clk_en), .*);
     439              :    rvdffe        #(.WIDTH(64))             wrbuf_dataff      (.din(dma_axi_wdata[63:0]),  .dout(wrbuf_data[63:0]),  .en(wrbuf_data_en & dma_bus_clk_en), .*);
     440              :    rvdffs_fpga   #(.WIDTH(8))              wrbuf_byteenff    (.din(dma_axi_wstrb[7:0]),   .dout(wrbuf_byteen[7:0]), .en(wrbuf_data_en),             .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
     441              : 
     442              :    // Read channel buffer
     443              :    assign rdbuf_en    = dma_axi_arvalid & dma_axi_arready;
     444              :    assign rdbuf_cmd_sent = bus_cmd_sent & ~bus_cmd_write;
     445              :    assign rdbuf_rst   = rdbuf_cmd_sent & ~rdbuf_en;
     446              : 
     447              :    rvdffsc_fpga  #(.WIDTH(1))              rdbuf_vldff  (.din(1'b1), .dout(rdbuf_vld), .en(rdbuf_en), .clear(rdbuf_rst), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
     448              :    rvdffs_fpga   #(.WIDTH(pt.DMA_BUS_TAG)) rdbuf_tagff  (.din(dma_axi_arid[pt.DMA_BUS_TAG-1:0]), .dout(rdbuf_tag[pt.DMA_BUS_TAG-1:0]), .en(rdbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
     449              :    rvdffs_fpga   #(.WIDTH(3))              rdbuf_szff   (.din(dma_axi_arsize[2:0]),  .dout(rdbuf_sz[2:0]),    .en(rdbuf_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
     450              :    rvdffe       #(.WIDTH(32))              rdbuf_addrff (.din(dma_axi_araddr[31:0]), .dout(rdbuf_addr[31:0]), .en(rdbuf_en & dma_bus_clk_en), .*);
     451              : 
     452              :    assign dma_axi_awready = ~(wrbuf_vld & ~wrbuf_cmd_sent);
     453              :    assign dma_axi_wready  = ~(wrbuf_data_vld & ~wrbuf_cmd_sent);
     454              :    assign dma_axi_arready = ~(rdbuf_vld & ~rdbuf_cmd_sent);
     455              : 
     456              :    //Generate a single request from read/write channel
     457              :    assign bus_cmd_valid                     = (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld;
     458              :    assign bus_cmd_sent                      = bus_cmd_valid & dma_fifo_ready;
     459              :    assign bus_cmd_write                     = axi_mstr_sel;
     460              :    assign bus_cmd_posted_write              = '0;
     461              :    assign bus_cmd_addr[31:0]                = axi_mstr_sel ? wrbuf_addr[31:0] : rdbuf_addr[31:0];
     462              :    assign bus_cmd_sz[2:0]                   = axi_mstr_sel ? wrbuf_sz[2:0] : rdbuf_sz[2:0];
     463              :    assign bus_cmd_wdata[63:0]               = wrbuf_data[63:0];
     464              :    assign bus_cmd_byteen[7:0]               = wrbuf_byteen[7:0];
     465              :    assign bus_cmd_tag[pt.DMA_BUS_TAG-1:0]   = axi_mstr_sel ? wrbuf_tag[pt.DMA_BUS_TAG-1:0] : rdbuf_tag[pt.DMA_BUS_TAG-1:0];
     466              :    assign bus_cmd_mid[pt.DMA_BUS_ID-1:0]    = '0;
     467              :    assign bus_cmd_prty[pt.DMA_BUS_PRTY-1:0] = '0;
     468              : 
     469              :    // Sel=1 -> write has higher priority
     470              :    assign axi_mstr_sel     = (wrbuf_vld & wrbuf_data_vld & rdbuf_vld) ? axi_mstr_priority : (wrbuf_vld & wrbuf_data_vld);
     471              :    assign axi_mstr_prty_in = ~axi_mstr_priority;
     472              :    assign axi_mstr_prty_en = bus_cmd_sent;
     473              :    rvdffs_fpga #(.WIDTH(1)) mstr_prtyff(.din(axi_mstr_prty_in), .dout(axi_mstr_priority), .en(axi_mstr_prty_en), .clk(dma_bus_clk), .clken(dma_bus_clk_en), .rawclk(clk), .*);
     474              : 
     475              :    assign axi_rsp_valid                   = fifo_valid[RspPtr] & ~fifo_dbg[RspPtr] & fifo_done_bus[RspPtr];
     476              :    assign axi_rsp_rdata[63:0]             = fifo_data[RspPtr];
     477              :    assign axi_rsp_write                   = fifo_write[RspPtr];
     478              :    assign axi_rsp_error[1:0]              = fifo_error[RspPtr][0] ? 2'b10 : (fifo_error[RspPtr][1] ? 2'b11 : 2'b0);
     479              :    assign axi_rsp_tag[pt.DMA_BUS_TAG-1:0] = fifo_tag[RspPtr];
     480              : 
     481              :    // AXI response channel signals
     482              :    assign dma_axi_bvalid                  = axi_rsp_valid & axi_rsp_write;
     483              :    assign dma_axi_bresp[1:0]              = axi_rsp_error[1:0];
     484              :    assign dma_axi_bid[pt.DMA_BUS_TAG-1:0] = axi_rsp_tag[pt.DMA_BUS_TAG-1:0];
     485              : 
     486              :    assign dma_axi_rvalid                  = axi_rsp_valid & ~axi_rsp_write;
     487              :    assign dma_axi_rresp[1:0]              = axi_rsp_error;
     488              :    assign dma_axi_rdata[63:0]             = axi_rsp_rdata[63:0];
     489              :    assign dma_axi_rlast                   = 1'b1;
     490              :    assign dma_axi_rid[pt.DMA_BUS_TAG-1:0] = axi_rsp_tag[pt.DMA_BUS_TAG-1:0];
     491              : 
     492              :    assign bus_posted_write_done = 1'b0;
     493              :    assign bus_rsp_valid      = (dma_axi_bvalid | dma_axi_rvalid);
     494              :    assign bus_rsp_sent       = (dma_axi_bvalid & dma_axi_bready) | (dma_axi_rvalid & dma_axi_rready);
     495              : 
     496              :    assign dma_active  = wrbuf_vld | rdbuf_vld | (|fifo_valid[DEPTH-1:0]);
     497              : 
     498              : 
     499              : `ifdef RV_ASSERT_ON
     500              : 
     501              :    for (genvar i=0; i<DEPTH; i++) begin
     502              :       assert_fifo_done_and_novalid: assert #0 (~fifo_done[i] | fifo_valid[i]);
     503              :    end
     504              : 
     505              :    // Assertion to check awvalid stays stable during entire bus clock
     506              :    property dma_axi_awvalid_stable;
     507              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_awvalid != $past(dma_axi_awvalid)) |-> $past(dma_bus_clk_en);
     508              :    endproperty
     509              :    assert_dma_axi_awvalid_stable: assert property (dma_axi_awvalid_stable) else
     510              :       $display("DMA AXI awvalid changed in middle of bus clock");
     511              : 
     512              :    // Assertion to check awid stays stable during entire bus clock
     513              :    property dma_axi_awid_stable;
     514              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_awvalid & (dma_axi_awid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_awid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);
     515              :    endproperty
     516              :    assert_dma_axi_awid_stable: assert property (dma_axi_awid_stable) else
     517              :       $display("DMA AXI awid changed in middle of bus clock");
     518              : 
     519              :    // Assertion to check awaddr stays stable during entire bus clock
     520              :    property dma_axi_awaddr_stable;
     521              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_awvalid & (dma_axi_awaddr[31:0] != $past(dma_axi_awaddr[31:0]))) |-> $past(dma_bus_clk_en);
     522              :    endproperty
     523              :    assert_dma_axi_awaddr_stable: assert property (dma_axi_awaddr_stable) else
     524              :       $display("DMA AXI awaddr changed in middle of bus clock");
     525              : 
     526              :    // Assertion to check awsize stays stable during entire bus clock
     527              :    property dma_axi_awsize_stable;
     528              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_awvalid & (dma_axi_awsize[2:0] != $past(dma_axi_awsize[2:0]))) |-> $past(dma_bus_clk_en);
     529              :    endproperty
     530              :    assert_dma_axi_awsize_stable: assert property (dma_axi_awsize_stable) else
     531              :       $display("DMA AXI awsize changed in middle of bus clock");
     532              : 
     533              :    // Assertion to check wstrb stays stable during entire bus clock
     534              :    property dma_axi_wstrb_stable;
     535              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_wvalid & (dma_axi_wstrb[7:0] != $past(dma_axi_wstrb[7:0]))) |-> $past(dma_bus_clk_en);
     536              :    endproperty
     537              :    assert_dma_axi_wstrb_stable: assert property (dma_axi_wstrb_stable) else
     538              :       $display("DMA AXI wstrb changed in middle of bus clock");
     539              : 
     540              :    // Assertion to check wdata stays stable during entire bus clock
     541              :    property dma_axi_wdata_stable;
     542              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_wvalid & (dma_axi_wdata[63:0] != $past(dma_axi_wdata[63:0]))) |-> $past(dma_bus_clk_en);
     543              :    endproperty
     544              :    assert_dma_axi_wdata_stable: assert property (dma_axi_wdata_stable) else
     545              :       $display("DMA AXI wdata changed in middle of bus clock");
     546              : 
     547              :    // Assertion to check awvalid stays stable during entire bus clock
     548              :    property dma_axi_arvalid_stable;
     549              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_arvalid != $past(dma_axi_arvalid)) |-> $past(dma_bus_clk_en);
     550              :    endproperty
     551              :    assert_dma_axi_arvalid_stable: assert property (dma_axi_arvalid_stable) else
     552              :       $display("DMA AXI awvalid changed in middle of bus clock");
     553              : 
     554              :    // Assertion to check awid stays stable during entire bus clock
     555              :    property dma_axi_arid_stable;
     556              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_arvalid & (dma_axi_arid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_arid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);
     557              :    endproperty
     558              :    assert_dma_axi_arid_stable: assert property (dma_axi_arid_stable) else
     559              :       $display("DMA AXI awid changed in middle of bus clock");
     560              : 
     561              :    // Assertion to check awaddr stays stable during entire bus clock
     562              :    property dma_axi_araddr_stable;
     563              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_arvalid & (dma_axi_araddr[31:0] != $past(dma_axi_araddr[31:0]))) |-> $past(dma_bus_clk_en);
     564              :    endproperty
     565              :    assert_dma_axi_araddr_stable: assert property (dma_axi_araddr_stable) else
     566              :       $display("DMA AXI awaddr changed in middle of bus clock");
     567              : 
     568              :    // Assertion to check awsize stays stable during entire bus clock
     569              :    property dma_axi_arsize_stable;
     570              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_awvalid & (dma_axi_arsize[2:0] != $past(dma_axi_arsize[2:0]))) |-> $past(dma_bus_clk_en);
     571              :    endproperty
     572              :    assert_dma_axi_arsize_stable: assert property (dma_axi_arsize_stable) else
     573              :       $display("DMA AXI awsize changed in middle of bus clock");
     574              : 
     575              :    // Assertion to check bvalid stays stable during entire bus clock
     576              :    property dma_axi_bvalid_stable;
     577              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_bvalid != $past(dma_axi_bvalid)) |-> $past(dma_bus_clk_en);
     578              :    endproperty
     579              :    assert_dma_axi_bvalid_stable: assert property (dma_axi_bvalid_stable) else
     580              :       $display("DMA AXI bvalid changed in middle of bus clock");
     581              : 
     582              :    // Assertion to check bvalid stays stable if bready is low
     583              :    property dma_axi_bvalid_stable_till_bready;
     584              :       @(posedge clk) disable iff(~rst_l)  (~dma_axi_bvalid && $past(dma_axi_bvalid)) |-> $past(dma_axi_bready);
     585              :    endproperty
     586              :    assert_dma_axi_bvalid_stable_till_bready: assert property (dma_axi_bvalid_stable_till_bready) else
     587              :       $display("DMA AXI bvalid deasserted without bready");
     588              : 
     589              :    // Assertion to check bresp stays stable during entire bus clock
     590              :    property dma_axi_bresp_stable;
     591              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_bvalid & (dma_axi_bresp[1:0] != $past(dma_axi_bresp[1:0]))) |-> $past(dma_bus_clk_en);
     592              :    endproperty
     593              :    assert_dma_axi_bresp_stable: assert property (dma_axi_bresp_stable) else
     594              :       $display("DMA AXI bresp changed in middle of bus clock");
     595              : 
     596              :    // Assertion to check bid stays stable during entire bus clock
     597              :    property dma_axi_bid_stable;
     598              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_bvalid & (dma_axi_bid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_bid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);
     599              :    endproperty
     600              :    assert_dma_axi_bid_stable: assert property (dma_axi_bid_stable) else
     601              :       $display("DMA AXI bid changed in middle of bus clock");
     602              : 
     603              :    // Assertion to check rvalid stays stable during entire bus clock
     604              :    property dma_axi_rvalid_stable;
     605              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_rvalid != $past(dma_axi_rvalid)) |-> $past(dma_bus_clk_en);
     606              :    endproperty
     607              :    assert_dma_axi_rvalid_stable: assert property (dma_axi_rvalid_stable) else
     608              :       $display("DMA AXI bvalid changed in middle of bus clock");
     609              : 
     610              :    // Assertion to check rvalid stays stable if bready is low
     611              :    property dma_axi_rvalid_stable_till_ready;
     612              :       @(posedge clk) disable iff(~rst_l)  (~dma_axi_rvalid && $past(dma_axi_rvalid)) |-> $past(dma_axi_rready);
     613              :    endproperty
     614              :    assert_dma_axi_rvalid_stable_till_ready: assert property (dma_axi_rvalid_stable_till_ready) else
     615              :       $display("DMA AXI bvalid changed in middle of bus clock");
     616              : 
     617              :    // Assertion to check rresp stays stable during entire bus clock
     618              :    property dma_axi_rresp_stable;
     619              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_rvalid & (dma_axi_rresp[1:0] != $past(dma_axi_rresp[1:0]))) |-> $past(dma_bus_clk_en);
     620              :    endproperty
     621              :    assert_dma_axi_rresp_stable: assert property (dma_axi_rresp_stable) else
     622              :       $display("DMA AXI bresp changed in middle of bus clock");
     623              : 
     624              :    // Assertion to check rid stays stable during entire bus clock
     625              :    property dma_axi_rid_stable;
     626              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_rvalid & (dma_axi_rid[pt.DMA_BUS_TAG-1:0] != $past(dma_axi_rid[pt.DMA_BUS_TAG-1:0]))) |-> $past(dma_bus_clk_en);
     627              :    endproperty
     628              :    assert_dma_axi_rid_stable: assert property (dma_axi_rid_stable) else
     629              :       $display("DMA AXI bid changed in middle of bus clock");
     630              : 
     631              :    // Assertion to check rdata stays stable during entire bus clock
     632              :    property dma_axi_rdata_stable;
     633              :       @(posedge clk) disable iff(~rst_l)  (dma_axi_rvalid & (dma_axi_rdata[63:0] != $past(dma_axi_rdata[63:0]))) |-> $past(dma_bus_clk_en);
     634              :    endproperty
     635              :    assert_dma_axi_rdata_stable: assert property (dma_axi_rdata_stable) else
     636              :       $display("DMA AXI bid changed in middle of bus clock");
     637              : 
     638              : `endif
     639              : 
     640              : endmodule // el2_dma_ctrl