Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or it's affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 :
17 : //********************************************************************************
18 : // el2_dec_tlu_ctl.sv
19 : //
20 : //
21 : // Function: CSRs, Commit/WB, flushing, exceptions, interrupts
22 : // Comments:
23 : //
24 : //********************************************************************************
25 :
26 : module el2_dec_tlu_ctl
27 : import el2_pkg::*;
28 : #(
29 : `include "el2_param.vh"
30 : )
31 : (
32 61843746 : input logic clk,
33 61843746 : input logic free_clk,
34 61843746 : input logic free_l2clk,
35 316 : input logic rst_l,
36 0 : input logic scan_mode,
37 :
38 0 : input logic [31:1] rst_vec, // reset vector, from core pins
39 17 : input logic nmi_int, // nmi pin
40 0 : input logic [31:1] nmi_vec, // nmi vector
41 0 : input logic i_cpu_halt_req, // Asynchronous Halt request to CPU
42 0 : input logic i_cpu_run_req, // Asynchronous Restart request to CPU
43 :
44 4 : input logic lsu_fastint_stall_any, // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
45 :
46 :
47 : // perf counter inputs
48 6190087 : input logic ifu_pmu_instr_aligned, // aligned instructions
49 614530 : input logic ifu_pmu_fetch_stall, // fetch unit stalled
50 5893104 : input logic ifu_pmu_ic_miss, // icache miss
51 744124 : input logic ifu_pmu_ic_hit, // icache hit
52 0 : input logic ifu_pmu_bus_error, // Instruction side bus error
53 4463637 : input logic ifu_pmu_bus_busy, // Instruction side bus busy
54 10356722 : input logic ifu_pmu_bus_trxn, // Instruction side bus transaction
55 6190087 : input logic dec_pmu_instr_decoded, // decoded instructions
56 238142 : input logic dec_pmu_decode_stall, // decode stall
57 264 : input logic dec_pmu_presync_stall, // decode stall due to presync'd inst
58 14500 : input logic dec_pmu_postsync_stall,// decode stall due to postsync'd inst
59 59374 : input logic lsu_store_stall_any, // SB or WB is full, stall decode
60 0 : input logic dma_dccm_stall_any, // DMA stall of lsu
61 26 : input logic dma_iccm_stall_any, // DMA stall of ifu
62 409754 : input logic exu_pmu_i0_br_misp, // pipe 0 branch misp
63 2868109 : input logic exu_pmu_i0_br_ataken, // pipe 0 branch actual taken
64 3459682 : input logic exu_pmu_i0_pc4, // pipe 0 4 byte branch
65 1667379 : input logic lsu_pmu_bus_trxn, // D side bus transaction
66 36420 : input logic lsu_pmu_bus_misaligned, // D side bus misaligned
67 0 : input logic lsu_pmu_bus_error, // D side bus error
68 67818 : input logic lsu_pmu_bus_busy, // D side bus busy
69 891764 : input logic lsu_pmu_load_external_m, // D side bus load
70 806110 : input logic lsu_pmu_store_external_m, // D side bus store
71 0 : input logic dma_pmu_dccm_read, // DMA DCCM read
72 0 : input logic dma_pmu_dccm_write, // DMA DCCM write
73 0 : input logic dma_pmu_any_read, // DMA read
74 66 : input logic dma_pmu_any_write, // DMA write
75 :
76 24694 : input logic [31:1] lsu_fir_addr, // Fast int address
77 0 : input logic [1:0] lsu_fir_error, // Fast int lookup error
78 :
79 0 : input logic iccm_dma_sb_error, // I side dma single bit error
80 :
81 4 : input el2_lsu_error_pkt_t lsu_error_pkt_r, // lsu precise exception/error packet
82 4 : input logic lsu_single_ecc_error_incr, // LSU inc SB error counter
83 :
84 0 : input logic dec_pause_state, // Pause counter not zero
85 0 : input logic lsu_imprecise_error_store_any, // store bus error
86 0 : input logic lsu_imprecise_error_load_any, // store bus error
87 401 : input logic [31:0] lsu_imprecise_error_addr_any, // store bus error address
88 :
89 41991 : input logic dec_csr_wen_unq_d, // valid csr with write - for csr legal
90 83863 : input logic dec_csr_any_unq_d, // valid csr - for csr legal
91 906 : input logic [11:0] dec_csr_rdaddr_d, // read address for csr
92 :
93 41826 : input logic dec_csr_wen_r, // csr write enable at wb
94 1559962 : input logic [11:0] dec_csr_rdaddr_r, // read address for csr
95 406 : input logic [11:0] dec_csr_wraddr_r, // write address for csr
96 1640 : input logic [31:0] dec_csr_wrdata_r, // csr write data at wb
97 :
98 1346 : input logic dec_csr_stall_int_ff, // csr is mie/mstatus
99 :
100 6189442 : input logic dec_tlu_i0_valid_r, // pipe 0 op at e4 is valid
101 :
102 313 : input logic [31:1] exu_npc_r, // for NPC tracking
103 :
104 308 : input logic [31:1] dec_tlu_i0_pc_r, // for PC/NPC tracking
105 :
106 264 : input el2_trap_pkt_t dec_tlu_packet_r, // exceptions known at decode
107 :
108 18 : input logic [31:0] dec_illegal_inst, // For mtval
109 6190087 : input logic dec_i0_decode_d, // decode valid, used for clean icache diagnostics
110 :
111 : // branch info from pipe0 for errors or counter updates
112 2679213 : input logic [1:0] exu_i0_br_hist_r, // history
113 26468 : input logic exu_i0_br_error_r, // error
114 9608 : input logic exu_i0_br_start_error_r, // start error
115 2970681 : input logic exu_i0_br_valid_r, // valid
116 409754 : input logic exu_i0_br_mp_r, // mispredict
117 2381498 : input logic exu_i0_br_middle_r, // middle of bank
118 :
119 : // branch info from pipe1 for errors or counter updates
120 :
121 2110900 : input logic exu_i0_br_way_r, // way hit or repl
122 :
123 2091300 : output logic dec_tlu_core_empty, // core is empty
124 : // Debug start
125 0 : output logic dec_dbg_cmd_done, // abstract command done
126 0 : output logic dec_dbg_cmd_fail, // abstract command failed
127 0 : output logic dec_tlu_dbg_halted, // Core is halted and ready for debug command
128 0 : output logic dec_tlu_debug_mode, // Core is in debug mode
129 0 : output logic dec_tlu_resume_ack, // Resume acknowledge
130 0 : output logic dec_tlu_debug_stall, // stall decode while waiting on core to empty
131 :
132 0 : output logic dec_tlu_flush_noredir_r , // Tell fetch to idle on this flush
133 0 : output logic dec_tlu_mpc_halted_only, // Core is halted only due to MPC
134 0 : output logic dec_tlu_flush_leak_one_r, // single step
135 8 : output logic dec_tlu_flush_err_r, // iside perr/ecc rfpc. This is the D stage of the error
136 :
137 0 : output logic dec_tlu_flush_extint, // fast ext int started
138 0 : output logic [31:2] dec_tlu_meihap, // meihap for fast int
139 :
140 0 : input logic dbg_halt_req, // DM requests a halt
141 0 : input logic dbg_resume_req, // DM requests a resume
142 5892108 : input logic ifu_miss_state_idle, // I-side miss buffer empty
143 1346967 : input logic lsu_idle_any, // lsu is idle
144 159496 : input logic dec_div_active, // oop div is active
145 0 : output el2_trigger_pkt_t [3:0] trigger_pkt_any, // trigger info for trigger blocks
146 :
147 0 : input logic ifu_ic_error_start, // IC single bit error
148 8 : input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error
149 :
150 :
151 0 : input logic [70:0] ifu_ic_debug_rd_data, // diagnostic icache read data
152 0 : input logic ifu_ic_debug_rd_data_valid, // diagnostic icache read data valid
153 0 : output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
154 : // Debug end
155 :
156 0 : input logic [7:0] pic_claimid, // pic claimid for csr
157 0 : input logic [3:0] pic_pl, // pic priv level for csr
158 0 : input logic mhwakeup, // high priority external int, wakeup if halted
159 :
160 0 : input logic mexintpend, // external interrupt pending
161 18 : input logic timer_int, // timer interrupt pending
162 17 : input logic soft_int, // software interrupt pending
163 :
164 0 : output logic o_cpu_halt_status, // PMU interface, halted
165 0 : output logic o_cpu_halt_ack, // halt req ack
166 0 : output logic o_cpu_run_ack, // run req ack
167 0 : output logic o_debug_mode_status, // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
168 :
169 0 : input logic [31:4] core_id, // Core ID
170 :
171 : // external MPC halt/run interface
172 0 : input logic mpc_debug_halt_req, // Async halt request
173 316 : input logic mpc_debug_run_req, // Async run request
174 316 : input logic mpc_reset_run_req, // Run/halt after reset
175 0 : output logic mpc_debug_halt_ack, // Halt ack
176 316 : output logic mpc_debug_run_ack, // Run ack
177 0 : output logic debug_brkpt_status, // debug breakpoint
178 :
179 0 : output logic [3:0] dec_tlu_meicurpl, // to PIC
180 0 : output logic [3:0] dec_tlu_meipt, // to PIC
181 :
182 :
183 6941 : output logic [31:0] dec_csr_rddata_d, // csr read data at wb
184 83741 : output logic dec_csr_legal_d, // csr indicates legal operation
185 :
186 782203 : output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt, // branch pkt to bp
187 :
188 29654 : output logic dec_tlu_i0_kill_writeb_wb, // I0 is flushed, don't writeback any results to arch state
189 58638 : output logic dec_tlu_flush_lower_wb, // commit has a flush (exception, int, mispredict at e4)
190 6162256 : output logic dec_tlu_i0_commit_cmt, // committed an instruction
191 :
192 29654 : output logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state
193 58638 : output logic dec_tlu_flush_lower_r, // commit has a flush (exception, int)
194 24686 : output logic [31:1] dec_tlu_flush_path_r, // flush pc
195 18866 : output logic dec_tlu_fence_i_r, // flush is a fence_i rfnpc, flush icache
196 0 : output logic dec_tlu_wr_pause_r, // CSR write to pause reg is at R.
197 0 : output logic dec_tlu_flush_pause_r, // Flush is due to pause
198 :
199 510 : output logic dec_tlu_presync_d, // CSR read needs to be presync'd
200 20293 : output logic dec_tlu_postsync_d, // CSR needs to be presync'd
201 :
202 :
203 0 : output logic [31:0] dec_tlu_mrac_ff, // CSR for memory region control
204 :
205 0 : output logic dec_tlu_force_halt, // halt has been forced
206 :
207 340148 : output logic dec_tlu_perfcnt0, // toggles when pipe0 perf counter 0 has an event inc
208 514626 : output logic dec_tlu_perfcnt1, // toggles when pipe0 perf counter 1 has an event inc
209 312914 : output logic dec_tlu_perfcnt2, // toggles when pipe0 perf counter 2 has an event inc
210 48468 : output logic dec_tlu_perfcnt3, // toggles when pipe0 perf counter 3 has an event inc
211 :
212 5118 : output logic dec_tlu_i0_exc_valid_wb1, // pipe 0 exception valid
213 6161964 : output logic dec_tlu_i0_valid_wb1, // pipe 0 valid
214 28 : output logic dec_tlu_int_valid_wb1, // pipe 2 int valid
215 0 : output logic [4:0] dec_tlu_exc_cause_wb1, // exception or int cause
216 54 : output logic [31:0] dec_tlu_mtval_wb1, // MTVAL value
217 :
218 : // feature disable from mfdc
219 0 : output logic dec_tlu_external_ldfwd_disable, // disable external load forwarding
220 301 : output logic dec_tlu_sideeffect_posted_disable, // disable posted stores to side-effect address
221 8 : output logic dec_tlu_core_ecc_disable, // disable core ECC
222 0 : output logic dec_tlu_bpred_disable, // disable branch prediction
223 4 : output logic dec_tlu_wb_coalescing_disable, // disable writebuffer coalescing
224 0 : output logic dec_tlu_pipelining_disable, // disable pipelining
225 0 : output logic dec_tlu_trace_disable, // disable trace
226 321 : output logic [2:0] dec_tlu_dma_qos_prty, // DMA QoS priority coming from MFDC [18:16]
227 :
228 : // clock gating overrides from mcgc
229 0 : output logic dec_tlu_misc_clk_override, // override misc clock domain gating
230 0 : output logic dec_tlu_dec_clk_override, // override decode clock domain gating
231 0 : output logic dec_tlu_ifu_clk_override, // override fetch clock domain gating
232 0 : output logic dec_tlu_lsu_clk_override, // override load/store clock domain gating
233 0 : output logic dec_tlu_bus_clk_override, // override bus clock domain gating
234 0 : output logic dec_tlu_pic_clk_override, // override PIC clock domain gating
235 317 : output logic dec_tlu_picio_clk_override,// override PICIO clock domain gating
236 0 : output logic dec_tlu_dccm_clk_override, // override DCCM clock domain gating
237 0 : output logic dec_tlu_icm_clk_override, // override ICCM clock domain gating
238 :
239 : `ifdef RV_USER_MODE
240 :
241 : // Privilege mode
242 : // 0 - machine, 1 - user
243 866 : output logic priv_mode,
244 960 : output logic priv_mode_eff,
245 866 : output logic priv_mode_ns,
246 :
247 : // mseccfg CSR content for PMP
248 2 : output logic [2:0] mseccfg,
249 :
250 : `endif
251 :
252 : // pmp
253 0 : output el2_pmp_cfg_pkt_t pmp_pmpcfg [pt.PMP_ENTRIES],
254 : output logic [31:0] pmp_pmpaddr [pt.PMP_ENTRIES]
255 : );
256 :
257 12 : logic clk_override, e4e5_int_clk, nmi_fir_type, nmi_lsu_load_type, nmi_lsu_store_type, nmi_int_detected_f, nmi_lsu_load_type_f,
258 0 : nmi_lsu_store_type_f, allow_dbg_halt_csr_write, dbg_cmd_done_ns, i_cpu_run_req_d1_raw, debug_mode_status, lsu_single_ecc_error_r_d1,
259 2 : sel_npc_r, sel_npc_resume, ce_int,
260 0 : nmi_in_debug_mode, dpc_capture_npc, dpc_capture_pc, tdata_load, tdata_opcode, tdata_action, perfcnt_halted, tdata_chain,
261 0 : tdata_kill_write;
262 :
263 :
264 316 : logic reset_delayed, reset_detect, reset_detected;
265 0 : logic wr_mstatus_r, wr_mtvec_r, wr_mcyclel_r, wr_mcycleh_r,
266 0 : wr_minstretl_r, wr_minstreth_r, wr_mscratch_r, wr_mepc_r, wr_mcause_r, wr_mscause_r, wr_mtval_r,
267 0 : wr_mrac_r, wr_meihap_r, wr_meicurpl_r, wr_meipt_r, wr_dcsr_r,
268 0 : wr_dpc_r, wr_meicidpl_r, wr_meivt_r, wr_meicpct_r, wr_micect_r, wr_miccmect_r, wr_mfdht_r, wr_mfdhs_r,
269 4 : wr_mdccmect_r,wr_mhpme3_r, wr_mhpme4_r, wr_mhpme5_r, wr_mhpme6_r;
270 0 : logic wr_mpmc_r;
271 0 : logic [1:1] mpmc_b_ns, mpmc, mpmc_b;
272 0 : logic set_mie_pmu_fw_halt, fw_halted_ns, fw_halted;
273 0 : logic wr_mcountinhibit_r;
274 : `ifdef RV_USER_MODE
275 36 : logic wr_mcounteren_r;
276 6 : logic [5:0] mcounteren; // HPM6, HPM5, HPM4, HPM3, IR, CY
277 40 : logic wr_mseccfg_r;
278 2789 : logic [2:0] mseccfg_ns;
279 : `endif
280 0 : logic [6:0] mcountinhibit;
281 0 : logic wr_mtsel_r, wr_mtdata1_t0_r, wr_mtdata1_t1_r, wr_mtdata1_t2_r, wr_mtdata1_t3_r, wr_mtdata2_t0_r, wr_mtdata2_t1_r, wr_mtdata2_t2_r, wr_mtdata2_t3_r;
282 0 : logic [31:0] mtdata2_t0, mtdata2_t1, mtdata2_t2, mtdata2_t3, mtdata2_tsel_out, mtdata1_tsel_out;
283 0 : logic [9:0] mtdata1_t0_ns, mtdata1_t0, mtdata1_t1_ns, mtdata1_t1, mtdata1_t2_ns, mtdata1_t2, mtdata1_t3_ns, mtdata1_t3;
284 0 : logic [9:0] tdata_wrdata_r;
285 0 : logic [1:0] mtsel_ns, mtsel;
286 29654 : logic tlu_i0_kill_writeb_r;
287 : `ifdef RV_USER_MODE
288 55 : logic [3:0] mstatus_ns, mstatus; // MPRV, MPP (inverted! 0-M, 1-U), MPIE, MIE
289 : `else
290 3466 : logic [1:0] mstatus_ns, mstatus;
291 : `endif
292 0 : logic [1:0] mfdhs_ns, mfdhs;
293 0 : logic [31:0] force_halt_ctr, force_halt_ctr_f;
294 0 : logic force_halt;
295 0 : logic [5:0] mfdht, mfdht_ns;
296 892 : logic mstatus_mie_ns;
297 0 : logic [30:0] mtvec_ns, mtvec;
298 0 : logic [15:2] dcsr_ns, dcsr;
299 2 : logic [5:0] mip_ns, mip;
300 0 : logic [5:0] mie_ns, mie;
301 47082 : logic [31:0] mcyclel_ns, mcyclel;
302 0 : logic [31:0] mcycleh_ns, mcycleh;
303 14380 : logic [31:0] minstretl_ns, minstretl;
304 0 : logic [31:0] minstreth_ns, minstreth;
305 0 : logic [31:0] micect_ns, micect, miccmect_ns, miccmect, mdccmect_ns, mdccmect;
306 0 : logic [26:0] micect_inc, miccmect_inc, mdccmect_inc;
307 1334 : logic [31:0] mscratch;
308 46 : logic [31:0] mhpmc3, mhpmc3_ns, mhpmc4, mhpmc4_ns, mhpmc5, mhpmc5_ns, mhpmc6, mhpmc6_ns;
309 0 : logic [31:0] mhpmc3h, mhpmc3h_ns, mhpmc4h, mhpmc4h_ns, mhpmc5h, mhpmc5h_ns, mhpmc6h, mhpmc6h_ns;
310 0 : logic [9:0] mhpme3, mhpme4, mhpme5, mhpme6;
311 0 : logic [31:0] mrac;
312 0 : logic [9:2] meihap;
313 0 : logic [31:10] meivt;
314 0 : logic [3:0] meicurpl_ns, meicurpl;
315 0 : logic [3:0] meicidpl_ns, meicidpl;
316 0 : logic [3:0] meipt_ns, meipt;
317 0 : logic [31:0] mdseac;
318 0 : logic mdseac_locked_ns, mdseac_locked_f, mdseac_en, nmi_lsu_detected;
319 156 : logic [31:1] mepc_ns, mepc;
320 0 : logic [31:1] dpc_ns, dpc;
321 0 : logic [31:0] mcause_ns, mcause;
322 0 : logic [3:0] mscause_ns, mscause, mscause_type;
323 54 : logic [31:0] mtval_ns, mtval;
324 0 : logic dec_pause_state_f, dec_tlu_wr_pause_r_d1, pause_expired_r, pause_expired_wb;
325 58638 : logic tlu_flush_lower_r, tlu_flush_lower_r_d1;
326 280 : logic [31:1] tlu_flush_path_r, tlu_flush_path_r_d1;
327 6161964 : logic i0_valid_wb;
328 6162256 : logic tlu_i0_commit_cmt;
329 6 : logic [31:1] vectored_path, interrupt_path;
330 0 : logic [16:0] dicawics_ns, dicawics;
331 0 : logic wr_dicawics_r, wr_dicad0_r, wr_dicad1_r, wr_dicad0h_r;
332 0 : logic [31:0] dicad0_ns, dicad0, dicad0h_ns, dicad0h;
333 :
334 0 : logic [6:0] dicad1_ns, dicad1_raw;
335 0 : logic [31:0] dicad1;
336 15924 : logic ebreak_r, ebreak_to_debug_mode_r, ecall_r, illegal_r, mret_r, inst_acc_r, fence_i_r,
337 0 : ic_perr_r, iccm_sbecc_r, ebreak_to_debug_mode_r_d1, kill_ebreak_count_r, inst_acc_second_r;
338 0 : logic ce_int_ready, ext_int_ready, timer_int_ready, soft_int_ready, int_timer0_int_ready, int_timer1_int_ready, mhwakeup_ready,
339 0 : take_ext_int, take_ce_int, take_timer_int, take_soft_int, take_int_timer0_int, take_int_timer1_int, take_nmi, take_nmi_r_d1, int_timer0_int_possible, int_timer1_int_possible;
340 5146 : logic i0_exception_valid_r, interrupt_valid_r, i0_exception_valid_r_d1, interrupt_valid_r_d1, exc_or_int_valid_r, exc_or_int_valid_r_d1, mdccme_ce_req, miccme_ce_req, mice_ce_req;
341 52860 : logic synchronous_flush_r;
342 0 : logic [4:0] exc_cause_r, exc_cause_wb;
343 188615 : logic mcyclel_cout, mcyclel_cout_f, mcyclela_cout;
344 47083 : logic [31:0] mcyclel_inc;
345 0 : logic [31:0] mcycleh_inc;
346 :
347 57930 : logic minstretl_cout, minstretl_cout_f, minstret_enable, minstretl_cout_ns, minstretl_couta;
348 :
349 14380 : logic [31:0] minstretl_inc, minstretl_read;
350 0 : logic [31:0] minstreth_inc, minstreth_read;
351 312 : logic [31:1] pc_r, pc_r_d1, npc_r, npc_r_d1;
352 83743 : logic valid_csr;
353 28866 : logic rfpc_i0_r;
354 4 : logic lsu_i0_rfnpc_r;
355 2377932 : logic dec_tlu_br0_error_r, dec_tlu_br0_start_error_r, dec_tlu_br0_v_r;
356 40 : logic lsu_i0_exc_r, lsu_i0_exc_r_raw, lsu_exc_ma_r, lsu_exc_acc_r, lsu_exc_st_r,
357 57666 : lsu_exc_valid_r, lsu_exc_valid_r_raw, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1, block_interrupts;
358 6189442 : logic i0_trigger_eval_r;
359 :
360 0 : logic request_debug_mode_r, request_debug_mode_r_d1, request_debug_mode_done, request_debug_mode_done_f;
361 632 : logic take_halt, halt_taken, halt_taken_f, internal_dbg_halt_mode, dbg_tlu_halted_f, take_reset,
362 0 : dbg_tlu_halted, core_empty, lsu_idle_any_f, ifu_miss_state_idle_f, resume_ack_ns,
363 0 : debug_halt_req_f, debug_resume_req_f_raw, debug_resume_req_f, enter_debug_halt_req, dcsr_single_step_done, dcsr_single_step_done_f,
364 0 : debug_halt_req_d1, debug_halt_req_ns, dcsr_single_step_running, dcsr_single_step_running_f, internal_dbg_halt_timers;
365 :
366 0 : logic [3:0] i0_trigger_r, trigger_action, trigger_enabled,
367 0 : i0_trigger_chain_masked_r;
368 0 : logic i0_trigger_hit_r, i0_trigger_hit_raw_r, i0_trigger_action_r,
369 0 : trigger_hit_r_d1,
370 0 : mepc_trigger_hit_sel_pc_r;
371 317 : logic [3:0] update_hit_bit_r, i0_iside_trigger_has_pri_r,i0trigger_qual_r, i0_lsu_trigger_has_pri_r;
372 0 : logic cpu_halt_status, cpu_halt_ack, cpu_run_ack, ext_halt_pulse, i_cpu_halt_req_d1, i_cpu_run_req_d1;
373 :
374 0 : logic inst_acc_r_raw, trigger_hit_dmode_r, trigger_hit_dmode_r_d1;
375 0 : logic [9:0] mcgc, mcgc_ns, mcgc_int;
376 0 : logic [18:0] mfdc;
377 0 : logic i_cpu_halt_req_sync_qual, i_cpu_run_req_sync_qual, pmu_fw_halt_req_ns, pmu_fw_halt_req_f, int_timer_stalled,
378 0 : fw_halt_req, enter_pmu_fw_halt_req, pmu_fw_tlu_halted, pmu_fw_tlu_halted_f, internal_pmu_fw_halt_mode,
379 0 : internal_pmu_fw_halt_mode_f, int_timer0_int_hold, int_timer1_int_hold, int_timer0_int_hold_f, int_timer1_int_hold_f;
380 12 : logic nmi_int_delayed, nmi_int_detected;
381 0 : logic [3:0] trigger_execute, trigger_data, trigger_store;
382 0 : logic dec_tlu_pmu_fw_halted;
383 :
384 0 : logic mpc_run_state_ns, debug_brkpt_status_ns, mpc_debug_halt_ack_ns, mpc_debug_run_ack_ns, dbg_halt_state_ns, dbg_run_state_ns,
385 0 : dbg_halt_state_f, mpc_debug_halt_req_sync_f, mpc_debug_run_req_sync_f, mpc_halt_state_f, mpc_halt_state_ns, mpc_run_state_f, debug_brkpt_status_f,
386 0 : mpc_debug_halt_ack_f, mpc_debug_run_ack_f, dbg_run_state_f, mpc_debug_halt_req_sync_pulse,
387 0 : mpc_debug_run_req_sync_pulse, debug_brkpt_valid, debug_halt_req, debug_resume_req, dec_tlu_mpc_halted_only_ns;
388 0 : logic take_ext_int_start, ext_int_freeze, take_ext_int_start_d1, take_ext_int_start_d2,
389 4 : take_ext_int_start_d3, ext_int_freeze_d1, ignore_ext_int_due_to_lsu_stall;
390 32 : logic mcause_sel_nmi_store, mcause_sel_nmi_load, mcause_sel_nmi_ext, fast_int_meicpct;
391 0 : logic [1:0] mcause_fir_error_type;
392 0 : logic dbg_halt_req_held_ns, dbg_halt_req_held, dbg_halt_req_final;
393 6 : logic iccm_repair_state_ns, iccm_repair_state_d1, iccm_repair_state_rfnpc;
394 :
395 :
396 : // internal timer, isolated for size reasons
397 26 : logic [31:0] dec_timer_rddata_d;
398 0 : logic dec_timer_read_d, dec_timer_t0_pulse, dec_timer_t1_pulse;
399 :
400 : // PMP unit, isolated for size reasons
401 238 : logic [31:0] dec_pmp_rddata_d;
402 1738 : logic dec_pmp_read_d;
403 :
404 0 : logic nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync, mpc_debug_run_req_sync, mpc_debug_halt_req_sync_raw;
405 61843746 : logic csr_wr_clk;
406 0 : logic e4e5_clk, e4_valid, e5_valid, e4e5_valid, internal_dbg_halt_mode_f, internal_dbg_halt_mode_f2;
407 672506 : logic lsu_pmu_load_external_r, lsu_pmu_store_external_r;
408 0 : logic dec_tlu_flush_noredir_r_d1, dec_tlu_flush_pause_r_d1;
409 4 : logic lsu_single_ecc_error_r;
410 2 : logic [31:0] lsu_error_pkt_addr_r;
411 317 : logic mcyclel_cout_in;
412 6185912 : logic i0_valid_no_ebreak_ecall_r;
413 6158676 : logic minstret_enable_f;
414 58639 : logic sel_exu_npc_r, sel_flush_npc_r, sel_hold_npc_r;
415 6189442 : logic pc0_valid_r;
416 1991 : logic [15:0] mfdc_int, mfdc_ns;
417 392 : logic [31:0] mrac_in;
418 752 : logic [31:27] csr_sat;
419 0 : logic [8:6] dcsr_cause;
420 0 : logic enter_debug_halt_req_le, dcsr_cause_upgradeable;
421 0 : logic icache_rd_valid, icache_wr_valid, icache_rd_valid_f, icache_wr_valid_f;
422 48468 : logic [3:0] mhpmc_inc_r, mhpmc_inc_r_d1;
423 :
424 0 : logic [3:0][9:0] mhpme_vec;
425 340148 : logic mhpmc3_wr_en0, mhpmc3_wr_en1, mhpmc3_wr_en;
426 514626 : logic mhpmc4_wr_en0, mhpmc4_wr_en1, mhpmc4_wr_en;
427 312914 : logic mhpmc5_wr_en0, mhpmc5_wr_en1, mhpmc5_wr_en;
428 48468 : logic mhpmc6_wr_en0, mhpmc6_wr_en1, mhpmc6_wr_en;
429 340148 : logic mhpmc3h_wr_en0, mhpmc3h_wr_en;
430 514626 : logic mhpmc4h_wr_en0, mhpmc4h_wr_en;
431 312914 : logic mhpmc5h_wr_en0, mhpmc5h_wr_en;
432 48468 : logic mhpmc6h_wr_en0, mhpmc6h_wr_en;
433 46 : logic [63:0] mhpmc3_incr, mhpmc4_incr, mhpmc5_incr, mhpmc6_incr;
434 11315 : logic perfcnt_halted_d1, zero_event_r;
435 0 : logic [3:0] perfcnt_during_sleep;
436 28 : logic [9:0] event_r;
437 :
438 2151829 : el2_inst_pkt_t pmu_i0_itype_qual;
439 :
440 41826 : logic dec_csr_wen_r_mod;
441 :
442 668 : logic flush_clkvalid;
443 0 : logic sel_fir_addr;
444 268 : logic wr_mie_r;
445 3816 : logic mtval_capture_pc_r;
446 0 : logic mtval_capture_pc_plus2_r;
447 262 : logic mtval_capture_inst_r;
448 64 : logic mtval_capture_lsu_r;
449 1004 : logic mtval_clear_r;
450 0 : logic wr_mcgc_r;
451 24 : logic wr_mfdc_r;
452 0 : logic wr_mdeau_r;
453 0 : logic trigger_hit_for_dscr_cause_r_d1;
454 0 : logic conditionally_illegal;
455 :
456 701 : logic [3:0] ifu_mscause ;
457 8 : logic ifu_ic_error_start_f, ifu_iccm_rd_ecc_single_err_f;
458 :
459 : // CSR address decoder
460 :
461 : // files "csrdecode_m" (machine mode only) and "csrdecode_mu" (machine mode plus
462 : // user mode) are human readable that have all of the CSR decodes defined and
463 : // are part of the git repo. Modify these files as needed.
464 :
465 : // to generate all the equations below from "csrdecode" except legal equation:
466 :
467 : // 1) coredecode -in csrdecode > corecsrdecode.e
468 :
469 : // 2) espresso -Dso -oeqntott < corecsrdecode.e | addassign > csrequations
470 :
471 : // to generate the legal CSR equation below:
472 :
473 : // 1) coredecode -in csrdecode -legal > csrlegal.e
474 :
475 : // 2) espresso -Dso -oeqntott < csrlegal.e | addassign > csrlegal_equation
476 :
477 : // coredecode -in csrdecode > corecsrdecode.e; espresso -Dso -oeqntott < corecsrdecode.e | addassign > csrequations; coredecode -in csrdecode -legal > csrlegal.e; espresso -Dso -oeqntott csrlegal.e | addassign > csrlegal_equation
478 :
479 : `ifdef RV_USER_MODE
480 :
481 : `include "el2_dec_csr_equ_mu.svh"
482 :
483 612 : logic csr_acc_r; // CSR access error
484 16682 : logic csr_wr_usr_r; // Write to an unprivileged/user-level CSR
485 1131188 : logic csr_rd_usr_r; // REad from an unprivileged/user-level CSR
486 :
487 : `else
488 :
489 : `include "el2_dec_csr_equ_m.svh"
490 :
491 : `endif
492 :
493 : el2_dec_timer_ctl #(.pt(pt)) int_timers(.*);
494 : // end of internal timers
495 :
496 : el2_dec_pmp_ctl #(.pt(pt)) pmp(.*);
497 : // end of pmp
498 :
499 : assign clk_override = dec_tlu_dec_clk_override;
500 :
501 : // Async inputs to the core have to be sync'd to the core clock.
502 : rvsyncss #(7) syncro_ff(.*,
503 : .clk(free_clk),
504 : .din ({nmi_int, timer_int, soft_int, i_cpu_halt_req, i_cpu_run_req, mpc_debug_halt_req, mpc_debug_run_req}),
505 : .dout({nmi_int_sync, timer_int_sync, soft_int_sync, i_cpu_halt_req_sync, i_cpu_run_req_sync, mpc_debug_halt_req_sync_raw, mpc_debug_run_req_sync}));
506 :
507 : // for CSRs that have inpipe writes only
508 :
509 : rvoclkhdr csrwr_r_cgc ( .en(dec_csr_wen_r_mod | clk_override), .l1clk(csr_wr_clk), .* );
510 :
511 : assign e4_valid = dec_tlu_i0_valid_r;
512 : assign e4e5_valid = e4_valid | e5_valid;
513 : assign flush_clkvalid = internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid_r | interrupt_valid_r_d1 |
514 : reset_delayed | pause_expired_r | pause_expired_wb | ic_perr_r | iccm_sbecc_r |
515 : clk_override;
516 : rvoclkhdr e4e5_cgc ( .en(e4e5_valid | clk_override), .l1clk(e4e5_clk), .* );
517 : rvoclkhdr e4e5_int_cgc ( .en(e4e5_valid | flush_clkvalid), .l1clk(e4e5_int_clk), .* );
518 :
519 : rvdffie #(11) freeff (.*, .clk(free_l2clk),
520 : .din ({ifu_ic_error_start, ifu_iccm_rd_ecc_single_err, iccm_repair_state_ns, e4_valid, internal_dbg_halt_mode,
521 : lsu_pmu_load_external_m, lsu_pmu_store_external_m, tlu_flush_lower_r, tlu_i0_kill_writeb_r,
522 : internal_dbg_halt_mode_f, force_halt}),
523 : .dout({ifu_ic_error_start_f, ifu_iccm_rd_ecc_single_err_f, iccm_repair_state_d1, e5_valid, internal_dbg_halt_mode_f,
524 : lsu_pmu_load_external_r, lsu_pmu_store_external_r, tlu_flush_lower_r_d1, dec_tlu_i0_kill_writeb_wb,
525 : internal_dbg_halt_mode_f2, dec_tlu_force_halt}));
526 :
527 : assign dec_tlu_i0_kill_writeb_r = tlu_i0_kill_writeb_r;
528 :
529 : assign nmi_int_detected = (nmi_int_sync & ~nmi_int_delayed) | nmi_lsu_detected | (nmi_int_detected_f & ~take_nmi_r_d1) | nmi_fir_type;
530 : // if the first nmi is a lsu type, note it. If there's already an nmi pending, ignore. Simultaneous with FIR, drop.
531 : assign nmi_lsu_load_type = (nmi_lsu_detected & lsu_imprecise_error_load_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) |
532 : (nmi_lsu_load_type_f & ~take_nmi_r_d1);
533 : assign nmi_lsu_store_type = (nmi_lsu_detected & lsu_imprecise_error_store_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) |
534 : (nmi_lsu_store_type_f & ~take_nmi_r_d1);
535 :
536 : assign nmi_fir_type = ~nmi_int_detected_f & take_ext_int_start_d3 & |lsu_fir_error[1:0];
537 :
538 : // Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared
539 : assign nmi_lsu_detected = ~mdseac_locked_f & (lsu_imprecise_error_load_any | lsu_imprecise_error_store_any) & ~nmi_fir_type;
540 :
541 :
542 : localparam MSTATUS_MIE = 0;
543 : localparam int MSTATUS_MPIE = 1;
544 : `ifdef RV_USER_MODE
545 : localparam MSTATUS_MPP = 2;
546 : localparam MSTATUS_MPRV = 3;
547 : `endif
548 :
549 : localparam MIP_MCEIP = 5;
550 : localparam MIP_MITIP0 = 4;
551 : localparam MIP_MITIP1 = 3;
552 : localparam MIP_MEIP = 2;
553 : localparam MIP_MTIP = 1;
554 : localparam MIP_MSIP = 0;
555 :
556 : localparam MIE_MCEIE = 5;
557 : localparam MIE_MITIE0 = 4;
558 : localparam MIE_MITIE1 = 3;
559 : localparam MIE_MEIE = 2;
560 : localparam MIE_MTIE = 1;
561 : localparam MIE_MSIE = 0;
562 :
563 : localparam DCSR_EBREAKM = 15;
564 : localparam DCSR_STEPIE = 11;
565 : localparam DCSR_STOPC = 10;
566 : localparam DCSR_STEP = 2;
567 :
568 : `ifdef RV_USER_MODE
569 : localparam MCOUNTEREN_CY = 0;
570 : localparam MCOUNTEREN_IR = 1;
571 : localparam MCOUNTEREN_HPM3 = 2;
572 : localparam MCOUNTEREN_HPM4 = 3;
573 : localparam MCOUNTEREN_HPM5 = 4;
574 : localparam MCOUNTEREN_HPM6 = 5;
575 :
576 : localparam MSECCFG_RLB = 2;
577 : localparam MSECCFG_MMWP = 1;
578 : localparam MSECCFG_MML = 0;
579 : `endif
580 :
581 : assign reset_delayed = reset_detect ^ reset_detected;
582 :
583 : // ----------------------------------------------------------------------
584 : // MPC halt
585 : // - can interact with debugger halt and v-v
586 :
587 : // fast ints in progress have priority
588 : assign mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & ~ext_int_freeze_d1;
589 :
590 : rvdffie #(16) mpvhalt_ff (.*, .clk(free_l2clk),
591 : .din({1'b1, reset_detect,
592 : nmi_int_sync, nmi_int_detected, nmi_lsu_load_type, nmi_lsu_store_type,
593 : mpc_debug_halt_req_sync, mpc_debug_run_req_sync,
594 : mpc_halt_state_ns, mpc_run_state_ns, debug_brkpt_status_ns,
595 : mpc_debug_halt_ack_ns, mpc_debug_run_ack_ns,
596 : dbg_halt_state_ns, dbg_run_state_ns,
597 : dec_tlu_mpc_halted_only_ns}),
598 : .dout({reset_detect, reset_detected,
599 : nmi_int_delayed, nmi_int_detected_f, nmi_lsu_load_type_f, nmi_lsu_store_type_f,
600 : mpc_debug_halt_req_sync_f, mpc_debug_run_req_sync_f,
601 : mpc_halt_state_f, mpc_run_state_f, debug_brkpt_status_f,
602 : mpc_debug_halt_ack_f, mpc_debug_run_ack_f,
603 : dbg_halt_state_f, dbg_run_state_f,
604 : dec_tlu_mpc_halted_only}));
605 :
606 : // turn level sensitive requests into pulses
607 : assign mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & ~mpc_debug_halt_req_sync_f;
608 : assign mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & ~mpc_debug_run_req_sync_f;
609 :
610 : // states
611 : assign mpc_halt_state_ns = (mpc_halt_state_f | mpc_debug_halt_req_sync_pulse | (reset_delayed & ~mpc_reset_run_req)) & ~mpc_debug_run_req_sync;
612 : assign mpc_run_state_ns = (mpc_run_state_f | (mpc_debug_run_req_sync_pulse & ~mpc_debug_run_ack_f)) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f);
613 :
614 : // note, MPC halt can allow the jtag debugger to just start sending commands. When that happens, set the interal debugger halt state to prevent
615 : // MPC run from starting the core.
616 : assign dbg_halt_state_ns = (dbg_halt_state_f | (dbg_halt_req_final | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1)) & ~dbg_resume_req;
617 : assign dbg_run_state_ns = (dbg_run_state_f | dbg_resume_req) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f);
618 :
619 : // tell dbg we are only MPC halted
620 : assign dec_tlu_mpc_halted_only_ns = ~dbg_halt_state_f & mpc_halt_state_f;
621 :
622 : // this asserts from detection of bkpt until after we leave debug mode
623 : assign debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1;
624 : assign debug_brkpt_status_ns = (debug_brkpt_valid | debug_brkpt_status_f) & (internal_dbg_halt_mode & ~dcsr_single_step_running_f);
625 :
626 : // acks back to interface
627 : assign mpc_debug_halt_ack_ns = (mpc_halt_state_f & internal_dbg_halt_mode_f & mpc_debug_halt_req_sync & core_empty) | (mpc_debug_halt_ack_f & mpc_debug_halt_req_sync);
628 : assign mpc_debug_run_ack_ns = (mpc_debug_run_req_sync & ~internal_dbg_halt_mode & ~mpc_debug_halt_req_sync) | (mpc_debug_run_ack_f & mpc_debug_run_req_sync) ;
629 :
630 : // Pins
631 : assign mpc_debug_halt_ack = mpc_debug_halt_ack_f;
632 : assign mpc_debug_run_ack = mpc_debug_run_ack_f;
633 : assign debug_brkpt_status = debug_brkpt_status_f;
634 :
635 : // DBG halt req is a pulse, fast ext int in progress has priority
636 : assign dbg_halt_req_held_ns = (dbg_halt_req | dbg_halt_req_held) & ext_int_freeze_d1;
637 : assign dbg_halt_req_final = (dbg_halt_req | dbg_halt_req_held) & ~ext_int_freeze_d1;
638 :
639 : // combine MPC and DBG halt requests
640 : assign debug_halt_req = (dbg_halt_req_final | mpc_debug_halt_req_sync | (reset_delayed & ~mpc_reset_run_req)) & ~internal_dbg_halt_mode_f & ~ext_int_freeze_d1;
641 :
642 : assign debug_resume_req = ~debug_resume_req_f & // squash back to back resumes
643 : ((mpc_run_state_ns & ~dbg_halt_state_ns) | // MPC run req
644 : (dbg_run_state_ns & ~mpc_halt_state_ns)); // dbg request is a pulse
645 :
646 :
647 : // HALT
648 : // dbg/pmu/fw requests halt, service as soon as lsu is not blocking interrupts
649 : assign take_halt = (debug_halt_req_f | pmu_fw_halt_req_f) & ~synchronous_flush_r & ~mret_r & ~halt_taken_f & ~dec_tlu_flush_noredir_r_d1 & ~take_reset;
650 :
651 : // hold after we take a halt, so we don't keep taking halts
652 : assign halt_taken = (dec_tlu_flush_noredir_r_d1 & ~dec_tlu_flush_pause_r_d1 & ~take_ext_int_start_d1) | (halt_taken_f & ~dbg_tlu_halted_f & ~pmu_fw_tlu_halted_f & ~interrupt_valid_r_d1);
653 :
654 : // After doing halt flush (RFNPC) wait until core is idle before asserting a particular halt mode
655 : // It takes a cycle for mb_empty to assert after a fetch, take_halt covers that cycle
656 : assign core_empty = force_halt |
657 : (lsu_idle_any & lsu_idle_any_f & ifu_miss_state_idle & ifu_miss_state_idle_f & ~debug_halt_req & ~debug_halt_req_d1 & ~dec_div_active);
658 :
659 : assign dec_tlu_core_empty = core_empty;
660 :
661 : //--------------------------------------------------------------------------------
662 : // Debug start
663 : //
664 :
665 : assign enter_debug_halt_req = (~internal_dbg_halt_mode_f & debug_halt_req) | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1;
666 :
667 : // dbg halt state active from request until non-step resume
668 : assign internal_dbg_halt_mode = debug_halt_req_ns | (internal_dbg_halt_mode_f & ~(debug_resume_req_f & ~dcsr[DCSR_STEP]));
669 : // dbg halt can access csrs as long as we are not stepping
670 : assign allow_dbg_halt_csr_write = internal_dbg_halt_mode_f & ~dcsr_single_step_running_f;
671 :
672 :
673 : // hold debug_halt_req_ns high until we enter debug halt
674 : assign debug_halt_req_ns = enter_debug_halt_req | (debug_halt_req_f & ~dbg_tlu_halted);
675 :
676 : assign dbg_tlu_halted = (debug_halt_req_f & core_empty & halt_taken) | (dbg_tlu_halted_f & ~debug_resume_req_f);
677 :
678 : assign resume_ack_ns = (debug_resume_req_f & dbg_tlu_halted_f & dbg_run_state_ns);
679 :
680 : assign dcsr_single_step_done = dec_tlu_i0_valid_r & ~dec_tlu_dbg_halted & dcsr[DCSR_STEP] & ~rfpc_i0_r;
681 :
682 : assign dcsr_single_step_running = (debug_resume_req_f & dcsr[DCSR_STEP]) | (dcsr_single_step_running_f & ~dcsr_single_step_done_f);
683 :
684 : assign dbg_cmd_done_ns = dec_tlu_i0_valid_r & dec_tlu_dbg_halted;
685 :
686 : // used to hold off commits after an in-pipe debug mode request (triggers, DCSR)
687 : assign request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~dec_tlu_flush_lower_wb);
688 :
689 : assign request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f;
690 :
691 : rvdffie #(18) halt_ff (.*, .clk(free_l2clk),
692 : .din({dec_tlu_flush_noredir_r, halt_taken, lsu_idle_any, ifu_miss_state_idle, dbg_tlu_halted,
693 : resume_ack_ns, debug_halt_req_ns, debug_resume_req, trigger_hit_dmode_r,
694 : dcsr_single_step_done, debug_halt_req, dec_tlu_wr_pause_r, dec_pause_state,
695 : request_debug_mode_r, request_debug_mode_done, dcsr_single_step_running, dec_tlu_flush_pause_r,
696 : dbg_halt_req_held_ns}),
697 : .dout({dec_tlu_flush_noredir_r_d1, halt_taken_f, lsu_idle_any_f, ifu_miss_state_idle_f, dbg_tlu_halted_f,
698 : dec_tlu_resume_ack , debug_halt_req_f, debug_resume_req_f_raw, trigger_hit_dmode_r_d1,
699 : dcsr_single_step_done_f, debug_halt_req_d1, dec_tlu_wr_pause_r_d1, dec_pause_state_f,
700 : request_debug_mode_r_d1, request_debug_mode_done_f, dcsr_single_step_running_f, dec_tlu_flush_pause_r_d1,
701 : dbg_halt_req_held}));
702 :
703 : // MPC run collides with DBG halt, fix it here
704 : assign debug_resume_req_f = debug_resume_req_f_raw & ~dbg_halt_req;
705 :
706 : assign dec_tlu_debug_stall = debug_halt_req_f;
707 : assign dec_tlu_dbg_halted = dbg_tlu_halted_f;
708 : assign dec_tlu_debug_mode = internal_dbg_halt_mode_f;
709 : assign dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f;
710 :
711 : // kill fetch redirection on flush if going to halt, or if there's a fence during db-halt
712 : assign dec_tlu_flush_noredir_r = take_halt | (fence_i_r & internal_dbg_halt_mode) | dec_tlu_flush_pause_r | (i0_trigger_hit_r & trigger_hit_dmode_r) | take_ext_int_start;
713 :
714 : assign dec_tlu_flush_extint = take_ext_int_start;
715 :
716 : // 1 cycle after writing the PAUSE counter, flush with noredir to idle F1-D.
717 : assign dec_tlu_flush_pause_r = dec_tlu_wr_pause_r_d1 & ~interrupt_valid_r & ~take_ext_int_start;
718 :
719 : // detect end of pause counter and rfpc
720 : assign pause_expired_r = ~dec_pause_state & dec_pause_state_f & ~(ext_int_ready | ce_int_ready | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | nmi_int_detected | ext_int_freeze_d1) & ~interrupt_valid_r_d1 & ~debug_halt_req_f & ~pmu_fw_halt_req_f & ~halt_taken_f;
721 :
722 : assign dec_tlu_flush_leak_one_r = dec_tlu_flush_lower_r & dcsr[DCSR_STEP] & (dec_tlu_resume_ack | dcsr_single_step_running) & ~dec_tlu_flush_noredir_r;
723 : assign dec_tlu_flush_err_r = dec_tlu_flush_lower_r & (ic_perr_r | iccm_sbecc_r);
724 :
725 : // If DM attempts to access an illegal CSR, send cmd_fail back
726 : assign dec_dbg_cmd_done = dbg_cmd_done_ns;
727 : assign dec_dbg_cmd_fail = illegal_r & dec_dbg_cmd_done;
728 :
729 :
730 : //--------------------------------------------------------------------------------
731 : //--------------------------------------------------------------------------------
732 : // Triggers
733 : //
734 : localparam MTDATA1_DMODE = 9;
735 : localparam MTDATA1_SEL = 7;
736 : localparam MTDATA1_ACTION = 6;
737 : localparam MTDATA1_CHAIN = 5;
738 : localparam MTDATA1_MATCH = 4;
739 : localparam MTDATA1_M_ENABLED = 3;
740 : localparam MTDATA1_EXE = 2;
741 : localparam MTDATA1_ST = 1;
742 : localparam MTDATA1_LD = 0;
743 :
744 : // Prioritize trigger hits with other exceptions.
745 : //
746 : // Trigger should have highest priority except:
747 : // - trigger is an execute-data and there is an inst_access exception (lsu triggers won't fire, inst. is nop'd by decode)
748 : // - trigger is a store-data and there is a lsu_acc_exc or lsu_ma_exc.
749 : assign trigger_execute[3:0] = {mtdata1_t3[MTDATA1_EXE], mtdata1_t2[MTDATA1_EXE], mtdata1_t1[MTDATA1_EXE], mtdata1_t0[MTDATA1_EXE]};
750 : assign trigger_data[3:0] = {mtdata1_t3[MTDATA1_SEL], mtdata1_t2[MTDATA1_SEL], mtdata1_t1[MTDATA1_SEL], mtdata1_t0[MTDATA1_SEL]};
751 : assign trigger_store[3:0] = {mtdata1_t3[MTDATA1_ST], mtdata1_t2[MTDATA1_ST], mtdata1_t1[MTDATA1_ST], mtdata1_t0[MTDATA1_ST]};
752 :
753 : // MSTATUS[MIE] needs to be on to take triggers unless the action is trigger to debug mode.
754 : assign trigger_enabled[3:0] = {(mtdata1_t3[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t3[MTDATA1_M_ENABLED],
755 : (mtdata1_t2[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t2[MTDATA1_M_ENABLED],
756 : (mtdata1_t1[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t1[MTDATA1_M_ENABLED],
757 : (mtdata1_t0[MTDATA1_ACTION] | mstatus[MSTATUS_MIE]) & mtdata1_t0[MTDATA1_M_ENABLED]};
758 :
759 : // iside exceptions are always in i0
760 : assign i0_iside_trigger_has_pri_r[3:0] = ~( (trigger_execute[3:0] & trigger_data[3:0] & {4{inst_acc_r_raw}}) | // exe-data with inst_acc
761 : ({4{exu_i0_br_error_r | exu_i0_br_start_error_r}})); // branch error in i0
762 :
763 : // lsu excs have to line up with their respective triggers since the lsu op can be i0
764 : assign i0_lsu_trigger_has_pri_r[3:0] = ~(trigger_store[3:0] & trigger_data[3:0] & {4{lsu_i0_exc_r_raw}});
765 :
766 : // trigger hits have to be eval'd to cancel side effect lsu ops even though the pipe is already frozen
767 : assign i0_trigger_eval_r = dec_tlu_i0_valid_r;
768 :
769 : assign i0trigger_qual_r[3:0] = {4{i0_trigger_eval_r}} & dec_tlu_packet_r.i0trigger[3:0] & i0_iside_trigger_has_pri_r[3:0] & i0_lsu_trigger_has_pri_r[3:0] & trigger_enabled[3:0];
770 :
771 : // Qual trigger hits
772 : assign i0_trigger_r[3:0] = ~{4{dec_tlu_flush_lower_wb | dec_tlu_dbg_halted}} & i0trigger_qual_r[3:0];
773 :
774 : // chaining can mask raw trigger info
775 : assign i0_trigger_chain_masked_r[3:0] = {i0_trigger_r[3] & (~mtdata1_t2[MTDATA1_CHAIN] | i0_trigger_r[2]),
776 : i0_trigger_r[2] & (~mtdata1_t2[MTDATA1_CHAIN] | i0_trigger_r[3]),
777 : i0_trigger_r[1] & (~mtdata1_t0[MTDATA1_CHAIN] | i0_trigger_r[0]),
778 : i0_trigger_r[0] & (~mtdata1_t0[MTDATA1_CHAIN] | i0_trigger_r[1])};
779 :
780 : // This is the highest priority by this point.
781 : assign i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r[3:0];
782 :
783 : assign i0_trigger_hit_r = i0_trigger_hit_raw_r;
784 :
785 : // Actions include breakpoint, or dmode. Dmode is only possible if the DMODE bit is set.
786 : // Otherwise, take a breakpoint.
787 : assign trigger_action[3:0] = {mtdata1_t3[MTDATA1_ACTION] & mtdata1_t3[MTDATA1_DMODE],
788 : mtdata1_t2[MTDATA1_ACTION] & mtdata1_t2[MTDATA1_DMODE] & ~mtdata1_t2[MTDATA1_CHAIN],
789 : mtdata1_t1[MTDATA1_ACTION] & mtdata1_t1[MTDATA1_DMODE],
790 : mtdata1_t0[MTDATA1_ACTION] & mtdata1_t0[MTDATA1_DMODE] & ~mtdata1_t0[MTDATA1_CHAIN]};
791 :
792 : // this is needed to set the HIT bit in the triggers
793 : assign update_hit_bit_r[3:0] = ({4{|i0_trigger_r[3:0] & ~rfpc_i0_r}} & {i0_trigger_chain_masked_r[3], i0_trigger_r[2], i0_trigger_chain_masked_r[1], i0_trigger_r[0]});
794 :
795 : // action, 1 means dmode. Simultaneous triggers with at least 1 set for dmode force entire action to dmode.
796 : assign i0_trigger_action_r = |(i0_trigger_chain_masked_r[3:0] & trigger_action[3:0]);
797 :
798 : assign trigger_hit_dmode_r = (i0_trigger_hit_r & i0_trigger_action_r);
799 :
800 : assign mepc_trigger_hit_sel_pc_r = i0_trigger_hit_r & ~trigger_hit_dmode_r;
801 :
802 :
803 : //
804 : // Debug end
805 : //--------------------------------------------------------------------------------
806 :
807 : //----------------------------------------------------------------------
808 : //
809 : // Commit
810 : //
811 : //----------------------------------------------------------------------
812 :
813 :
814 :
815 : //--------------------------------------------------------------------------------
816 : // External halt (not debug halt)
817 : // - Fully interlocked handshake
818 : // i_cpu_halt_req ____|--------------|_______________
819 : // core_empty ---------------|___________
820 : // o_cpu_halt_ack _________________|----|__________
821 : // o_cpu_halt_status _______________|---------------------|_________
822 : // i_cpu_run_req ______|----------|____
823 : // o_cpu_run_ack ____________|------|________
824 : //
825 :
826 :
827 : // debug mode has priority, ignore PMU/FW halt/run while in debug mode
828 : assign i_cpu_halt_req_sync_qual = i_cpu_halt_req_sync & ~dec_tlu_debug_mode & ~ext_int_freeze_d1;
829 : assign i_cpu_run_req_sync_qual = i_cpu_run_req_sync & ~dec_tlu_debug_mode & pmu_fw_tlu_halted_f & ~ext_int_freeze_d1;
830 :
831 : rvdffie #(10) exthaltff (.*, .clk(free_l2clk), .din({i_cpu_halt_req_sync_qual, i_cpu_run_req_sync_qual, cpu_halt_status,
832 : cpu_halt_ack, cpu_run_ack, internal_pmu_fw_halt_mode,
833 : pmu_fw_halt_req_ns, pmu_fw_tlu_halted,
834 : int_timer0_int_hold, int_timer1_int_hold}),
835 : .dout({i_cpu_halt_req_d1, i_cpu_run_req_d1_raw, o_cpu_halt_status,
836 : o_cpu_halt_ack, o_cpu_run_ack, internal_pmu_fw_halt_mode_f,
837 : pmu_fw_halt_req_f, pmu_fw_tlu_halted_f,
838 : int_timer0_int_hold_f, int_timer1_int_hold_f}));
839 :
840 : // only happens if we aren't in dgb_halt
841 : assign ext_halt_pulse = i_cpu_halt_req_sync_qual & ~i_cpu_halt_req_d1;
842 :
843 : assign enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req;
844 :
845 : assign pmu_fw_halt_req_ns = (enter_pmu_fw_halt_req | (pmu_fw_halt_req_f & ~pmu_fw_tlu_halted)) & ~debug_halt_req_f;
846 :
847 : assign internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | (internal_pmu_fw_halt_mode_f & ~i_cpu_run_req_d1 & ~debug_halt_req_f);
848 :
849 : // debug halt has priority
850 : assign pmu_fw_tlu_halted = ((pmu_fw_halt_req_f & core_empty & halt_taken & ~enter_debug_halt_req) | (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1)) & ~debug_halt_req_f;
851 :
852 : assign cpu_halt_ack = (i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f) | (o_cpu_halt_ack & i_cpu_halt_req_sync);
853 : assign cpu_halt_status = (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1) | (o_cpu_halt_status & ~i_cpu_run_req_d1 & ~internal_dbg_halt_mode_f);
854 : assign cpu_run_ack = (~pmu_fw_tlu_halted_f & i_cpu_run_req_sync) | (o_cpu_halt_status & i_cpu_run_req_d1_raw) | (o_cpu_run_ack & i_cpu_run_req_sync);
855 : assign debug_mode_status = internal_dbg_halt_mode_f;
856 : assign o_debug_mode_status = debug_mode_status;
857 :
858 : `ifdef RV_ASSERT_ON
859 : assert_commit_while_halted: assert #0 (~(tlu_i0_commit_cmt & o_cpu_halt_status)) else $display("ERROR: Commiting while cpu_halt_status asserted!");
860 : assert_flush_while_fastint: assert #0 (~((take_ext_int_start_d1 | take_ext_int_start_d2) & dec_tlu_flush_lower_r)) else $display("ERROR: TLU Flushing inside fast interrupt procedure!");
861 : `endif
862 :
863 : // high priority interrupts can wakeup from external halt, so can unmasked timer interrupts
864 : assign i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (mhwakeup & mhwakeup_ready)) & o_cpu_halt_status & ~i_cpu_halt_req_d1);
865 :
866 : //--------------------------------------------------------------------------------
867 : //--------------------------------------------------------------------------------
868 :
869 : assign lsu_single_ecc_error_r = lsu_single_ecc_error_incr;
870 :
871 : assign lsu_error_pkt_addr_r[31:0] = lsu_error_pkt_r.addr[31:0];
872 :
873 :
874 : assign lsu_exc_valid_r_raw = lsu_error_pkt_r.exc_valid & ~dec_tlu_flush_lower_wb;
875 :
876 : assign lsu_i0_exc_r_raw = lsu_error_pkt_r.exc_valid;
877 :
878 : assign lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r;
879 :
880 : assign lsu_exc_valid_r = lsu_i0_exc_r;
881 :
882 : assign lsu_exc_ma_r = lsu_i0_exc_r & ~lsu_error_pkt_r.exc_type;
883 : assign lsu_exc_acc_r = lsu_i0_exc_r & lsu_error_pkt_r.exc_type;
884 : assign lsu_exc_st_r = lsu_i0_exc_r & lsu_error_pkt_r.inst_type;
885 :
886 : // Single bit ECC errors on loads are RFNPC corrected, with the corrected data written to the GPR.
887 : // LSU turns the load into a store and patches the data in the DCCM
888 : assign lsu_i0_rfnpc_r = dec_tlu_i0_valid_r & ~i0_trigger_hit_r &
889 : (~lsu_error_pkt_r.inst_type & lsu_error_pkt_r.single_ecc_error);
890 :
891 : // Final commit valids
892 : `ifdef RV_USER_MODE
893 : assign tlu_i0_commit_cmt = dec_tlu_i0_valid_r &
894 : ~rfpc_i0_r &
895 : ~lsu_i0_exc_r &
896 : ~inst_acc_r &
897 : ~dec_tlu_dbg_halted &
898 : ~request_debug_mode_r_d1 &
899 : ~i0_trigger_hit_r &
900 : ~csr_acc_r;
901 : `else
902 : assign tlu_i0_commit_cmt = dec_tlu_i0_valid_r &
903 : ~rfpc_i0_r &
904 : ~lsu_i0_exc_r &
905 : ~inst_acc_r &
906 : ~dec_tlu_dbg_halted &
907 : ~request_debug_mode_r_d1 &
908 : ~i0_trigger_hit_r;
909 : `endif
910 :
911 : // unified place to manage the killing of arch state writebacks
912 : `ifdef RV_USER_MODE
913 : assign tlu_i0_kill_writeb_r = rfpc_i0_r | lsu_i0_exc_r | inst_acc_r | (illegal_r & dec_tlu_dbg_halted) | i0_trigger_hit_r | csr_acc_r;
914 : `else
915 : assign tlu_i0_kill_writeb_r = rfpc_i0_r | lsu_i0_exc_r | inst_acc_r | (illegal_r & dec_tlu_dbg_halted) | i0_trigger_hit_r;
916 : `endif
917 : assign dec_tlu_i0_commit_cmt = tlu_i0_commit_cmt;
918 :
919 :
920 : // refetch PC, microarch flush
921 : // ic errors only in pipe0
922 : assign rfpc_i0_r = ((dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (exu_i0_br_error_r | exu_i0_br_start_error_r)) | // inst commit with rfpc
923 : ((ic_perr_r | iccm_sbecc_r) & ~ext_int_freeze_d1)) & // ic/iccm without inst commit
924 : ~i0_trigger_hit_r & // unless there's a trigger. Err signal to ic/iccm will assert anyway to clear the error.
925 : ~lsu_i0_rfnpc_r;
926 :
927 : // From the indication of a iccm single bit error until the first commit or flush, maintain a repair state. In the repair state, rfnpc i0 commits.
928 : assign iccm_repair_state_ns = iccm_sbecc_r | (iccm_repair_state_d1 & ~dec_tlu_flush_lower_r);
929 :
930 :
931 : localparam MCPC = 12'h7c2;
932 :
933 : // this is a flush of last resort, meaning only assert it if there is no other flush happening.
934 : assign iccm_repair_state_rfnpc = tlu_i0_commit_cmt & iccm_repair_state_d1 &
935 : ~(ebreak_r | ecall_r | mret_r | take_reset | illegal_r | (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCPC)));
936 :
937 : if(pt.BTB_ENABLE==1) begin
938 : // go ahead and repair the branch error on other flushes, doesn't have to be the rfpc flush
939 : assign dec_tlu_br0_error_r = exu_i0_br_error_r & dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1;
940 : assign dec_tlu_br0_start_error_r = exu_i0_br_start_error_r & dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1;
941 : assign dec_tlu_br0_v_r = exu_i0_br_valid_r & dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~exu_i0_br_mp_r | ~exu_pmu_i0_br_ataken);
942 :
943 :
944 : assign dec_tlu_br0_r_pkt.hist[1:0] = exu_i0_br_hist_r[1:0];
945 : assign dec_tlu_br0_r_pkt.br_error = dec_tlu_br0_error_r;
946 : assign dec_tlu_br0_r_pkt.br_start_error = dec_tlu_br0_start_error_r;
947 : assign dec_tlu_br0_r_pkt.valid = dec_tlu_br0_v_r;
948 : assign dec_tlu_br0_r_pkt.way = exu_i0_br_way_r;
949 : assign dec_tlu_br0_r_pkt.middle = exu_i0_br_middle_r;
950 : end // if (pt.BTB_ENABLE==1)
951 : else begin
952 : assign dec_tlu_br0_error_r = '0;
953 : assign dec_tlu_br0_start_error_r = '0;
954 : assign dec_tlu_br0_v_r = '0;
955 : assign dec_tlu_br0_r_pkt = '0;
956 : end // else: !if(pt.BTB_ENABLE==1)
957 :
958 :
959 : // only expect these in pipe 0
960 : assign ebreak_r = (dec_tlu_packet_r.pmu_i0_itype == EBREAK) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr[DCSR_EBREAKM] & ~rfpc_i0_r;
961 : assign ecall_r = (dec_tlu_packet_r.pmu_i0_itype == ECALL) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r;
962 : `ifdef RV_USER_MODE
963 : assign illegal_r = (((dec_tlu_packet_r.pmu_i0_itype == MRET) & priv_mode) | ~dec_tlu_packet_r.legal) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r;
964 : assign mret_r = ( (dec_tlu_packet_r.pmu_i0_itype == MRET) & ~priv_mode ) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r;
965 : `else
966 : assign illegal_r = ~dec_tlu_packet_r.legal & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r;
967 : assign mret_r = (dec_tlu_packet_r.pmu_i0_itype == MRET) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r;
968 : `endif
969 : // fence_i includes debug only fence_i's
970 : assign fence_i_r = (dec_tlu_packet_r.fence_i & dec_tlu_i0_valid_r & ~i0_trigger_hit_r) & ~rfpc_i0_r;
971 : assign ic_perr_r = ifu_ic_error_start_f & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f;
972 : assign iccm_sbecc_r = ifu_iccm_rd_ecc_single_err_f & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f;
973 : assign inst_acc_r_raw = dec_tlu_packet_r.icaf & dec_tlu_i0_valid_r;
974 : assign inst_acc_r = inst_acc_r_raw & ~rfpc_i0_r & ~i0_trigger_hit_r;
975 : assign inst_acc_second_r = dec_tlu_packet_r.icaf_second;
976 :
977 : assign ebreak_to_debug_mode_r = (dec_tlu_packet_r.pmu_i0_itype == EBREAK) & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & dcsr[DCSR_EBREAKM] & ~rfpc_i0_r;
978 :
979 : rvdff #(1) exctype_wb_ff (.*, .clk(e4e5_clk),
980 : .din (ebreak_to_debug_mode_r ),
981 : .dout(ebreak_to_debug_mode_r_d1));
982 :
983 : assign dec_tlu_fence_i_r = fence_i_r;
984 :
985 : `ifdef RV_USER_MODE
986 :
987 : // CSR access
988 : // Address bits 9:8 == 2'b00 indicate unprivileged / user-level CSR
989 : assign csr_wr_usr_r = ~|dec_csr_wraddr_r[9:8];
990 : assign csr_rd_usr_r = ~|dec_csr_rdaddr_r[9:8];
991 :
992 : // CSR access error
993 : // cycle and instret CSR unprivileged access is controller by bits in mcounteren CSR
994 0 : logic csr_wr_acc_r;
995 568 : logic csr_rd_acc_r;
996 :
997 : assign csr_wr_acc_r = csr_wr_usr_r & (
998 : ((dec_csr_wraddr_r[11:0] == CYCLEL) & mcounteren[MCOUNTEREN_CY]) |
999 : ((dec_csr_wraddr_r[11:0] == CYCLEH) & mcounteren[MCOUNTEREN_CY]) |
1000 : ((dec_csr_wraddr_r[11:0] == INSTRETL) & mcounteren[MCOUNTEREN_IR]) |
1001 : ((dec_csr_wraddr_r[11:0] == INSTRETH) & mcounteren[MCOUNTEREN_IR]) |
1002 : ((dec_csr_wraddr_r[11:0] == HPMC3) & mcounteren[MCOUNTEREN_HPM3]) |
1003 : ((dec_csr_wraddr_r[11:0] == HPMC3H) & mcounteren[MCOUNTEREN_HPM3]) |
1004 : ((dec_csr_wraddr_r[11:0] == HPMC4) & mcounteren[MCOUNTEREN_HPM4]) |
1005 : ((dec_csr_wraddr_r[11:0] == HPMC4H) & mcounteren[MCOUNTEREN_HPM4]) |
1006 : ((dec_csr_wraddr_r[11:0] == HPMC5) & mcounteren[MCOUNTEREN_HPM5]) |
1007 : ((dec_csr_wraddr_r[11:0] == HPMC5H) & mcounteren[MCOUNTEREN_HPM5]) |
1008 : ((dec_csr_wraddr_r[11:0] == HPMC6) & mcounteren[MCOUNTEREN_HPM6]) |
1009 : ((dec_csr_wraddr_r[11:0] == HPMC6H) & mcounteren[MCOUNTEREN_HPM6]));
1010 :
1011 : assign csr_rd_acc_r = csr_rd_usr_r & (
1012 : ((dec_csr_rdaddr_r[11:0] == CYCLEL) & mcounteren[MCOUNTEREN_CY]) |
1013 : ((dec_csr_rdaddr_r[11:0] == CYCLEH) & mcounteren[MCOUNTEREN_CY]) |
1014 : ((dec_csr_rdaddr_r[11:0] == INSTRETL) & mcounteren[MCOUNTEREN_IR]) |
1015 : ((dec_csr_rdaddr_r[11:0] == INSTRETH) & mcounteren[MCOUNTEREN_IR]) |
1016 : ((dec_csr_rdaddr_r[11:0] == HPMC3) & mcounteren[MCOUNTEREN_HPM3]) |
1017 : ((dec_csr_rdaddr_r[11:0] == HPMC3H) & mcounteren[MCOUNTEREN_HPM3]) |
1018 : ((dec_csr_rdaddr_r[11:0] == HPMC4) & mcounteren[MCOUNTEREN_HPM4]) |
1019 : ((dec_csr_rdaddr_r[11:0] == HPMC4H) & mcounteren[MCOUNTEREN_HPM4]) |
1020 : ((dec_csr_rdaddr_r[11:0] == HPMC5) & mcounteren[MCOUNTEREN_HPM5]) |
1021 : ((dec_csr_rdaddr_r[11:0] == HPMC5H) & mcounteren[MCOUNTEREN_HPM5]) |
1022 : ((dec_csr_rdaddr_r[11:0] == HPMC6) & mcounteren[MCOUNTEREN_HPM6]) |
1023 : ((dec_csr_rdaddr_r[11:0] == HPMC6H) & mcounteren[MCOUNTEREN_HPM6]));
1024 :
1025 : assign csr_acc_r = priv_mode & dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r & (
1026 : (dec_tlu_packet_r.pmu_i0_itype == CSRREAD) & ~csr_rd_acc_r |
1027 : (dec_tlu_packet_r.pmu_i0_itype == CSRWRITE) & ~csr_wr_acc_r |
1028 : (dec_tlu_packet_r.pmu_i0_itype == CSRRW) & ~csr_rd_acc_r & ~csr_wr_acc_r);
1029 :
1030 : `endif
1031 :
1032 : //
1033 : // Exceptions
1034 : //
1035 : // - MEPC <- PC
1036 : // - PC <- MTVEC, assert flush_lower
1037 : // - MCAUSE <- cause
1038 : // - MSCAUSE <- secondary cause
1039 : // - MTVAL <-
1040 : // - MPIE <- MIE
1041 : // - MIE <- 0
1042 : //
1043 : `ifdef RV_USER_MODE
1044 : assign i0_exception_valid_r = (ebreak_r | ecall_r | illegal_r | inst_acc_r | csr_acc_r) & ~rfpc_i0_r & ~dec_tlu_dbg_halted;
1045 : `else
1046 : assign i0_exception_valid_r = (ebreak_r | ecall_r | illegal_r | inst_acc_r) & ~rfpc_i0_r & ~dec_tlu_dbg_halted;
1047 : `endif
1048 :
1049 : // Cause:
1050 : //
1051 : // 0x2 : illegal
1052 : // 0x3 : breakpoint
1053 : // 0x8 : Environment call U-mode (if U-mode is enabled)
1054 : // 0xb : Environment call M-mode
1055 :
1056 :
1057 : assign exc_cause_r[4:0] = ( ({5{take_ext_int}} & 5'h0b) |
1058 : ({5{take_timer_int}} & 5'h07) |
1059 : ({5{take_soft_int}} & 5'h03) |
1060 : ({5{take_int_timer0_int}} & 5'h1d) |
1061 : ({5{take_int_timer1_int}} & 5'h1c) |
1062 : ({5{take_ce_int}} & 5'h1e) |
1063 : `ifdef RV_USER_MODE
1064 : ({5{illegal_r| csr_acc_r}} & 5'h02) |
1065 : ({5{ecall_r & priv_mode}} & 5'h08) |
1066 : ({5{ecall_r & ~priv_mode}} & 5'h0b) |
1067 : `else
1068 : ({5{illegal_r}} & 5'h02) |
1069 : ({5{ecall_r}} & 5'h0b) |
1070 : `endif
1071 : ({5{inst_acc_r}} & 5'h01) |
1072 : ({5{ebreak_r | i0_trigger_hit_r}} & 5'h03) |
1073 : ({5{lsu_exc_ma_r & ~lsu_exc_st_r}} & 5'h04) |
1074 : ({5{lsu_exc_acc_r & ~lsu_exc_st_r}} & 5'h05) |
1075 : ({5{lsu_exc_ma_r & lsu_exc_st_r}} & 5'h06) |
1076 : ({5{lsu_exc_acc_r & lsu_exc_st_r}} & 5'h07)
1077 : ) & ~{5{take_nmi}};
1078 :
1079 : //
1080 : // Interrupts
1081 : //
1082 : // exceptions that are committed have already happened and will cause an int at E4 to wait a cycle
1083 : // or more if MSTATUS[MIE] is cleared.
1084 : //
1085 : // -in priority order, highest to lowest
1086 : // -single cycle window where a csr write to MIE/MSTATUS is at E4 when the other conditions for externals are met.
1087 : // Hold off externals for a cycle to make sure we are consistent with what was just written
1088 : assign mhwakeup_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MEIP] & mie_ns[MIE_MEIE];
1089 : assign ext_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MEIP] & mie_ns[MIE_MEIE] & ~ignore_ext_int_due_to_lsu_stall;
1090 : assign ce_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MCEIP] & mie_ns[MIE_MCEIE];
1091 : assign soft_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MSIP] & mie_ns[MIE_MSIE];
1092 : assign timer_int_ready = ~dec_csr_stall_int_ff & mstatus_mie_ns & mip[MIP_MTIP] & mie_ns[MIE_MTIE];
1093 :
1094 : // MIP for internal timers pulses for 1 clock, resets the timer counter. Mip won't hold past the various stall conditions.
1095 : assign int_timer0_int_possible = mstatus_mie_ns & mie_ns[MIE_MITIE0];
1096 : assign int_timer0_int_ready = mip[MIP_MITIP0] & int_timer0_int_possible;
1097 : assign int_timer1_int_possible = mstatus_mie_ns & mie_ns[MIE_MITIE1];
1098 : assign int_timer1_int_ready = mip[MIP_MITIP1] & int_timer1_int_possible;
1099 :
1100 : // Internal timers pulse and reset. If core is PMU/FW halted, the pulse will cause an exit from halt, but won't stick around
1101 : // Make it sticky, also for 1 cycle stall conditions.
1102 : assign int_timer_stalled = dec_csr_stall_int_ff | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r;
1103 :
1104 : assign int_timer0_int_hold = (int_timer0_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer0_int_possible & int_timer0_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f);
1105 : assign int_timer1_int_hold = (int_timer1_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer1_int_possible & int_timer1_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f);
1106 :
1107 :
1108 : assign internal_dbg_halt_timers = internal_dbg_halt_mode_f & ~dcsr_single_step_running;
1109 :
1110 :
1111 : assign block_interrupts = ( (internal_dbg_halt_mode & (~dcsr_single_step_running | dec_tlu_i0_valid_r)) | // No ints in db-halt unless we are single stepping
1112 : internal_pmu_fw_halt_mode | i_cpu_halt_req_d1 |// No ints in PMU/FW halt. First we exit halt
1113 : take_nmi | // NMI is top priority
1114 : ebreak_to_debug_mode_r | // Heading to debug mode, hold off ints
1115 : synchronous_flush_r | // exception flush this cycle
1116 : exc_or_int_valid_r_d1 | // ext/int past cycle (need time for MIE to update)
1117 : mret_r | // mret in progress, for cases were ISR enables ints before mret
1118 : ext_int_freeze_d1 // Fast interrupt in progress (optional)
1119 : );
1120 :
1121 :
1122 : if (pt.FAST_INTERRUPT_REDIRECT) begin
1123 :
1124 :
1125 : assign take_ext_int_start = ext_int_ready & ~block_interrupts;
1126 :
1127 : assign ext_int_freeze = take_ext_int_start | take_ext_int_start_d1 | take_ext_int_start_d2 | take_ext_int_start_d3;
1128 : assign take_ext_int = take_ext_int_start_d3 & ~|lsu_fir_error[1:0];
1129 : assign fast_int_meicpct = csr_meicpct & dec_csr_any_unq_d; // MEICPCT becomes illegal if fast ints are enabled
1130 :
1131 : assign ignore_ext_int_due_to_lsu_stall = lsu_fastint_stall_any;
1132 : end
1133 : else begin
1134 : assign take_ext_int_start = 1'b0;
1135 : assign ext_int_freeze = 1'b0;
1136 : assign ext_int_freeze_d1 = 1'b0;
1137 : assign take_ext_int_start_d1 = 1'b0;
1138 : assign take_ext_int_start_d2 = 1'b0;
1139 : assign take_ext_int_start_d3 = 1'b0;
1140 : assign fast_int_meicpct = 1'b0;
1141 : assign ignore_ext_int_due_to_lsu_stall = 1'b0;
1142 :
1143 : assign take_ext_int = ext_int_ready & ~block_interrupts;
1144 : end
1145 :
1146 : assign take_ce_int = ce_int_ready & ~ext_int_ready & ~block_interrupts;
1147 : assign take_soft_int = soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts;
1148 : assign take_timer_int = timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts;
1149 : assign take_int_timer0_int = (int_timer0_int_ready | int_timer0_int_hold_f) & int_timer0_int_possible & ~dec_csr_stall_int_ff &
1150 : ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts;
1151 : assign take_int_timer1_int = (int_timer1_int_ready | int_timer1_int_hold_f) & int_timer1_int_possible & ~dec_csr_stall_int_ff &
1152 : ~(int_timer0_int_ready | int_timer0_int_hold_f) & ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts;
1153 :
1154 : assign take_reset = reset_delayed & mpc_reset_run_req;
1155 : assign take_nmi = nmi_int_detected & ~internal_pmu_fw_halt_mode & (~internal_dbg_halt_mode | (dcsr_single_step_running_f & dcsr[DCSR_STEPIE] & ~dec_tlu_i0_valid_r & ~dcsr_single_step_done_f)) &
1156 : ~synchronous_flush_r & ~mret_r & ~take_reset & ~ebreak_to_debug_mode_r & (~ext_int_freeze_d1 | (take_ext_int_start_d3 & |lsu_fir_error[1:0]));
1157 :
1158 : assign interrupt_valid_r = take_ext_int | take_timer_int | take_soft_int | take_nmi | take_ce_int | take_int_timer0_int | take_int_timer1_int;
1159 :
1160 :
1161 : // Compute interrupt path:
1162 : // If vectored async is set in mtvec, flush path for interrupts is MTVEC + (4 * CAUSE);
1163 : assign vectored_path[31:1] = {mtvec[30:1], 1'b0} + {25'b0, exc_cause_r[4:0], 1'b0};
1164 : assign interrupt_path[31:1] = take_nmi ? nmi_vec[31:1] : ((mtvec[0] == 1'b1) ? vectored_path[31:1] : {mtvec[30:1], 1'b0});
1165 :
1166 : assign sel_npc_r = lsu_i0_rfnpc_r | fence_i_r | iccm_repair_state_rfnpc | (i_cpu_run_req_d1 & ~interrupt_valid_r) | (rfpc_i0_r & ~dec_tlu_i0_valid_r);
1167 : assign sel_npc_resume = (i_cpu_run_req_d1 & pmu_fw_tlu_halted_f) | pause_expired_r;
1168 :
1169 : assign sel_fir_addr = take_ext_int_start_d3 & ~|lsu_fir_error[1:0];
1170 :
1171 : assign synchronous_flush_r = i0_exception_valid_r | // exception
1172 : rfpc_i0_r | // rfpc
1173 : lsu_exc_valid_r | // lsu exception in either pipe 0 or pipe 1
1174 : fence_i_r | // fence, a rfnpc
1175 : lsu_i0_rfnpc_r | // lsu dccm sb ecc
1176 : iccm_repair_state_rfnpc | // Iccm sb ecc
1177 : debug_resume_req_f | // resume from debug halt, fetch the dpc
1178 : sel_npc_resume | // resume from pmu/fw halt, or from pause and fetch the NPC
1179 : dec_tlu_wr_pause_r_d1 | // flush at start of pause
1180 : i0_trigger_hit_r; // trigger hit, ebreak or goto debug mode
1181 :
1182 : assign tlu_flush_lower_r = interrupt_valid_r | mret_r | synchronous_flush_r | take_halt | take_reset | take_ext_int_start;
1183 :
1184 : assign tlu_flush_path_r[31:1] = take_reset ? rst_vec[31:1] :
1185 :
1186 : ( ({31{sel_fir_addr}} & lsu_fir_addr[31:1]) |
1187 : ({31{~take_nmi & sel_npc_r}} & npc_r[31:1]) |
1188 : ({31{~take_nmi & rfpc_i0_r & dec_tlu_i0_valid_r & ~sel_npc_r}} & dec_tlu_i0_pc_r[31:1]) |
1189 : ({31{interrupt_valid_r & ~sel_fir_addr}} & interrupt_path[31:1]) |
1190 : ({31{(i0_exception_valid_r | lsu_exc_valid_r |
1191 : (i0_trigger_hit_r & ~trigger_hit_dmode_r)) & ~interrupt_valid_r & ~sel_fir_addr}} & {mtvec[30:1],1'b0}) |
1192 : ({31{~take_nmi & mret_r}} & mepc[31:1]) |
1193 : ({31{~take_nmi & debug_resume_req_f}} & dpc[31:1]) |
1194 : ({31{~take_nmi & sel_npc_resume}} & npc_r_d1[31:1]) );
1195 :
1196 : rvdffpcie #(31) flush_lower_ff (.*, .en(tlu_flush_lower_r),
1197 : .din({tlu_flush_path_r[31:1]}),
1198 : .dout({tlu_flush_path_r_d1[31:1]}));
1199 :
1200 : assign dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1;
1201 : assign dec_tlu_flush_lower_r = tlu_flush_lower_r;
1202 : assign dec_tlu_flush_path_r[31:1] = tlu_flush_path_r[31:1];
1203 :
1204 :
1205 : // this is used to capture mepc, etc.
1206 : assign exc_or_int_valid_r = lsu_exc_valid_r | i0_exception_valid_r | interrupt_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r);
1207 :
1208 :
1209 : rvdffie #(12) excinfo_wb_ff (.*,
1210 : .din({interrupt_valid_r, i0_exception_valid_r, exc_or_int_valid_r,
1211 : exc_cause_r[4:0], tlu_i0_commit_cmt & ~illegal_r, i0_trigger_hit_r,
1212 : take_nmi, pause_expired_r }),
1213 : .dout({interrupt_valid_r_d1, i0_exception_valid_r_d1, exc_or_int_valid_r_d1,
1214 : exc_cause_wb[4:0], i0_valid_wb, trigger_hit_r_d1,
1215 : take_nmi_r_d1, pause_expired_wb}));
1216 : `ifdef RV_USER_MODE
1217 :
1218 : //
1219 : // Privilege mode
1220 : //
1221 : assign priv_mode_ns = (mret_r & mstatus[MSTATUS_MPP]) |
1222 : (exc_or_int_valid_r & 1'b0 ) |
1223 : ((~mret_r & ~exc_or_int_valid_r) & priv_mode);
1224 :
1225 : rvdff #(1) priv_ff (
1226 : .clk (free_l2clk),
1227 : .rst_l (rst_l),
1228 : .din (priv_mode_ns),
1229 : .dout (priv_mode)
1230 : );
1231 :
1232 : `endif
1233 :
1234 : //----------------------------------------------------------------------
1235 : //
1236 : // CSRs
1237 : //
1238 : //----------------------------------------------------------------------
1239 :
1240 :
1241 : // ----------------------------------------------------------------------
1242 : // MISA (RO)
1243 : // [31:30] XLEN - implementation width, 2'b01 - 32 bits
1244 : // [20] U - user mode support (if enabled in config)
1245 : // [12] M - integer mul/div
1246 : // [8] I - RV32I
1247 : // [2] C - Compressed extension
1248 : localparam MISA = 12'h301;
1249 :
1250 : // MVENDORID, MARCHID, MIMPID, MHARTID
1251 : localparam MVENDORID = 12'hf11;
1252 : localparam MARCHID = 12'hf12;
1253 : localparam MIMPID = 12'hf13;
1254 : localparam MHARTID = 12'hf14;
1255 :
1256 :
1257 : // ----------------------------------------------------------------------
1258 : // MSTATUS (RW)
1259 : // [17] MPRV : Modify PRiVilege (if enabled in config)
1260 : // [12:11] MPP : Prior priv level, either 2'b11 (machine) or 2'b00 (user)
1261 : // [7] MPIE : Int enable previous [1]
1262 : // [3] MIE : Int enable [0]
1263 : localparam MSTATUS = 12'h300;
1264 :
1265 :
1266 : //When executing a MRET instruction, supposing MPP holds the value 3, MIE
1267 : //is set to MPIE; the privilege mode is changed to 3; MPIE is set to 1; and MPP is set to 3
1268 : `ifdef RV_USER_MODE
1269 : assign dec_csr_wen_r_mod = dec_csr_wen_r & ~i0_trigger_hit_r & ~rfpc_i0_r & ~csr_acc_r;
1270 : `else
1271 : assign dec_csr_wen_r_mod = dec_csr_wen_r & ~i0_trigger_hit_r & ~rfpc_i0_r;
1272 : `endif
1273 :
1274 : assign wr_mstatus_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSTATUS);
1275 :
1276 : // set this even if we don't go to fwhalt due to debug halt. We committed the inst, so ...
1277 : assign set_mie_pmu_fw_halt = ~mpmc_b_ns[1] & fw_halt_req;
1278 :
1279 : `ifdef RV_USER_MODE
1280 : // mstatus[2] / mstatus_ns[2] actually stores inverse of the MPP field !
1281 : assign mstatus_ns[3:0] = ( ({4{~wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MPRV], priv_mode, mstatus[MSTATUS_MIE], 1'b0}) |
1282 : ({4{ wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MPRV], priv_mode, dec_csr_wrdata_r[3], 1'b0}) |
1283 : ({4{mret_r & ~exc_or_int_valid_r}} & {mstatus[MSTATUS_MPRV] & ~mstatus[MSTATUS_MPP], 1'b1, 1'b1, mstatus[MSTATUS_MPIE]}) |
1284 : ({4{set_mie_pmu_fw_halt}} & {mstatus[3:2], mstatus[MSTATUS_MPIE], 1'b1}) |
1285 : ({4{wr_mstatus_r & ~exc_or_int_valid_r}} & {dec_csr_wrdata_r[17], ~dec_csr_wrdata_r[12], dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]}) |
1286 : ({4{~wr_mstatus_r & ~exc_or_int_valid_r & ~mret_r & ~set_mie_pmu_fw_halt}} & mstatus[3:0]) );
1287 :
1288 : // gate MIE if we are single stepping and DCSR[STEPIE] is off
1289 : // in user mode machine interrupts are always enabled as per RISC-V privilege spec (chapter 3.1.6.1).
1290 : assign mstatus_mie_ns = (priv_mode | mstatus[MSTATUS_MIE]) & (~dcsr_single_step_running_f | dcsr[DCSR_STEPIE]);
1291 :
1292 : // set effective privilege mode according to MPRV and MPP
1293 : assign priv_mode_eff = ( mstatus[MSTATUS_MPRV] & mstatus[MSTATUS_MPP]) | // MPRV=1, use MPP
1294 : (~mstatus[MSTATUS_MPRV] & priv_mode); // MPRV=0, use current operating mode
1295 :
1296 : `else
1297 :
1298 : assign mstatus_ns[1:0] = ( ({2{~wr_mstatus_r & exc_or_int_valid_r}} & {mstatus[MSTATUS_MIE], 1'b0}) |
1299 : ({2{ wr_mstatus_r & exc_or_int_valid_r}} & {dec_csr_wrdata_r[3], 1'b0}) |
1300 : ({2{mret_r & ~exc_or_int_valid_r}} & {1'b1, mstatus[MSTATUS_MPIE]}) |
1301 : ({2{set_mie_pmu_fw_halt}} & {mstatus[MSTATUS_MPIE], 1'b1}) |
1302 : ({2{wr_mstatus_r & ~exc_or_int_valid_r}} & {dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]}) |
1303 : ({2{~wr_mstatus_r & ~exc_or_int_valid_r & ~mret_r & ~set_mie_pmu_fw_halt}} & mstatus[1:0]) );
1304 :
1305 : assign mstatus_mie_ns = mstatus[MSTATUS_MIE] & (~dcsr_single_step_running_f | dcsr[DCSR_STEPIE]);
1306 :
1307 : `endif
1308 :
1309 : // ----------------------------------------------------------------------
1310 : // MTVEC (RW)
1311 : // [31:2] BASE : Trap vector base address
1312 : // [1] - Reserved, not implemented, reads zero
1313 : // [0] MODE : 0 = Direct, 1 = Asyncs are vectored to BASE + (4 * CAUSE)
1314 : localparam MTVEC = 12'h305;
1315 :
1316 : assign wr_mtvec_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVEC);
1317 : assign mtvec_ns[30:0] = {dec_csr_wrdata_r[31:2], dec_csr_wrdata_r[0]} ;
1318 : rvdffe #(31) mtvec_ff (.*, .en(wr_mtvec_r), .din(mtvec_ns[30:0]), .dout(mtvec[30:0]));
1319 :
1320 : // ----------------------------------------------------------------------
1321 : // MIP (RW)
1322 : //
1323 : // [30] MCEIP : (RO) M-Mode Correctable Error interrupt pending
1324 : // [29] MITIP0 : (RO) M-Mode Internal Timer0 interrupt pending
1325 : // [28] MITIP1 : (RO) M-Mode Internal Timer1 interrupt pending
1326 : // [11] MEIP : (RO) M-Mode external interrupt pending
1327 : // [7] MTIP : (RO) M-Mode timer interrupt pending
1328 : // [3] MSIP : (RO) M-Mode software interrupt pending
1329 : localparam MIP = 12'h344;
1330 :
1331 : assign ce_int = (mdccme_ce_req | miccme_ce_req | mice_ce_req);
1332 :
1333 : assign mip_ns[5:0] = {ce_int, dec_timer_t0_pulse, dec_timer_t1_pulse, mexintpend, timer_int_sync, soft_int_sync};
1334 :
1335 : // ----------------------------------------------------------------------
1336 : // MIE (RW)
1337 : // [30] MCEIE : (RO) M-Mode Correctable Error interrupt enable
1338 : // [29] MITIE0 : (RO) M-Mode Internal Timer0 interrupt enable
1339 : // [28] MITIE1 : (RO) M-Mode Internal Timer1 interrupt enable
1340 : // [11] MEIE : (RW) M-Mode external interrupt enable
1341 : // [7] MTIE : (RW) M-Mode timer interrupt enable
1342 : // [3] MSIE : (RW) M-Mode software interrupt enable
1343 : localparam MIE = 12'h304;
1344 :
1345 : assign wr_mie_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MIE);
1346 : assign mie_ns[5:0] = wr_mie_r ? {dec_csr_wrdata_r[30:28], dec_csr_wrdata_r[11], dec_csr_wrdata_r[7], dec_csr_wrdata_r[3]} : mie[5:0];
1347 : rvdff #(6) mie_ff (.*, .clk(csr_wr_clk), .din(mie_ns[5:0]), .dout(mie[5:0]));
1348 :
1349 :
1350 : // ----------------------------------------------------------------------
1351 : // MCYCLEL (RW)
1352 : // [31:0] : Lower Cycle count
1353 :
1354 : localparam MCYCLEL = 12'hb00;
1355 : localparam logic [11:0] CYCLEL = 12'hc00;
1356 :
1357 : assign kill_ebreak_count_r = ebreak_to_debug_mode_r & dcsr[DCSR_STOPC];
1358 :
1359 : assign wr_mcyclel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEL);
1360 :
1361 : assign mcyclel_cout_in = ~(kill_ebreak_count_r | (dec_tlu_dbg_halted & dcsr[DCSR_STOPC]) | dec_tlu_pmu_fw_halted | mcountinhibit[0]);
1362 :
1363 : // split for power
1364 : assign {mcyclela_cout, mcyclel_inc[7:0]} = mcyclel[7:0] + {7'b0, 1'b1};
1365 : assign {mcyclel_cout, mcyclel_inc[31:8]} = mcyclel[31:8] + {23'b0, mcyclela_cout};
1366 :
1367 : assign mcyclel_ns[31:0] = wr_mcyclel_r ? dec_csr_wrdata_r[31:0] : mcyclel_inc[31:0];
1368 :
1369 : rvdffe #(24) mcyclel_bff (.*, .clk(free_l2clk), .en(wr_mcyclel_r | (mcyclela_cout & mcyclel_cout_in)), .din(mcyclel_ns[31:8]), .dout(mcyclel[31:8]));
1370 : rvdffe #(8) mcyclel_aff (.*, .clk(free_l2clk), .en(wr_mcyclel_r | mcyclel_cout_in), .din(mcyclel_ns[7:0]), .dout(mcyclel[7:0]));
1371 :
1372 : // ----------------------------------------------------------------------
1373 : // MCYCLEH (RW)
1374 : // [63:32] : Higher Cycle count
1375 : // Chained with mcyclel. Note: mcyclel overflow due to a mcycleh write gets ignored.
1376 :
1377 : localparam MCYCLEH = 12'hb80;
1378 : localparam logic [11:0] CYCLEH = 12'hc80;
1379 :
1380 : assign wr_mcycleh_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCYCLEH);
1381 :
1382 : assign mcycleh_inc[31:0] = mcycleh[31:0] + {31'b0, mcyclel_cout_f};
1383 : assign mcycleh_ns[31:0] = wr_mcycleh_r ? dec_csr_wrdata_r[31:0] : mcycleh_inc[31:0];
1384 :
1385 : rvdffe #(32) mcycleh_ff (.*, .clk(free_l2clk), .en(wr_mcycleh_r | mcyclel_cout_f), .din(mcycleh_ns[31:0]), .dout(mcycleh[31:0]));
1386 :
1387 : // ----------------------------------------------------------------------
1388 : // MINSTRETL (RW)
1389 : // [31:0] : Lower Instruction retired count
1390 : // From the spec "Some CSRs, such as the instructions retired counter, instret, may be modified as side effects
1391 : // of instruction execution. In these cases, if a CSR access instruction reads a CSR, it reads the
1392 : // value prior to the execution of the instruction. If a CSR access instruction writes a CSR, the
1393 : // update occurs after the execution of the instruction. In particular, a value written to instret by
1394 : // one instruction will be the value read by the following instruction (i.e., the increment of instret
1395 : // caused by the first instruction retiring happens before the write of the new value)."
1396 : localparam MINSTRETL = 12'hb02;
1397 : localparam logic [11:0] INSTRETL = 12'hc02;
1398 :
1399 : assign i0_valid_no_ebreak_ecall_r = dec_tlu_i0_valid_r & ~(ebreak_r | ecall_r | ebreak_to_debug_mode_r | illegal_r | mcountinhibit[2]);
1400 :
1401 : assign wr_minstretl_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MINSTRETL);
1402 :
1403 : assign {minstretl_couta, minstretl_inc[7:0]} = minstretl[7:0] + {7'b0,1'b1};
1404 : assign {minstretl_cout, minstretl_inc[31:8]} = minstretl[31:8] + {23'b0, minstretl_couta};
1405 :
1406 : assign minstret_enable = (i0_valid_no_ebreak_ecall_r & tlu_i0_commit_cmt) | wr_minstretl_r;
1407 :
1408 : assign minstretl_cout_ns = minstretl_cout & ~wr_minstreth_r & i0_valid_no_ebreak_ecall_r & ~dec_tlu_dbg_halted;
1409 :
1410 : assign minstretl_ns[31:0] = wr_minstretl_r ? dec_csr_wrdata_r[31:0] : minstretl_inc[31:0];
1411 : rvdffe #(24) minstretl_bff (.*, .en(wr_minstretl_r | (minstretl_couta & minstret_enable)),
1412 : .din(minstretl_ns[31:8]), .dout(minstretl[31:8]));
1413 : rvdffe #(8) minstretl_aff (.*, .en(minstret_enable),
1414 : .din(minstretl_ns[7:0]), .dout(minstretl[7:0]));
1415 :
1416 :
1417 : assign minstretl_read[31:0] = minstretl[31:0];
1418 : // ----------------------------------------------------------------------
1419 : // MINSTRETH (RW)
1420 : // [63:32] : Higher Instret count
1421 : // Chained with minstretl. Note: minstretl overflow due to a minstreth write gets ignored.
1422 :
1423 : localparam MINSTRETH = 12'hb82;
1424 : localparam logic [11:0] INSTRETH = 12'hc82;
1425 :
1426 : assign wr_minstreth_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MINSTRETH);
1427 :
1428 : assign minstreth_inc[31:0] = minstreth[31:0] + {31'b0, minstretl_cout_f};
1429 : assign minstreth_ns[31:0] = wr_minstreth_r ? dec_csr_wrdata_r[31:0] : minstreth_inc[31:0];
1430 : rvdffe #(32) minstreth_ff (.*, .en((minstret_enable_f & minstretl_cout_f) | wr_minstreth_r), .din(minstreth_ns[31:0]), .dout(minstreth[31:0]));
1431 :
1432 : assign minstreth_read[31:0] = minstreth_inc[31:0];
1433 :
1434 : // ----------------------------------------------------------------------
1435 : // MSCRATCH (RW)
1436 : // [31:0] : Scratch register
1437 : localparam MSCRATCH = 12'h340;
1438 :
1439 : assign wr_mscratch_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCRATCH);
1440 :
1441 : rvdffe #(32) mscratch_ff (.*, .en(wr_mscratch_r), .din(dec_csr_wrdata_r[31:0]), .dout(mscratch[31:0]));
1442 :
1443 : // ----------------------------------------------------------------------
1444 : // MEPC (RW)
1445 : // [31:1] : Exception PC
1446 : localparam MEPC = 12'h341;
1447 :
1448 : // NPC
1449 :
1450 : assign sel_exu_npc_r = ~dec_tlu_dbg_halted & ~tlu_flush_lower_r_d1 & dec_tlu_i0_valid_r;
1451 : assign sel_flush_npc_r = ~dec_tlu_dbg_halted & tlu_flush_lower_r_d1 & ~dec_tlu_flush_noredir_r_d1;
1452 : assign sel_hold_npc_r = ~sel_exu_npc_r & ~sel_flush_npc_r;
1453 :
1454 : assign npc_r[31:1] = ( ({31{sel_exu_npc_r}} & exu_npc_r[31:1]) |
1455 : ({31{~mpc_reset_run_req & reset_delayed}} & rst_vec[31:1]) | // init to reset vector for mpc halt on reset case
1456 : ({31{(sel_flush_npc_r)}} & tlu_flush_path_r_d1[31:1]) |
1457 : ({31{(sel_hold_npc_r)}} & npc_r_d1[31:1]) );
1458 :
1459 : rvdffpcie #(31) npwbc_ff (.*, .en(sel_exu_npc_r | sel_flush_npc_r | reset_delayed), .din(npc_r[31:1]), .dout(npc_r_d1[31:1]));
1460 :
1461 : // PC has to be captured for exceptions and interrupts. For MRET, we could execute it and then take an
1462 : // interrupt before the next instruction.
1463 : assign pc0_valid_r = ~dec_tlu_dbg_halted & dec_tlu_i0_valid_r;
1464 :
1465 : assign pc_r[31:1] = ( ({31{ pc0_valid_r}} & dec_tlu_i0_pc_r[31:1]) |
1466 : ({31{~pc0_valid_r}} & pc_r_d1[31:1]));
1467 :
1468 : rvdffpcie #(31) pwbc_ff (.*, .en(pc0_valid_r), .din(pc_r[31:1]), .dout(pc_r_d1[31:1]));
1469 :
1470 : assign wr_mepc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEPC);
1471 :
1472 : assign mepc_ns[31:1] = ( ({31{i0_exception_valid_r | lsu_exc_valid_r | mepc_trigger_hit_sel_pc_r}} & pc_r[31:1]) |
1473 : ({31{interrupt_valid_r}} & npc_r[31:1]) |
1474 : ({31{wr_mepc_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[31:1]) |
1475 : ({31{~wr_mepc_r & ~exc_or_int_valid_r}} & mepc[31:1]) );
1476 :
1477 :
1478 : rvdffe #(31) mepc_ff (.*, .en(i0_exception_valid_r | lsu_exc_valid_r | mepc_trigger_hit_sel_pc_r | interrupt_valid_r | wr_mepc_r), .din(mepc_ns[31:1]), .dout(mepc[31:1]));
1479 :
1480 : // ----------------------------------------------------------------------
1481 : // MCAUSE (RW)
1482 : // [31:0] : Exception Cause
1483 : localparam MCAUSE = 12'h342;
1484 :
1485 : assign wr_mcause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCAUSE);
1486 : assign mcause_sel_nmi_store = exc_or_int_valid_r & take_nmi & nmi_lsu_store_type;
1487 : assign mcause_sel_nmi_load = exc_or_int_valid_r & take_nmi & nmi_lsu_load_type;
1488 : assign mcause_sel_nmi_ext = exc_or_int_valid_r & take_nmi & take_ext_int_start_d3 & |lsu_fir_error[1:0] & ~nmi_int_detected_f;
1489 : // FIR value decoder
1490 : // 0 –no error
1491 : // 1 –uncorrectable ecc => f000_1000
1492 : // 2 –dccm region access error => f000_1001
1493 : // 3 –non dccm region access error => f000_1002
1494 : assign mcause_fir_error_type[1:0] = {&lsu_fir_error[1:0], lsu_fir_error[1] & ~lsu_fir_error[0]};
1495 :
1496 : assign mcause_ns[31:0] = ( ({32{mcause_sel_nmi_store}} & {32'hf000_0000}) |
1497 : ({32{mcause_sel_nmi_load}} & {32'hf000_0001}) |
1498 : ({32{mcause_sel_nmi_ext}} & {28'hf000_100, 2'b0, mcause_fir_error_type[1:0]}) |
1499 : ({32{exc_or_int_valid_r & ~take_nmi}} & {interrupt_valid_r, 26'b0, exc_cause_r[4:0]}) |
1500 : ({32{wr_mcause_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[31:0]) |
1501 : ({32{~wr_mcause_r & ~exc_or_int_valid_r}} & mcause[31:0]) );
1502 :
1503 : rvdffe #(32) mcause_ff (.*, .en(exc_or_int_valid_r | wr_mcause_r), .din(mcause_ns[31:0]), .dout(mcause[31:0]));
1504 : // ----------------------------------------------------------------------
1505 : // MSCAUSE (RW)
1506 : // [2:0] : Secondary exception Cause
1507 : localparam MSCAUSE = 12'h7ff;
1508 :
1509 : assign wr_mscause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSCAUSE);
1510 :
1511 : assign ifu_mscause[3:0] = (dec_tlu_packet_r.icaf_type[1:0] == 2'b00) ? 4'b1001 :
1512 : {2'b00 , dec_tlu_packet_r.icaf_type[1:0]} ;
1513 :
1514 : assign mscause_type[3:0] = ( ({4{lsu_i0_exc_r}} & lsu_error_pkt_r.mscause[3:0]) |
1515 : ({4{i0_trigger_hit_r}} & 4'b0001) |
1516 : ({4{ebreak_r}} & 4'b0010) |
1517 : ({4{inst_acc_r}} & ifu_mscause[3:0])
1518 : );
1519 :
1520 : assign mscause_ns[3:0] = ( ({4{exc_or_int_valid_r}} & mscause_type[3:0]) |
1521 : ({4{ wr_mscause_r & ~exc_or_int_valid_r}} & dec_csr_wrdata_r[3:0]) |
1522 : ({4{~wr_mscause_r & ~exc_or_int_valid_r}} & mscause[3:0])
1523 : );
1524 :
1525 : rvdff #(4) mscause_ff (.*, .clk(e4e5_int_clk), .din(mscause_ns[3:0]), .dout(mscause[3:0]));
1526 : // ----------------------------------------------------------------------
1527 : // MTVAL (RW)
1528 : // [31:0] : Exception address if relevant
1529 : localparam MTVAL = 12'h343;
1530 :
1531 : assign wr_mtval_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTVAL);
1532 : assign mtval_capture_pc_r = exc_or_int_valid_r & (ebreak_r | (inst_acc_r & ~inst_acc_second_r) | mepc_trigger_hit_sel_pc_r) & ~take_nmi;
1533 : assign mtval_capture_pc_plus2_r = exc_or_int_valid_r & (inst_acc_r & inst_acc_second_r) & ~take_nmi;
1534 : assign mtval_capture_inst_r = exc_or_int_valid_r & illegal_r & ~take_nmi;
1535 : assign mtval_capture_lsu_r = exc_or_int_valid_r & lsu_exc_valid_r & ~take_nmi;
1536 : assign mtval_clear_r = exc_or_int_valid_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_capture_lsu_r & ~mepc_trigger_hit_sel_pc_r;
1537 :
1538 :
1539 : assign mtval_ns[31:0] = (({32{mtval_capture_pc_r}} & {pc_r[31:1], 1'b0}) |
1540 : ({32{mtval_capture_pc_plus2_r}} & {pc_r[31:1] + 31'b1, 1'b0}) |
1541 : ({32{mtval_capture_inst_r}} & dec_illegal_inst[31:0]) |
1542 : ({32{mtval_capture_lsu_r}} & lsu_error_pkt_addr_r[31:0]) |
1543 : ({32{wr_mtval_r & ~interrupt_valid_r}} & dec_csr_wrdata_r[31:0]) |
1544 : ({32{~take_nmi & ~wr_mtval_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_clear_r & ~mtval_capture_lsu_r}} & mtval[31:0]) );
1545 :
1546 :
1547 : rvdffe #(32) mtval_ff (.*, .en(tlu_flush_lower_r | wr_mtval_r), .din(mtval_ns[31:0]), .dout(mtval[31:0]));
1548 :
1549 : // ----------------------------------------------------------------------
1550 : // MSECCFG
1551 : // [31:3] : Reserved, read 0x0
1552 : // [2] : RLB
1553 : // [1] : MMWP
1554 : // [0] : MML
1555 :
1556 : `ifdef RV_USER_MODE
1557 :
1558 : localparam MSECCFG = 12'h747;
1559 : localparam MSECCFGH = 12'h757;
1560 :
1561 : // Detect if any PMP region is locked regardless of being enabled. This is
1562 : // necessary for mseccfg.RLB bit write behavior
1563 0 : logic [pt.PMP_ENTRIES-1:0] pmp_region_locked;
1564 : for (genvar r = 0; r < pt.PMP_ENTRIES; r++) begin : g_regions
1565 : assign pmp_region_locked[r] = pmp_pmpcfg[r].lock;
1566 : end
1567 :
1568 10 : logic pmp_any_region_locked;
1569 : assign pmp_any_region_locked = |pmp_region_locked;
1570 :
1571 : // mseccfg
1572 : assign wr_mseccfg_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MSECCFG);
1573 : rvdffs #(3) mseccfg_ff (.*, .clk(csr_wr_clk), .en(wr_mseccfg_r), .din(mseccfg_ns), .dout(mseccfg));
1574 :
1575 : assign mseccfg_ns = {
1576 : pmp_any_region_locked ?
1577 : (dec_csr_wrdata_r[MSECCFG_RLB] & mseccfg[MSECCFG_RLB]) : // When any PMP region is locked this bit can only be cleared
1578 : dec_csr_wrdata_r[MSECCFG_RLB], // Otherwise regularly writeable
1579 : dec_csr_wrdata_r[MSECCFG_MMWP] | mseccfg[MSECCFG_MMWP], // Sticky bit, can only be set but not cleared
1580 : dec_csr_wrdata_r[MSECCFG_MML ] | mseccfg[MSECCFG_MML ] // Sticky bit, can only be set but never cleared
1581 : };
1582 :
1583 : `endif
1584 :
1585 : // ----------------------------------------------------------------------
1586 : // MCGC (RW) Clock gating control
1587 : // [31:10]: Reserved, reads 0x0
1588 : // [9] : picio_clk_override
1589 : // [7] : dec_clk_override
1590 : // [6] : Unused
1591 : // [5] : ifu_clk_override
1592 : // [4] : lsu_clk_override
1593 : // [3] : bus_clk_override
1594 : // [2] : pic_clk_override
1595 : // [1] : dccm_clk_override
1596 : // [0] : icm_clk_override
1597 : //
1598 : localparam MCGC = 12'h7f8;
1599 : assign wr_mcgc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCGC);
1600 :
1601 : assign mcgc_ns[9:0] = wr_mcgc_r ? {~dec_csr_wrdata_r[9], dec_csr_wrdata_r[8:0]} : mcgc_int[9:0];
1602 : rvdffe #(10) mcgc_ff (.*, .en(wr_mcgc_r), .din(mcgc_ns[9:0]), .dout(mcgc_int[9:0]));
1603 :
1604 : assign mcgc[9:0] = {~mcgc_int[9], mcgc_int[8:0]};
1605 :
1606 : assign dec_tlu_picio_clk_override= mcgc[9];
1607 : assign dec_tlu_misc_clk_override = mcgc[8];
1608 : assign dec_tlu_dec_clk_override = mcgc[7];
1609 : //sign dec_tlu_exu_clk_override = mcgc[6];
1610 : assign dec_tlu_ifu_clk_override = mcgc[5];
1611 : assign dec_tlu_lsu_clk_override = mcgc[4];
1612 : assign dec_tlu_bus_clk_override = mcgc[3];
1613 : assign dec_tlu_pic_clk_override = mcgc[2];
1614 : assign dec_tlu_dccm_clk_override = mcgc[1];
1615 : assign dec_tlu_icm_clk_override = mcgc[0];
1616 :
1617 : // ----------------------------------------------------------------------
1618 : // MFDC (RW) Feature Disable Control
1619 : // [31:19] : Reserved, reads 0x0
1620 : // [18:16] : DMA QoS Prty
1621 : // [15:13] : Reserved, reads 0x0
1622 : // [12] : Disable trace
1623 : // [11] : Disable external load forwarding
1624 : // [10] : Disable dual issue
1625 : // [9] : Disable pic multiple ints
1626 : // [8] : Disable core ecc
1627 : // [7] : Disable secondary alu?s
1628 : // [6] : Unused, 0x0
1629 : // [5] : Disable non-blocking loads/divides
1630 : // [4] : Disable fast divide
1631 : // [3] : Disable branch prediction and return stack
1632 : // [2] : Disable write buffer coalescing
1633 : // [1] : Disable load misses that bypass the write buffer
1634 : // [0] : Disable pipelining - Enable single instruction execution
1635 : //
1636 : localparam MFDC = 12'h7f9;
1637 :
1638 : assign wr_mfdc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDC);
1639 :
1640 : rvdffe #(16) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[15:0]}), .dout(mfdc_int[15:0]));
1641 :
1642 : // flip poweron value of bit 6 for AXI build
1643 : if(pt.BUILD_AXI4==1) begin : axi4
1644 : // flip poweron valid of bit 12
1645 : assign mfdc_ns[15:0] = {~dec_csr_wrdata_r[18:16], dec_csr_wrdata_r[12], dec_csr_wrdata_r[11:7], ~dec_csr_wrdata_r[6], dec_csr_wrdata_r[5:0]};
1646 : assign mfdc[18:0] = {~mfdc_int[15:13], 3'b0, mfdc_int[12], mfdc_int[11:7], ~mfdc_int[6], mfdc_int[5:0]};
1647 : end
1648 : else begin
1649 : // flip poweron valid of bit 12
1650 : assign mfdc_ns[15:0] = {~dec_csr_wrdata_r[18:16],dec_csr_wrdata_r[12:0]};
1651 : assign mfdc[18:0] = {~mfdc_int[15:13], 3'b0, mfdc_int[12:0]};
1652 : end
1653 :
1654 :
1655 : assign dec_tlu_dma_qos_prty[2:0] = mfdc[18:16];
1656 : assign dec_tlu_trace_disable = mfdc[12];
1657 : assign dec_tlu_external_ldfwd_disable = mfdc[11];
1658 : assign dec_tlu_core_ecc_disable = mfdc[8];
1659 : assign dec_tlu_sideeffect_posted_disable = mfdc[6];
1660 : assign dec_tlu_bpred_disable = mfdc[3];
1661 : assign dec_tlu_wb_coalescing_disable = mfdc[2];
1662 : assign dec_tlu_pipelining_disable = mfdc[0];
1663 :
1664 : // ----------------------------------------------------------------------
1665 : // MCPC (RW) Pause counter
1666 : // [31:0] : Reads 0x0, decs in the wb register in decode_ctl
1667 :
1668 : assign dec_tlu_wr_pause_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCPC) & ~interrupt_valid_r & ~take_ext_int_start;
1669 :
1670 : // ----------------------------------------------------------------------
1671 : // MRAC (RW)
1672 : // [31:0] : Region Access Control Register, 16 regions, {side_effect, cachable} pairs
1673 : localparam MRAC = 12'h7c0;
1674 :
1675 : assign wr_mrac_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MRAC);
1676 :
1677 : // prevent pairs of 0x11, side_effect and cacheable
1678 : assign mrac_in[31:0] = {dec_csr_wrdata_r[31], dec_csr_wrdata_r[30] & ~dec_csr_wrdata_r[31],
1679 : dec_csr_wrdata_r[29], dec_csr_wrdata_r[28] & ~dec_csr_wrdata_r[29],
1680 : dec_csr_wrdata_r[27], dec_csr_wrdata_r[26] & ~dec_csr_wrdata_r[27],
1681 : dec_csr_wrdata_r[25], dec_csr_wrdata_r[24] & ~dec_csr_wrdata_r[25],
1682 : dec_csr_wrdata_r[23], dec_csr_wrdata_r[22] & ~dec_csr_wrdata_r[23],
1683 : dec_csr_wrdata_r[21], dec_csr_wrdata_r[20] & ~dec_csr_wrdata_r[21],
1684 : dec_csr_wrdata_r[19], dec_csr_wrdata_r[18] & ~dec_csr_wrdata_r[19],
1685 : dec_csr_wrdata_r[17], dec_csr_wrdata_r[16] & ~dec_csr_wrdata_r[17],
1686 : dec_csr_wrdata_r[15], dec_csr_wrdata_r[14] & ~dec_csr_wrdata_r[15],
1687 : dec_csr_wrdata_r[13], dec_csr_wrdata_r[12] & ~dec_csr_wrdata_r[13],
1688 : dec_csr_wrdata_r[11], dec_csr_wrdata_r[10] & ~dec_csr_wrdata_r[11],
1689 : dec_csr_wrdata_r[9], dec_csr_wrdata_r[8] & ~dec_csr_wrdata_r[9],
1690 : dec_csr_wrdata_r[7], dec_csr_wrdata_r[6] & ~dec_csr_wrdata_r[7],
1691 : dec_csr_wrdata_r[5], dec_csr_wrdata_r[4] & ~dec_csr_wrdata_r[5],
1692 : dec_csr_wrdata_r[3], dec_csr_wrdata_r[2] & ~dec_csr_wrdata_r[3],
1693 : dec_csr_wrdata_r[1], dec_csr_wrdata_r[0] & ~dec_csr_wrdata_r[1]};
1694 :
1695 : rvdffe #(32) mrac_ff (.*, .en(wr_mrac_r), .din(mrac_in[31:0]), .dout(mrac[31:0]));
1696 :
1697 : // drive to LSU/IFU
1698 : assign dec_tlu_mrac_ff[31:0] = mrac[31:0];
1699 :
1700 : // ----------------------------------------------------------------------
1701 : // MDEAU (WAR0)
1702 : // [31:0] : Dbus Error Address Unlock register
1703 : //
1704 : localparam MDEAU = 12'hbc0;
1705 :
1706 : assign wr_mdeau_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDEAU);
1707 :
1708 :
1709 : // ----------------------------------------------------------------------
1710 : // MDSEAC (R)
1711 : // [31:0] : Dbus Store Error Address Capture register
1712 : //
1713 : localparam MDSEAC = 12'hfc0;
1714 :
1715 : // only capture error bus if the MDSEAC reg is not locked
1716 : assign mdseac_locked_ns = mdseac_en | (mdseac_locked_f & ~wr_mdeau_r);
1717 :
1718 : assign mdseac_en = (lsu_imprecise_error_store_any | lsu_imprecise_error_load_any) & ~nmi_int_detected_f & ~mdseac_locked_f;
1719 :
1720 : rvdffe #(32) mdseac_ff (.*, .en(mdseac_en), .din(lsu_imprecise_error_addr_any[31:0]), .dout(mdseac[31:0]));
1721 :
1722 : // ----------------------------------------------------------------------
1723 : // MPMC (R0W1)
1724 : // [0] : FW halt
1725 : // [1] : Set MSTATUS[MIE] on halt
1726 :
1727 : localparam MPMC = 12'h7c6;
1728 :
1729 : assign wr_mpmc_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MPMC);
1730 :
1731 : // allow the cycle of the dbg halt flush that contains the wr_mpmc_r to
1732 : // set the mstatus bit potentially, use delayed version of internal dbg halt.
1733 : assign fw_halt_req = wr_mpmc_r & dec_csr_wrdata_r[0] & ~internal_dbg_halt_mode_f2 & ~ext_int_freeze_d1;
1734 :
1735 : assign fw_halted_ns = (fw_halt_req | fw_halted) & ~set_mie_pmu_fw_halt;
1736 : assign mpmc_b_ns[1] = wr_mpmc_r ? ~dec_csr_wrdata_r[1] : ~mpmc[1];
1737 : rvdff #(1) mpmc_ff (.*, .clk(csr_wr_clk), .din(mpmc_b_ns[1]), .dout(mpmc_b[1]));
1738 : assign mpmc[1] = ~mpmc_b[1];
1739 :
1740 : // ----------------------------------------------------------------------
1741 : // MICECT (I-Cache error counter/threshold)
1742 : // [31:27] : Icache parity error threshold
1743 : // [26:0] : Icache parity error count
1744 : localparam MICECT = 12'h7f0;
1745 :
1746 : assign csr_sat[31:27] = (dec_csr_wrdata_r[31:27] > 5'd26) ? 5'd26 : dec_csr_wrdata_r[31:27];
1747 :
1748 : assign wr_micect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MICECT);
1749 : assign micect_inc[26:0] = micect[26:0] + {26'b0, ic_perr_r};
1750 : assign micect_ns = wr_micect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {micect[31:27], micect_inc[26:0]};
1751 :
1752 : rvdffe #(32) micect_ff (.*, .en(wr_micect_r | ic_perr_r), .din(micect_ns[31:0]), .dout(micect[31:0]));
1753 :
1754 : assign mice_ce_req = |({32'hffffffff << micect[31:27]} & {5'b0, micect[26:0]});
1755 :
1756 : // ----------------------------------------------------------------------
1757 : // MICCMECT (ICCM error counter/threshold)
1758 : // [31:27] : ICCM parity error threshold
1759 : // [26:0] : ICCM parity error count
1760 : localparam MICCMECT = 12'h7f1;
1761 :
1762 : assign wr_miccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MICCMECT);
1763 : assign miccmect_inc[26:0] = miccmect[26:0] + {26'b0, iccm_sbecc_r | iccm_dma_sb_error};
1764 : assign miccmect_ns = wr_miccmect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {miccmect[31:27], miccmect_inc[26:0]};
1765 :
1766 : rvdffe #(32) miccmect_ff (.*, .clk(free_l2clk), .en(wr_miccmect_r | iccm_sbecc_r | iccm_dma_sb_error), .din(miccmect_ns[31:0]), .dout(miccmect[31:0]));
1767 :
1768 : assign miccme_ce_req = |({32'hffffffff << miccmect[31:27]} & {5'b0, miccmect[26:0]});
1769 :
1770 : // ----------------------------------------------------------------------
1771 : // MDCCMECT (DCCM error counter/threshold)
1772 : // [31:27] : DCCM parity error threshold
1773 : // [26:0] : DCCM parity error count
1774 : localparam MDCCMECT = 12'h7f2;
1775 :
1776 : assign wr_mdccmect_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MDCCMECT);
1777 : assign mdccmect_inc[26:0] = mdccmect[26:0] + {26'b0, lsu_single_ecc_error_r_d1};
1778 : assign mdccmect_ns = wr_mdccmect_r ? {csr_sat[31:27], dec_csr_wrdata_r[26:0]} : {mdccmect[31:27], mdccmect_inc[26:0]};
1779 :
1780 : rvdffe #(32) mdccmect_ff (.*, .clk(free_l2clk), .en(wr_mdccmect_r | lsu_single_ecc_error_r_d1), .din(mdccmect_ns[31:0]), .dout(mdccmect[31:0]));
1781 :
1782 : assign mdccme_ce_req = |({32'hffffffff << mdccmect[31:27]} & {5'b0, mdccmect[26:0]});
1783 :
1784 :
1785 : // ----------------------------------------------------------------------
1786 : // MFDHT (Force Debug Halt Threshold)
1787 : // [5:1] : Halt timeout threshold (power of 2)
1788 : // [0] : Halt timeout enabled
1789 : localparam MFDHT = 12'h7ce;
1790 :
1791 : assign wr_mfdht_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHT);
1792 :
1793 : assign mfdht_ns[5:0] = wr_mfdht_r ? dec_csr_wrdata_r[5:0] : mfdht[5:0];
1794 :
1795 : rvdffs #(6) mfdht_ff (.*, .clk(csr_wr_clk), .en(wr_mfdht_r), .din(mfdht_ns[5:0]), .dout(mfdht[5:0]));
1796 :
1797 : // ----------------------------------------------------------------------
1798 : // MFDHS(RW)
1799 : // [1] : LSU operation pending when debug halt threshold reached
1800 : // [0] : IFU operation pending when debug halt threshold reached
1801 :
1802 : localparam MFDHS = 12'h7cf;
1803 :
1804 : assign wr_mfdhs_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MFDHS);
1805 :
1806 : assign mfdhs_ns[1:0] = wr_mfdhs_r ? dec_csr_wrdata_r[1:0] : ((dbg_tlu_halted & ~dbg_tlu_halted_f) ? {~lsu_idle_any_f, ~ifu_miss_state_idle_f} : mfdhs[1:0]);
1807 :
1808 : rvdffs #(2) mfdhs_ff (.*, .clk(free_clk), .en(wr_mfdhs_r | dbg_tlu_halted), .din(mfdhs_ns[1:0]), .dout(mfdhs[1:0]));
1809 :
1810 : assign force_halt_ctr[31:0] = debug_halt_req_f ? (force_halt_ctr_f[31:0] + 32'b1) : (dbg_tlu_halted_f ? 32'b0 : force_halt_ctr_f[31:0]);
1811 :
1812 : rvdffe #(32) forcehaltctr_ff (.*, .en(mfdht[0]), .din(force_halt_ctr[31:0]), .dout(force_halt_ctr_f[31:0]));
1813 :
1814 : assign force_halt = mfdht[0] & |(force_halt_ctr_f[31:0] & (32'hffffffff << mfdht[5:1]));
1815 :
1816 :
1817 : // ----------------------------------------------------------------------
1818 : // MEIVT (External Interrupt Vector Table (R/W))
1819 : // [31:10]: Base address (R/W)
1820 : // [9:0] : Reserved, reads 0x0
1821 : localparam MEIVT = 12'hbc8;
1822 :
1823 : assign wr_meivt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIVT);
1824 :
1825 : rvdffe #(22) meivt_ff (.*, .en(wr_meivt_r), .din(dec_csr_wrdata_r[31:10]), .dout(meivt[31:10]));
1826 :
1827 :
1828 : // ----------------------------------------------------------------------
1829 : // MEIHAP (External Interrupt Handler Access Pointer (R))
1830 : // [31:10]: Base address (R/W)
1831 : // [9:2] : ClaimID (R)
1832 : // [1:0] : Reserved, 0x0
1833 : localparam MEIHAP = 12'hfc8;
1834 :
1835 : assign wr_meihap_r = wr_meicpct_r;
1836 :
1837 : rvdffe #(8) meihap_ff (.*, .en(wr_meihap_r), .din(pic_claimid[7:0]), .dout(meihap[9:2]));
1838 :
1839 : assign dec_tlu_meihap[31:2] = {meivt[31:10], meihap[9:2]};
1840 : // ----------------------------------------------------------------------
1841 : // MEICURPL (R/W)
1842 : // [31:4] : Reserved (read 0x0)
1843 : // [3:0] : CURRPRI - Priority level of current interrupt service routine (R/W)
1844 : localparam MEICURPL = 12'hbcc;
1845 :
1846 : assign wr_meicurpl_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICURPL);
1847 : assign meicurpl_ns[3:0] = wr_meicurpl_r ? dec_csr_wrdata_r[3:0] : meicurpl[3:0];
1848 :
1849 : rvdff #(4) meicurpl_ff (.*, .clk(csr_wr_clk), .din(meicurpl_ns[3:0]), .dout(meicurpl[3:0]));
1850 :
1851 : // PIC needs this reg
1852 : assign dec_tlu_meicurpl[3:0] = meicurpl[3:0];
1853 :
1854 :
1855 : // ----------------------------------------------------------------------
1856 : // MEICIDPL (R/W)
1857 : // [31:4] : Reserved (read 0x0)
1858 : // [3:0] : External Interrupt Claim ID's Priority Level Register
1859 : localparam MEICIDPL = 12'hbcb;
1860 :
1861 : assign wr_meicidpl_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICIDPL)) | take_ext_int_start;
1862 :
1863 : assign meicidpl_ns[3:0] = wr_meicpct_r ? pic_pl[3:0] : (wr_meicidpl_r ? dec_csr_wrdata_r[3:0] : meicidpl[3:0]);
1864 :
1865 :
1866 : // ----------------------------------------------------------------------
1867 : // MEICPCT (Capture CLAIMID in MEIHAP and PL in MEICIDPL
1868 : // [31:1] : Reserved (read 0x0)
1869 : // [0] : Capture (W1, Read 0)
1870 : localparam MEICPCT = 12'hbca;
1871 :
1872 : assign wr_meicpct_r = (dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEICPCT)) | take_ext_int_start;
1873 :
1874 : // ----------------------------------------------------------------------
1875 : // MEIPT (External Interrupt Priority Threshold)
1876 : // [31:4] : Reserved (read 0x0)
1877 : // [3:0] : PRITHRESH
1878 : localparam MEIPT = 12'hbc9;
1879 :
1880 : assign wr_meipt_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MEIPT);
1881 : assign meipt_ns[3:0] = wr_meipt_r ? dec_csr_wrdata_r[3:0] : meipt[3:0];
1882 :
1883 : rvdff #(4) meipt_ff (.*, .clk(csr_wr_clk), .din(meipt_ns[3:0]), .dout(meipt[3:0]));
1884 :
1885 : // to PIC
1886 : assign dec_tlu_meipt[3:0] = meipt[3:0];
1887 : // ----------------------------------------------------------------------
1888 : // DCSR (R/W) (Only accessible in debug mode)
1889 : // [31:28] : xdebugver (hard coded to 0x4) RO
1890 : // [27:16] : 0x0, reserved
1891 : // [15] : ebreakm
1892 : // [14] : 0x0, reserved
1893 : // [13] : ebreaks (0x0 for this core)
1894 : // [12] : ebreaku (0x0 for this core)
1895 : // [11] : stepie
1896 : // [10] : stopcount
1897 : // [9] : 0x0 //stoptime
1898 : // [8:6] : cause (RO)
1899 : // [5:4] : 0x0, reserved
1900 : // [3] : nmip
1901 : // [2] : step
1902 : // [1:0] : prv (0x3 for this core)
1903 : //
1904 : localparam DCSR = 12'h7b0;
1905 :
1906 : // RV has clarified that 'priority 4' in the spec means top priority.
1907 : // 4. single step. 3. Debugger request. 2. Ebreak. 1. Trigger.
1908 :
1909 : // RV debug spec indicates a cause priority change for trigger hits during single step.
1910 : assign trigger_hit_for_dscr_cause_r_d1 = trigger_hit_dmode_r_d1 | (trigger_hit_r_d1 & dcsr_single_step_done_f);
1911 :
1912 : assign dcsr_cause[8:6] = ( ({3{dcsr_single_step_done_f & ~ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1 & ~debug_halt_req}} & 3'b100) |
1913 : ({3{debug_halt_req & ~ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1}} & 3'b011) |
1914 : ({3{ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1}} & 3'b001) |
1915 : ({3{trigger_hit_for_dscr_cause_r_d1}} & 3'b010));
1916 :
1917 : assign wr_dcsr_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DCSR);
1918 :
1919 :
1920 :
1921 : // Multiple halt enter requests can happen before we are halted.
1922 : // We have to continue to upgrade based on dcsr_cause priority but we can't downgrade.
1923 : assign dcsr_cause_upgradeable = internal_dbg_halt_mode_f & (dcsr[8:6] == 3'b011);
1924 : assign enter_debug_halt_req_le = enter_debug_halt_req & (~dbg_tlu_halted | dcsr_cause_upgradeable);
1925 :
1926 : assign nmi_in_debug_mode = nmi_int_detected_f & internal_dbg_halt_mode_f;
1927 : assign dcsr_ns[15:2] = enter_debug_halt_req_le ? {dcsr[15:9], dcsr_cause[8:6], dcsr[5:2]} :
1928 : (wr_dcsr_r ? {dec_csr_wrdata_r[15], 3'b0, dec_csr_wrdata_r[11:10], 1'b0, dcsr[8:6], 2'b00, nmi_in_debug_mode | dcsr[3], dec_csr_wrdata_r[2]} :
1929 : {dcsr[15:4], nmi_in_debug_mode, dcsr[2]});
1930 :
1931 : rvdffe #(14) dcsr_ff (.*, .clk(free_l2clk), .en(enter_debug_halt_req_le | wr_dcsr_r | internal_dbg_halt_mode | take_nmi), .din(dcsr_ns[15:2]), .dout(dcsr[15:2]));
1932 :
1933 : // ----------------------------------------------------------------------
1934 : // DPC (R/W) (Only accessible in debug mode)
1935 : // [31:0] : Debug PC
1936 : localparam DPC = 12'h7b1;
1937 :
1938 : assign wr_dpc_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DPC);
1939 : assign dpc_capture_npc = dbg_tlu_halted & ~dbg_tlu_halted_f & ~request_debug_mode_done;
1940 : assign dpc_capture_pc = request_debug_mode_r;
1941 :
1942 : assign dpc_ns[31:1] = ( ({31{~dpc_capture_pc & ~dpc_capture_npc & wr_dpc_r}} & dec_csr_wrdata_r[31:1]) |
1943 : ({31{dpc_capture_pc}} & pc_r[31:1]) |
1944 : ({31{~dpc_capture_pc & dpc_capture_npc}} & npc_r[31:1]) );
1945 :
1946 : rvdffe #(31) dpc_ff (.*, .en(wr_dpc_r | dpc_capture_pc | dpc_capture_npc), .din(dpc_ns[31:1]), .dout(dpc[31:1]));
1947 :
1948 : // ----------------------------------------------------------------------
1949 : // DICAWICS (R/W) (Only accessible in debug mode)
1950 : // [31:25] : Reserved
1951 : // [24] : Array select, 0 is data, 1 is tag
1952 : // [23:22] : Reserved
1953 : // [21:20] : Way select
1954 : // [19:17] : Reserved
1955 : // [16:3] : Index
1956 : // [2:0] : Reserved
1957 : localparam DICAWICS = 12'h7c8;
1958 :
1959 : assign dicawics_ns[16:0] = {dec_csr_wrdata_r[24], dec_csr_wrdata_r[21:20], dec_csr_wrdata_r[16:3]};
1960 : assign wr_dicawics_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAWICS);
1961 :
1962 : rvdffe #(17) dicawics_ff (.*, .en(wr_dicawics_r), .din(dicawics_ns[16:0]), .dout(dicawics[16:0]));
1963 :
1964 : // ----------------------------------------------------------------------
1965 : // DICAD0 (R/W) (Only accessible in debug mode)
1966 : //
1967 : // If dicawics[array] is 0
1968 : // [31:0] : inst data
1969 : //
1970 : // If dicawics[array] is 1
1971 : // [31:16] : Tag
1972 : // [15:7] : Reserved
1973 : // [6:4] : LRU
1974 : // [3:1] : Reserved
1975 : // [0] : Valid
1976 : localparam DICAD0 = 12'h7c9;
1977 :
1978 : assign dicad0_ns[31:0] = wr_dicad0_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[31:0];
1979 :
1980 : assign wr_dicad0_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD0);
1981 :
1982 : rvdffe #(32) dicad0_ff (.*, .en(wr_dicad0_r | ifu_ic_debug_rd_data_valid), .din(dicad0_ns[31:0]), .dout(dicad0[31:0]));
1983 :
1984 : // ----------------------------------------------------------------------
1985 : // DICAD0H (R/W) (Only accessible in debug mode)
1986 : //
1987 : // If dicawics[array] is 0
1988 : // [63:32] : inst data
1989 : //
1990 : localparam DICAD0H = 12'h7cc;
1991 :
1992 : assign dicad0h_ns[31:0] = wr_dicad0h_r ? dec_csr_wrdata_r[31:0] : ifu_ic_debug_rd_data[63:32];
1993 :
1994 : assign wr_dicad0h_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD0H);
1995 :
1996 : rvdffe #(32) dicad0h_ff (.*, .en(wr_dicad0h_r | ifu_ic_debug_rd_data_valid), .din(dicad0h_ns[31:0]), .dout(dicad0h[31:0]));
1997 :
1998 :
1999 : if (pt.ICACHE_ECC == 1) begin : genblock1
2000 : // ----------------------------------------------------------------------
2001 : // DICAD1 (R/W) (Only accessible in debug mode)
2002 : // [6:0] : ECC
2003 : localparam DICAD1 = 12'h7ca;
2004 :
2005 : assign dicad1_ns[6:0] = wr_dicad1_r ? dec_csr_wrdata_r[6:0] : ifu_ic_debug_rd_data[70:64];
2006 :
2007 : assign wr_dicad1_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD1);
2008 :
2009 : rvdffe #(.WIDTH(7), .OVERRIDE(1)) dicad1_ff (.*, .en(wr_dicad1_r | ifu_ic_debug_rd_data_valid), .din(dicad1_ns[6:0]), .dout(dicad1_raw[6:0]));
2010 :
2011 : assign dicad1[31:0] = {25'b0, dicad1_raw[6:0]};
2012 :
2013 : end
2014 : else begin : genblock1
2015 : // ----------------------------------------------------------------------
2016 : // DICAD1 (R/W) (Only accessible in debug mode)
2017 : // [3:0] : Parity
2018 : localparam DICAD1 = 12'h7ca;
2019 :
2020 : assign dicad1_ns[3:0] = wr_dicad1_r ? dec_csr_wrdata_r[3:0] : ifu_ic_debug_rd_data[67:64];
2021 :
2022 : assign wr_dicad1_r = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAD1);
2023 :
2024 : rvdffs #(4) dicad1_ff (.*, .clk(free_clk), .en(wr_dicad1_r | ifu_ic_debug_rd_data_valid), .din(dicad1_ns[3:0]), .dout(dicad1_raw[3:0]));
2025 :
2026 : assign dicad1[31:0] = {28'b0, dicad1_raw[3:0]};
2027 : end
2028 : // ----------------------------------------------------------------------
2029 : // DICAGO (R/W) (Only accessible in debug mode)
2030 : // [0] : Go
2031 : localparam DICAGO = 12'h7cb;
2032 :
2033 : if (pt.ICACHE_ECC == 1)
2034 : assign dec_tlu_ic_diag_pkt.icache_wrdata[70:0] = { dicad1[6:0], dicad0h[31:0], dicad0[31:0]};
2035 : else
2036 : assign dec_tlu_ic_diag_pkt.icache_wrdata[70:0] = {3'b0, dicad1[3:0], dicad0h[31:0], dicad0[31:0]};
2037 :
2038 :
2039 : assign dec_tlu_ic_diag_pkt.icache_dicawics[16:0] = dicawics[16:0];
2040 :
2041 : assign icache_rd_valid = allow_dbg_halt_csr_write & dec_csr_any_unq_d & dec_i0_decode_d & ~dec_csr_wen_unq_d & (dec_csr_rdaddr_d[11:0] == DICAGO);
2042 : assign icache_wr_valid = allow_dbg_halt_csr_write & dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == DICAGO);
2043 :
2044 :
2045 : assign dec_tlu_ic_diag_pkt.icache_rd_valid = icache_rd_valid_f;
2046 : assign dec_tlu_ic_diag_pkt.icache_wr_valid = icache_wr_valid_f;
2047 :
2048 : // ----------------------------------------------------------------------
2049 : // MTSEL (R/W)
2050 : // [1:0] : Trigger select : 00, 01, 10 are data/address triggers. 11 is inst count
2051 : localparam MTSEL = 12'h7a0;
2052 :
2053 : assign wr_mtsel_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTSEL);
2054 : assign mtsel_ns[1:0] = wr_mtsel_r ? {dec_csr_wrdata_r[1:0]} : mtsel[1:0];
2055 :
2056 : rvdff #(2) mtsel_ff (.*, .clk(csr_wr_clk), .din(mtsel_ns[1:0]), .dout(mtsel[1:0]));
2057 :
2058 : // ----------------------------------------------------------------------
2059 : // MTDATA1 (R/W)
2060 : // [31:0] : Trigger Data 1
2061 : localparam MTDATA1 = 12'h7a1;
2062 :
2063 : // for triggers 0, 1, 2 and 3 aka Match Control
2064 : // [31:28] : type, hard coded to 0x2
2065 : // [27] : dmode
2066 : // [26:21] : hard coded to 0x1f
2067 : // [20] : hit
2068 : // [19] : select (0 - address, 1 - data)
2069 : // [18] : timing, always 'before', reads 0x0
2070 : // [17:12] : action, bits [17:13] not implemented and reads 0x0
2071 : // [11] : chain
2072 : // [10:7] : match, bits [10:8] not implemented and reads 0x0
2073 : // [6] : M
2074 : // [5:3] : not implemented, reads 0x0
2075 : // [2] : execute
2076 : // [1] : store
2077 : // [0] : load
2078 : //
2079 : // decoder ring
2080 : // [27] : => 9
2081 : // [20] : => 8
2082 : // [19] : => 7
2083 : // [12] : => 6
2084 : // [11] : => 5
2085 : // [7] : => 4
2086 : // [6] : => 3
2087 : // [2] : => 2
2088 : // [1] : => 1
2089 : // [0] : => 0
2090 :
2091 :
2092 : // don't allow setting load-data.
2093 : assign tdata_load = dec_csr_wrdata_r[0] & ~dec_csr_wrdata_r[19];
2094 : // don't allow setting execute-data.
2095 : assign tdata_opcode = dec_csr_wrdata_r[2] & ~dec_csr_wrdata_r[19];
2096 : // don't allow clearing DMODE and action=1
2097 : assign tdata_action = (dec_csr_wrdata_r[27] & dbg_tlu_halted_f) & dec_csr_wrdata_r[12];
2098 :
2099 : // Chain bit has conditions: WARL for triggers without chains. Force to zero if dmode is 0 but next trigger dmode is 1.
2100 : assign tdata_chain = mtsel[0] ? 1'b0 : // triggers 1 and 3 chain bit is always zero
2101 : mtsel[1] ? dec_csr_wrdata_r[11] & ~(mtdata1_t3[MTDATA1_DMODE] & ~dec_csr_wrdata_r[27]) : // trigger 2
2102 : dec_csr_wrdata_r[11] & ~(mtdata1_t1[MTDATA1_DMODE] & ~dec_csr_wrdata_r[27]); // trigger 0
2103 :
2104 : // Kill mtdata1 write if dmode=1 but prior trigger has dmode=0/chain=1. Only applies to T1 and T3
2105 : assign tdata_kill_write = mtsel[1] ? dec_csr_wrdata_r[27] & (~mtdata1_t2[MTDATA1_DMODE] & mtdata1_t2[MTDATA1_CHAIN]) : // trigger 3
2106 : dec_csr_wrdata_r[27] & (~mtdata1_t0[MTDATA1_DMODE] & mtdata1_t0[MTDATA1_CHAIN]) ; // trigger 1
2107 :
2108 :
2109 : assign tdata_wrdata_r[9:0] = {dec_csr_wrdata_r[27] & dbg_tlu_halted_f,
2110 : dec_csr_wrdata_r[20:19],
2111 : tdata_action,
2112 : tdata_chain,
2113 : dec_csr_wrdata_r[7:6],
2114 : tdata_opcode,
2115 : dec_csr_wrdata_r[1],
2116 : tdata_load};
2117 :
2118 : // If the DMODE bit is set, tdata1 can only be updated in debug_mode
2119 : assign wr_mtdata1_t0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b0) & (~mtdata1_t0[MTDATA1_DMODE] | dbg_tlu_halted_f);
2120 : assign mtdata1_t0_ns[9:0] = wr_mtdata1_t0_r ? tdata_wrdata_r[9:0] :
2121 : {mtdata1_t0[9], update_hit_bit_r[0] | mtdata1_t0[8], mtdata1_t0[7:0]};
2122 :
2123 : assign wr_mtdata1_t1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b01) & (~mtdata1_t1[MTDATA1_DMODE] | dbg_tlu_halted_f) & ~tdata_kill_write;
2124 : assign mtdata1_t1_ns[9:0] = wr_mtdata1_t1_r ? tdata_wrdata_r[9:0] :
2125 : {mtdata1_t1[9], update_hit_bit_r[1] | mtdata1_t1[8], mtdata1_t1[7:0]};
2126 :
2127 : assign wr_mtdata1_t2_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b10) & (~mtdata1_t2[MTDATA1_DMODE] | dbg_tlu_halted_f);
2128 : assign mtdata1_t2_ns[9:0] = wr_mtdata1_t2_r ? tdata_wrdata_r[9:0] :
2129 : {mtdata1_t2[9], update_hit_bit_r[2] | mtdata1_t2[8], mtdata1_t2[7:0]};
2130 :
2131 : assign wr_mtdata1_t3_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA1) & (mtsel[1:0] == 2'b11) & (~mtdata1_t3[MTDATA1_DMODE] | dbg_tlu_halted_f) & ~tdata_kill_write;
2132 : assign mtdata1_t3_ns[9:0] = wr_mtdata1_t3_r ? tdata_wrdata_r[9:0] :
2133 : {mtdata1_t3[9], update_hit_bit_r[3] | mtdata1_t3[8], mtdata1_t3[7:0]};
2134 :
2135 :
2136 : rvdffe #(10) mtdata1_t0_ff (.*, .en(trigger_enabled[0] | wr_mtdata1_t0_r), .din(mtdata1_t0_ns[9:0]), .dout(mtdata1_t0[9:0]));
2137 : rvdffe #(10) mtdata1_t1_ff (.*, .en(trigger_enabled[1] | wr_mtdata1_t1_r), .din(mtdata1_t1_ns[9:0]), .dout(mtdata1_t1[9:0]));
2138 : rvdffe #(10) mtdata1_t2_ff (.*, .en(trigger_enabled[2] | wr_mtdata1_t2_r), .din(mtdata1_t2_ns[9:0]), .dout(mtdata1_t2[9:0]));
2139 : rvdffe #(10) mtdata1_t3_ff (.*, .en(trigger_enabled[3] | wr_mtdata1_t3_r), .din(mtdata1_t3_ns[9:0]), .dout(mtdata1_t3[9:0]));
2140 :
2141 : assign mtdata1_tsel_out[31:0] = ( ({32{(mtsel[1:0] == 2'b00)}} & {4'h2, mtdata1_t0[9], 6'b011111, mtdata1_t0[8:7], 6'b0, mtdata1_t0[6:5], 3'b0, mtdata1_t0[4:3], 3'b0, mtdata1_t0[2:0]}) |
2142 : ({32{(mtsel[1:0] == 2'b01)}} & {4'h2, mtdata1_t1[9], 6'b011111, mtdata1_t1[8:7], 6'b0, mtdata1_t1[6:5], 3'b0, mtdata1_t1[4:3], 3'b0, mtdata1_t1[2:0]}) |
2143 : ({32{(mtsel[1:0] == 2'b10)}} & {4'h2, mtdata1_t2[9], 6'b011111, mtdata1_t2[8:7], 6'b0, mtdata1_t2[6:5], 3'b0, mtdata1_t2[4:3], 3'b0, mtdata1_t2[2:0]}) |
2144 : ({32{(mtsel[1:0] == 2'b11)}} & {4'h2, mtdata1_t3[9], 6'b011111, mtdata1_t3[8:7], 6'b0, mtdata1_t3[6:5], 3'b0, mtdata1_t3[4:3], 3'b0, mtdata1_t3[2:0]}));
2145 :
2146 : assign trigger_pkt_any[0].select = mtdata1_t0[MTDATA1_SEL];
2147 : assign trigger_pkt_any[0].match = mtdata1_t0[MTDATA1_MATCH];
2148 : assign trigger_pkt_any[0].store = mtdata1_t0[MTDATA1_ST];
2149 : assign trigger_pkt_any[0].load = mtdata1_t0[MTDATA1_LD];
2150 : assign trigger_pkt_any[0].execute = mtdata1_t0[MTDATA1_EXE];
2151 : assign trigger_pkt_any[0].m = mtdata1_t0[MTDATA1_M_ENABLED];
2152 :
2153 : assign trigger_pkt_any[1].select = mtdata1_t1[MTDATA1_SEL];
2154 : assign trigger_pkt_any[1].match = mtdata1_t1[MTDATA1_MATCH];
2155 : assign trigger_pkt_any[1].store = mtdata1_t1[MTDATA1_ST];
2156 : assign trigger_pkt_any[1].load = mtdata1_t1[MTDATA1_LD];
2157 : assign trigger_pkt_any[1].execute = mtdata1_t1[MTDATA1_EXE];
2158 : assign trigger_pkt_any[1].m = mtdata1_t1[MTDATA1_M_ENABLED];
2159 :
2160 : assign trigger_pkt_any[2].select = mtdata1_t2[MTDATA1_SEL];
2161 : assign trigger_pkt_any[2].match = mtdata1_t2[MTDATA1_MATCH];
2162 : assign trigger_pkt_any[2].store = mtdata1_t2[MTDATA1_ST];
2163 : assign trigger_pkt_any[2].load = mtdata1_t2[MTDATA1_LD];
2164 : assign trigger_pkt_any[2].execute = mtdata1_t2[MTDATA1_EXE];
2165 : assign trigger_pkt_any[2].m = mtdata1_t2[MTDATA1_M_ENABLED];
2166 :
2167 : assign trigger_pkt_any[3].select = mtdata1_t3[MTDATA1_SEL];
2168 : assign trigger_pkt_any[3].match = mtdata1_t3[MTDATA1_MATCH];
2169 : assign trigger_pkt_any[3].store = mtdata1_t3[MTDATA1_ST];
2170 : assign trigger_pkt_any[3].load = mtdata1_t3[MTDATA1_LD];
2171 : assign trigger_pkt_any[3].execute = mtdata1_t3[MTDATA1_EXE];
2172 : assign trigger_pkt_any[3].m = mtdata1_t3[MTDATA1_M_ENABLED];
2173 :
2174 :
2175 :
2176 :
2177 :
2178 : // ----------------------------------------------------------------------
2179 : // MTDATA2 (R/W)
2180 : // [31:0] : Trigger Data 2
2181 : localparam MTDATA2 = 12'h7a2;
2182 :
2183 : // If the DMODE bit is set, tdata2 can only be updated in debug_mode
2184 : assign wr_mtdata2_t0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b0) & (~mtdata1_t0[MTDATA1_DMODE] | dbg_tlu_halted_f);
2185 : assign wr_mtdata2_t1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b01) & (~mtdata1_t1[MTDATA1_DMODE] | dbg_tlu_halted_f);
2186 : assign wr_mtdata2_t2_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b10) & (~mtdata1_t2[MTDATA1_DMODE] | dbg_tlu_halted_f);
2187 : assign wr_mtdata2_t3_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MTDATA2) & (mtsel[1:0] == 2'b11) & (~mtdata1_t3[MTDATA1_DMODE] | dbg_tlu_halted_f);
2188 :
2189 : rvdffe #(32) mtdata2_t0_ff (.*, .en(wr_mtdata2_t0_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t0[31:0]));
2190 : rvdffe #(32) mtdata2_t1_ff (.*, .en(wr_mtdata2_t1_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t1[31:0]));
2191 : rvdffe #(32) mtdata2_t2_ff (.*, .en(wr_mtdata2_t2_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t2[31:0]));
2192 : rvdffe #(32) mtdata2_t3_ff (.*, .en(wr_mtdata2_t3_r), .din(dec_csr_wrdata_r[31:0]), .dout(mtdata2_t3[31:0]));
2193 :
2194 : assign mtdata2_tsel_out[31:0] = ( ({32{(mtsel[1:0] == 2'b00)}} & mtdata2_t0[31:0]) |
2195 : ({32{(mtsel[1:0] == 2'b01)}} & mtdata2_t1[31:0]) |
2196 : ({32{(mtsel[1:0] == 2'b10)}} & mtdata2_t2[31:0]) |
2197 : ({32{(mtsel[1:0] == 2'b11)}} & mtdata2_t3[31:0]));
2198 :
2199 : assign trigger_pkt_any[0].tdata2[31:0] = mtdata2_t0[31:0];
2200 : assign trigger_pkt_any[1].tdata2[31:0] = mtdata2_t1[31:0];
2201 : assign trigger_pkt_any[2].tdata2[31:0] = mtdata2_t2[31:0];
2202 : assign trigger_pkt_any[3].tdata2[31:0] = mtdata2_t3[31:0];
2203 :
2204 :
2205 : //----------------------------------------------------------------------
2206 : // Performance Monitor Counters section starts
2207 : //----------------------------------------------------------------------
2208 : localparam MHPME_NOEVENT = 10'd0;
2209 : localparam MHPME_CLK_ACTIVE = 10'd1; // OOP - out of pipe
2210 : localparam MHPME_ICACHE_HIT = 10'd2; // OOP
2211 : localparam MHPME_ICACHE_MISS = 10'd3; // OOP
2212 : localparam MHPME_INST_COMMIT = 10'd4;
2213 : localparam MHPME_INST_COMMIT_16B = 10'd5;
2214 : localparam MHPME_INST_COMMIT_32B = 10'd6;
2215 : localparam MHPME_INST_ALIGNED = 10'd7; // OOP
2216 : localparam MHPME_INST_DECODED = 10'd8; // OOP
2217 : localparam MHPME_INST_MUL = 10'd9;
2218 : localparam MHPME_INST_DIV = 10'd10;
2219 : localparam MHPME_INST_LOAD = 10'd11;
2220 : localparam MHPME_INST_STORE = 10'd12;
2221 : localparam MHPME_INST_MALOAD = 10'd13;
2222 : localparam MHPME_INST_MASTORE = 10'd14;
2223 : localparam MHPME_INST_ALU = 10'd15;
2224 : localparam MHPME_INST_CSRREAD = 10'd16;
2225 : localparam MHPME_INST_CSRRW = 10'd17;
2226 : localparam MHPME_INST_CSRWRITE = 10'd18;
2227 : localparam MHPME_INST_EBREAK = 10'd19;
2228 : localparam MHPME_INST_ECALL = 10'd20;
2229 : localparam MHPME_INST_FENCE = 10'd21;
2230 : localparam MHPME_INST_FENCEI = 10'd22;
2231 : localparam MHPME_INST_MRET = 10'd23;
2232 : localparam MHPME_INST_BRANCH = 10'd24;
2233 : localparam MHPME_BRANCH_MP = 10'd25;
2234 : localparam MHPME_BRANCH_TAKEN = 10'd26;
2235 : localparam MHPME_BRANCH_NOTP = 10'd27;
2236 : localparam MHPME_FETCH_STALL = 10'd28; // OOP
2237 : localparam MHPME_DECODE_STALL = 10'd30; // OOP
2238 : localparam MHPME_POSTSYNC_STALL = 10'd31; // OOP
2239 : localparam MHPME_PRESYNC_STALL = 10'd32; // OOP
2240 : localparam MHPME_LSU_SB_WB_STALL = 10'd34; // OOP
2241 : localparam MHPME_DMA_DCCM_STALL = 10'd35; // OOP
2242 : localparam MHPME_DMA_ICCM_STALL = 10'd36; // OOP
2243 : localparam MHPME_EXC_TAKEN = 10'd37;
2244 : localparam MHPME_TIMER_INT_TAKEN = 10'd38;
2245 : localparam MHPME_EXT_INT_TAKEN = 10'd39;
2246 : localparam MHPME_FLUSH_LOWER = 10'd40;
2247 : localparam MHPME_BR_ERROR = 10'd41;
2248 : localparam MHPME_IBUS_TRANS = 10'd42; // OOP
2249 : localparam MHPME_DBUS_TRANS = 10'd43; // OOP
2250 : localparam MHPME_DBUS_MA_TRANS = 10'd44; // OOP
2251 : localparam MHPME_IBUS_ERROR = 10'd45; // OOP
2252 : localparam MHPME_DBUS_ERROR = 10'd46; // OOP
2253 : localparam MHPME_IBUS_STALL = 10'd47; // OOP
2254 : localparam MHPME_DBUS_STALL = 10'd48; // OOP
2255 : localparam MHPME_INT_DISABLED = 10'd49; // OOP
2256 : localparam MHPME_INT_STALLED = 10'd50; // OOP
2257 : localparam MHPME_INST_BITMANIP = 10'd54;
2258 : localparam MHPME_DBUS_LOAD = 10'd55;
2259 : localparam MHPME_DBUS_STORE = 10'd56;
2260 : // Counts even during sleep state
2261 : localparam MHPME_SLEEP_CYC = 10'd512; // OOP
2262 : localparam MHPME_DMA_READ_ALL = 10'd513; // OOP
2263 : localparam MHPME_DMA_WRITE_ALL = 10'd514; // OOP
2264 : localparam MHPME_DMA_READ_DCCM = 10'd515; // OOP
2265 : localparam MHPME_DMA_WRITE_DCCM = 10'd516; // OOP
2266 :
2267 : // Pack the event selects into a vector for genvar
2268 : assign mhpme_vec[0][9:0] = mhpme3[9:0];
2269 : assign mhpme_vec[1][9:0] = mhpme4[9:0];
2270 : assign mhpme_vec[2][9:0] = mhpme5[9:0];
2271 : assign mhpme_vec[3][9:0] = mhpme6[9:0];
2272 :
2273 : // only consider committed itypes
2274 : //logic [3:0] pmu_i0_itype_qual;
2275 : assign pmu_i0_itype_qual[3:0] = dec_tlu_packet_r.pmu_i0_itype[3:0] & {4{tlu_i0_commit_cmt}};
2276 :
2277 : // Generate the muxed incs for all counters based on event type
2278 : for (genvar i=0 ; i < 4; i++) begin
2279 : assign mhpmc_inc_r[i] = {{~mcountinhibit[i+3]}} &
2280 : (
2281 : ({1{(mhpme_vec[i][9:0] == MHPME_CLK_ACTIVE )}} & 1'b1) |
2282 : ({1{(mhpme_vec[i][9:0] == MHPME_ICACHE_HIT )}} & {ifu_pmu_ic_hit}) |
2283 : ({1{(mhpme_vec[i][9:0] == MHPME_ICACHE_MISS )}} & {ifu_pmu_ic_miss}) |
2284 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_COMMIT )}} & {tlu_i0_commit_cmt & ~illegal_r}) |
2285 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_COMMIT_16B )}} & {tlu_i0_commit_cmt & ~exu_pmu_i0_pc4 & ~illegal_r}) |
2286 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_COMMIT_32B )}} & {tlu_i0_commit_cmt & exu_pmu_i0_pc4 & ~illegal_r}) |
2287 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_ALIGNED )}} & ifu_pmu_instr_aligned) |
2288 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_DECODED )}} & dec_pmu_instr_decoded) |
2289 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_MUL )}} & {(pmu_i0_itype_qual == MUL)}) |
2290 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_DIV )}} & {dec_tlu_packet_r.pmu_divide & tlu_i0_commit_cmt & ~illegal_r}) |
2291 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_LOAD )}} & {(pmu_i0_itype_qual == LOAD)}) |
2292 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_STORE )}} & {(pmu_i0_itype_qual == STORE)}) |
2293 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_MALOAD )}} & {(pmu_i0_itype_qual == LOAD)} &
2294 : {1{dec_tlu_packet_r.pmu_lsu_misaligned}}) |
2295 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_MASTORE )}} & {(pmu_i0_itype_qual == STORE)} &
2296 : {1{dec_tlu_packet_r.pmu_lsu_misaligned}}) |
2297 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_ALU )}} & {(pmu_i0_itype_qual == ALU)}) |
2298 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_CSRREAD )}} & {(pmu_i0_itype_qual == CSRREAD)}) |
2299 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_CSRWRITE )}} & {(pmu_i0_itype_qual == CSRWRITE)})|
2300 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_CSRRW )}} & {(pmu_i0_itype_qual == CSRRW)}) |
2301 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_EBREAK )}} & {(pmu_i0_itype_qual == EBREAK)}) |
2302 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_ECALL )}} & {(pmu_i0_itype_qual == ECALL)}) |
2303 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_FENCE )}} & {(pmu_i0_itype_qual == FENCE)}) |
2304 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_FENCEI )}} & {(pmu_i0_itype_qual == FENCEI)}) |
2305 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_MRET )}} & {(pmu_i0_itype_qual == MRET)}) |
2306 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_BRANCH )}} & {
2307 : ((pmu_i0_itype_qual == CONDBR) | (pmu_i0_itype_qual == JAL))}) |
2308 : ({1{(mhpme_vec[i][9:0] == MHPME_BRANCH_MP )}} & {exu_pmu_i0_br_misp & tlu_i0_commit_cmt & ~illegal_r}) |
2309 : ({1{(mhpme_vec[i][9:0] == MHPME_BRANCH_TAKEN )}} & {exu_pmu_i0_br_ataken & tlu_i0_commit_cmt & ~illegal_r}) |
2310 : ({1{(mhpme_vec[i][9:0] == MHPME_BRANCH_NOTP )}} & {dec_tlu_packet_r.pmu_i0_br_unpred & tlu_i0_commit_cmt & ~illegal_r}) |
2311 : ({1{(mhpme_vec[i][9:0] == MHPME_FETCH_STALL )}} & { ifu_pmu_fetch_stall}) |
2312 : ({1{(mhpme_vec[i][9:0] == MHPME_DECODE_STALL )}} & { dec_pmu_decode_stall}) |
2313 : ({1{(mhpme_vec[i][9:0] == MHPME_POSTSYNC_STALL )}} & {dec_pmu_postsync_stall}) |
2314 : ({1{(mhpme_vec[i][9:0] == MHPME_PRESYNC_STALL )}} & {dec_pmu_presync_stall}) |
2315 : ({1{(mhpme_vec[i][9:0] == MHPME_LSU_SB_WB_STALL )}} & { lsu_store_stall_any}) |
2316 : ({1{(mhpme_vec[i][9:0] == MHPME_DMA_DCCM_STALL )}} & { dma_dccm_stall_any}) |
2317 : ({1{(mhpme_vec[i][9:0] == MHPME_DMA_ICCM_STALL )}} & { dma_iccm_stall_any}) |
2318 : ({1{(mhpme_vec[i][9:0] == MHPME_EXC_TAKEN )}} & { (i0_exception_valid_r | i0_trigger_hit_r | lsu_exc_valid_r)}) |
2319 : ({1{(mhpme_vec[i][9:0] == MHPME_TIMER_INT_TAKEN )}} & { take_timer_int | take_int_timer0_int | take_int_timer1_int}) |
2320 : ({1{(mhpme_vec[i][9:0] == MHPME_EXT_INT_TAKEN )}} & { take_ext_int}) |
2321 : ({1{(mhpme_vec[i][9:0] == MHPME_FLUSH_LOWER )}} & { tlu_flush_lower_r}) |
2322 : ({1{(mhpme_vec[i][9:0] == MHPME_BR_ERROR )}} & {(dec_tlu_br0_error_r | dec_tlu_br0_start_error_r) & rfpc_i0_r}) |
2323 : ({1{(mhpme_vec[i][9:0] == MHPME_IBUS_TRANS )}} & {ifu_pmu_bus_trxn}) |
2324 : ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_TRANS )}} & {lsu_pmu_bus_trxn}) |
2325 : ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_MA_TRANS )}} & {lsu_pmu_bus_misaligned}) |
2326 : ({1{(mhpme_vec[i][9:0] == MHPME_IBUS_ERROR )}} & {ifu_pmu_bus_error}) |
2327 : ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_ERROR )}} & {lsu_pmu_bus_error}) |
2328 : ({1{(mhpme_vec[i][9:0] == MHPME_IBUS_STALL )}} & {ifu_pmu_bus_busy}) |
2329 : ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_STALL )}} & {lsu_pmu_bus_busy}) |
2330 : ({1{(mhpme_vec[i][9:0] == MHPME_INT_DISABLED )}} & {~mstatus[MSTATUS_MIE]}) |
2331 : ({1{(mhpme_vec[i][9:0] == MHPME_INT_STALLED )}} & {~mstatus[MSTATUS_MIE] & |(mip[5:0] & mie[5:0])}) |
2332 : ({1{(mhpme_vec[i][9:0] == MHPME_INST_BITMANIP )}} & {(pmu_i0_itype_qual == BITMANIPU)}) |
2333 : ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_LOAD )}} & {tlu_i0_commit_cmt & lsu_pmu_load_external_r & ~illegal_r}) |
2334 : ({1{(mhpme_vec[i][9:0] == MHPME_DBUS_STORE )}} & {tlu_i0_commit_cmt & lsu_pmu_store_external_r & ~illegal_r}) |
2335 : // These count even during sleep
2336 : ({1{(mhpme_vec[i][9:0] == MHPME_SLEEP_CYC )}} & {dec_tlu_pmu_fw_halted}) |
2337 : ({1{(mhpme_vec[i][9:0] == MHPME_DMA_READ_ALL )}} & {dma_pmu_any_read}) |
2338 : ({1{(mhpme_vec[i][9:0] == MHPME_DMA_WRITE_ALL )}} & {dma_pmu_any_write}) |
2339 : ({1{(mhpme_vec[i][9:0] == MHPME_DMA_READ_DCCM )}} & {dma_pmu_dccm_read}) |
2340 : ({1{(mhpme_vec[i][9:0] == MHPME_DMA_WRITE_DCCM )}} & {dma_pmu_dccm_write})
2341 : );
2342 : end
2343 :
2344 :
2345 : if(pt.FAST_INTERRUPT_REDIRECT) begin : genblock2
2346 :
2347 : `ifdef RV_USER_MODE
2348 : rvdffie #(33) mstatus_ff (.*, .clk(free_l2clk),
2349 : .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r,
2350 : take_ext_int_start, take_ext_int_start_d1, take_ext_int_start_d2, ext_int_freeze,
2351 : mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in,
2352 : minstret_enable, minstretl_cout_ns, fw_halted_ns,
2353 : meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted,
2354 : mstatus_ns[3:0]}),
2355 : .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1,
2356 : take_ext_int_start_d1, take_ext_int_start_d2, take_ext_int_start_d3, ext_int_freeze_d1,
2357 : mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f,
2358 : fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f,
2359 : mhpmc_inc_r_d1[3:0], perfcnt_halted_d1,
2360 : mstatus[3:0]}));
2361 : `else
2362 : rvdffie #(31) mstatus_ff (.*, .clk(free_l2clk),
2363 : .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r,
2364 : take_ext_int_start, take_ext_int_start_d1, take_ext_int_start_d2, ext_int_freeze,
2365 : mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in,
2366 : minstret_enable, minstretl_cout_ns, fw_halted_ns,
2367 : meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted,
2368 : mstatus_ns[1:0]}),
2369 : .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1,
2370 : take_ext_int_start_d1, take_ext_int_start_d2, take_ext_int_start_d3, ext_int_freeze_d1,
2371 : mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f,
2372 : fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f,
2373 : mhpmc_inc_r_d1[3:0], perfcnt_halted_d1,
2374 : mstatus[1:0]}));
2375 :
2376 : `endif
2377 :
2378 : end
2379 : else begin : genblock2
2380 : `ifdef RV_USER_MODE
2381 : rvdffie #(29) mstatus_ff (.*, .clk(free_l2clk),
2382 : .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r,
2383 : mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in,
2384 : minstret_enable, minstretl_cout_ns, fw_halted_ns,
2385 : meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted,
2386 : mstatus_ns[3:0]}),
2387 : .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1,
2388 : mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f,
2389 : fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f,
2390 : mhpmc_inc_r_d1[3:0], perfcnt_halted_d1,
2391 : mstatus[3:0]}));
2392 : `else
2393 : rvdffie #(27) mstatus_ff (.*, .clk(free_l2clk),
2394 : .din({mdseac_locked_ns, lsu_single_ecc_error_r, lsu_exc_valid_r, lsu_i0_exc_r,
2395 : mip_ns[5:0], mcyclel_cout & ~wr_mcycleh_r & mcyclel_cout_in,
2396 : minstret_enable, minstretl_cout_ns, fw_halted_ns,
2397 : meicidpl_ns[3:0], icache_rd_valid, icache_wr_valid, mhpmc_inc_r[3:0], perfcnt_halted,
2398 : mstatus_ns[1:0]}),
2399 : .dout({mdseac_locked_f, lsu_single_ecc_error_r_d1, lsu_exc_valid_r_d1, lsu_i0_exc_r_d1,
2400 : mip[5:0], mcyclel_cout_f, minstret_enable_f, minstretl_cout_f,
2401 : fw_halted, meicidpl[3:0], icache_rd_valid_f, icache_wr_valid_f,
2402 : mhpmc_inc_r_d1[3:0], perfcnt_halted_d1,
2403 : mstatus[1:0]}));
2404 : `endif
2405 : end
2406 :
2407 : assign perfcnt_halted = ((dec_tlu_dbg_halted & dcsr[DCSR_STOPC]) | dec_tlu_pmu_fw_halted);
2408 : assign perfcnt_during_sleep[3:0] = {4{~(dec_tlu_dbg_halted & dcsr[DCSR_STOPC])}} & {mhpme_vec[3][9],mhpme_vec[2][9],mhpme_vec[1][9],mhpme_vec[0][9]};
2409 :
2410 : assign dec_tlu_perfcnt0 = mhpmc_inc_r_d1[0] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[0]);
2411 : assign dec_tlu_perfcnt1 = mhpmc_inc_r_d1[1] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[1]);
2412 : assign dec_tlu_perfcnt2 = mhpmc_inc_r_d1[2] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[2]);
2413 : assign dec_tlu_perfcnt3 = mhpmc_inc_r_d1[3] & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep[3]);
2414 :
2415 : // ----------------------------------------------------------------------
2416 : // MHPMC3H(RW), MHPMC3(RW)
2417 : // [63:32][31:0] : Hardware Performance Monitor Counter 3
2418 : localparam MHPMC3 = 12'hB03;
2419 : localparam MHPMC3H = 12'hB83;
2420 : `ifdef RV_USER_MODE
2421 : localparam HPMC3 = 12'hC03;
2422 : localparam HPMC3H = 12'hC83;
2423 : `endif
2424 :
2425 : assign mhpmc3_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC3);
2426 : assign mhpmc3_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[0]) & (|(mhpmc_inc_r[0]));
2427 : assign mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1;
2428 : assign mhpmc3_incr[63:0] = {mhpmc3h[31:0],mhpmc3[31:0]} + {63'b0, 1'b1};
2429 : assign mhpmc3_ns[31:0] = mhpmc3_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc3_incr[31:0];
2430 : rvdffe #(32) mhpmc3_ff (.*, .clk(free_l2clk), .en(mhpmc3_wr_en), .din(mhpmc3_ns[31:0]), .dout(mhpmc3[31:0]));
2431 :
2432 : assign mhpmc3h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC3H);
2433 : assign mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1;
2434 : assign mhpmc3h_ns[31:0] = mhpmc3h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc3_incr[63:32];
2435 : rvdffe #(32) mhpmc3h_ff (.*, .clk(free_l2clk), .en(mhpmc3h_wr_en), .din(mhpmc3h_ns[31:0]), .dout(mhpmc3h[31:0]));
2436 :
2437 : // ----------------------------------------------------------------------
2438 : // MHPMC4H(RW), MHPMC4(RW)
2439 : // [63:32][31:0] : Hardware Performance Monitor Counter 4
2440 : localparam MHPMC4 = 12'hB04;
2441 : localparam MHPMC4H = 12'hB84;
2442 : `ifdef RV_USER_MODE
2443 : localparam HPMC4 = 12'hC04;
2444 : localparam HPMC4H = 12'hC84;
2445 : `endif
2446 :
2447 : assign mhpmc4_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC4);
2448 : assign mhpmc4_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[1]) & (|(mhpmc_inc_r[1]));
2449 : assign mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1;
2450 : assign mhpmc4_incr[63:0] = {mhpmc4h[31:0],mhpmc4[31:0]} + {63'b0,1'b1};
2451 : assign mhpmc4_ns[31:0] = mhpmc4_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc4_incr[31:0];
2452 : rvdffe #(32) mhpmc4_ff (.*, .clk(free_l2clk), .en(mhpmc4_wr_en), .din(mhpmc4_ns[31:0]), .dout(mhpmc4[31:0]));
2453 :
2454 : assign mhpmc4h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC4H);
2455 : assign mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1;
2456 : assign mhpmc4h_ns[31:0] = mhpmc4h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc4_incr[63:32];
2457 : rvdffe #(32) mhpmc4h_ff (.*, .clk(free_l2clk), .en(mhpmc4h_wr_en), .din(mhpmc4h_ns[31:0]), .dout(mhpmc4h[31:0]));
2458 :
2459 : // ----------------------------------------------------------------------
2460 : // MHPMC5H(RW), MHPMC5(RW)
2461 : // [63:32][31:0] : Hardware Performance Monitor Counter 5
2462 : localparam MHPMC5 = 12'hB05;
2463 : localparam MHPMC5H = 12'hB85;
2464 : `ifdef RV_USER_MODE
2465 : localparam HPMC5 = 12'hC05;
2466 : localparam HPMC5H = 12'hC85;
2467 : `endif
2468 :
2469 : assign mhpmc5_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC5);
2470 : assign mhpmc5_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[2]) & (|(mhpmc_inc_r[2]));
2471 : assign mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1;
2472 : assign mhpmc5_incr[63:0] = {mhpmc5h[31:0],mhpmc5[31:0]} + {63'b0,1'b1};
2473 : assign mhpmc5_ns[31:0] = mhpmc5_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc5_incr[31:0];
2474 : rvdffe #(32) mhpmc5_ff (.*, .clk(free_l2clk), .en(mhpmc5_wr_en), .din(mhpmc5_ns[31:0]), .dout(mhpmc5[31:0]));
2475 :
2476 : assign mhpmc5h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC5H);
2477 : assign mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1;
2478 : assign mhpmc5h_ns[31:0] = mhpmc5h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc5_incr[63:32];
2479 : rvdffe #(32) mhpmc5h_ff (.*, .clk(free_l2clk), .en(mhpmc5h_wr_en), .din(mhpmc5h_ns[31:0]), .dout(mhpmc5h[31:0]));
2480 :
2481 : // ----------------------------------------------------------------------
2482 : // MHPMC6H(RW), MHPMC6(RW)
2483 : // [63:32][31:0] : Hardware Performance Monitor Counter 6
2484 : localparam MHPMC6 = 12'hB06;
2485 : localparam MHPMC6H = 12'hB86;
2486 : `ifdef RV_USER_MODE
2487 : localparam HPMC6 = 12'hC06;
2488 : localparam HPMC6H = 12'hC86;
2489 : `endif
2490 :
2491 : assign mhpmc6_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC6);
2492 : assign mhpmc6_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep[3]) & (|(mhpmc_inc_r[3]));
2493 : assign mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1;
2494 : assign mhpmc6_incr[63:0] = {mhpmc6h[31:0],mhpmc6[31:0]} + {63'b0,1'b1};
2495 : assign mhpmc6_ns[31:0] = mhpmc6_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc6_incr[31:0];
2496 : rvdffe #(32) mhpmc6_ff (.*, .clk(free_l2clk), .en(mhpmc6_wr_en), .din(mhpmc6_ns[31:0]), .dout(mhpmc6[31:0]));
2497 :
2498 : assign mhpmc6h_wr_en0 = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPMC6H);
2499 : assign mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1;
2500 : assign mhpmc6h_ns[31:0] = mhpmc6h_wr_en0 ? dec_csr_wrdata_r[31:0] : mhpmc6_incr[63:32];
2501 : rvdffe #(32) mhpmc6h_ff (.*, .clk(free_l2clk), .en(mhpmc6h_wr_en), .din(mhpmc6h_ns[31:0]), .dout(mhpmc6h[31:0]));
2502 :
2503 : // ----------------------------------------------------------------------
2504 : // MHPME3(RW)
2505 : // [9:0] : Hardware Performance Monitor Event 3
2506 : localparam MHPME3 = 12'h323;
2507 :
2508 : // we only have events 0-56 with holes, 512-516, HPME* are WARL so zero otherwise.
2509 : assign zero_event_r = ( (dec_csr_wrdata_r[9:0] > 10'd516) |
2510 : (|dec_csr_wrdata_r[31:10]) |
2511 : ((dec_csr_wrdata_r[9:0] < 10'd512) & (dec_csr_wrdata_r[9:0] > 10'd56)) |
2512 : ((dec_csr_wrdata_r[9:0] < 10'd54) & (dec_csr_wrdata_r[9:0] > 10'd50)) |
2513 : (dec_csr_wrdata_r[9:0] == 10'd29) |
2514 : (dec_csr_wrdata_r[9:0] == 10'd33)
2515 : );
2516 :
2517 : assign event_r[9:0] = zero_event_r ? '0 : dec_csr_wrdata_r[9:0];
2518 :
2519 : assign wr_mhpme3_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME3);
2520 : rvdffe #(10) mhpme3_ff (.*, .en(wr_mhpme3_r), .din(event_r[9:0]), .dout(mhpme3[9:0]));
2521 : // ----------------------------------------------------------------------
2522 : // MHPME4(RW)
2523 : // [9:0] : Hardware Performance Monitor Event 4
2524 : localparam MHPME4 = 12'h324;
2525 :
2526 : assign wr_mhpme4_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME4);
2527 : rvdffe #(10) mhpme4_ff (.*, .en(wr_mhpme4_r), .din(event_r[9:0]), .dout(mhpme4[9:0]));
2528 : // ----------------------------------------------------------------------
2529 : // MHPME5(RW)
2530 : // [9:0] : Hardware Performance Monitor Event 5
2531 : localparam MHPME5 = 12'h325;
2532 :
2533 : assign wr_mhpme5_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME5);
2534 : rvdffe #(10) mhpme5_ff (.*, .en(wr_mhpme5_r), .din(event_r[9:0]), .dout(mhpme5[9:0]));
2535 : // ----------------------------------------------------------------------
2536 : // MHPME6(RW)
2537 : // [9:0] : Hardware Performance Monitor Event 6
2538 : localparam MHPME6 = 12'h326;
2539 :
2540 : assign wr_mhpme6_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MHPME6);
2541 : rvdffe #(10) mhpme6_ff (.*, .en(wr_mhpme6_r), .din(event_r[9:0]), .dout(mhpme6[9:0]));
2542 :
2543 : //----------------------------------------------------------------------
2544 : // Performance Monitor Counters section ends
2545 : //----------------------------------------------------------------------
2546 : // ----------------------------------------------------------------------
2547 :
2548 : // ----------------------------------------------------------------------
2549 : // MCOUNTEREN
2550 : // [31:3] : Reserved, read 0x0
2551 : // [2] : INSTRET user-mode access disable
2552 : // [1] : reserved, read 0x0
2553 : // [0] : CYCLE user-mode access disable
2554 :
2555 : `ifdef RV_USER_MODE
2556 :
2557 : localparam MCOUNTEREN = 12'h306;
2558 :
2559 : assign wr_mcounteren_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCOUNTEREN);
2560 : rvdffs #(6) mcounteren_ff (.*, .clk(csr_wr_clk), .en(wr_mcounteren_r), .din({dec_csr_wrdata_r[6:2], dec_csr_wrdata_r[0]}), .dout(mcounteren));
2561 :
2562 : `endif
2563 :
2564 : // MCOUNTINHIBIT(RW)
2565 : // [31:7] : Reserved, read 0x0
2566 : // [6] : HPM6 disable
2567 : // [5] : HPM5 disable
2568 : // [4] : HPM4 disable
2569 : // [3] : HPM3 disable
2570 : // [2] : MINSTRET disable
2571 : // [1] : reserved, read 0x0
2572 : // [0] : MCYCLE disable
2573 :
2574 : localparam MCOUNTINHIBIT = 12'h320;
2575 :
2576 : assign wr_mcountinhibit_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MCOUNTINHIBIT);
2577 : rvdffs #(6) mcountinhibit_ff (.*, .clk(csr_wr_clk), .en(wr_mcountinhibit_r), .din({dec_csr_wrdata_r[6:2], dec_csr_wrdata_r[0]}), .dout({mcountinhibit[6:2], mcountinhibit[0]}));
2578 : assign mcountinhibit[1] = 1'b0;
2579 :
2580 : //--------------------------------------------------------------------------------
2581 : // trace
2582 : //--------------------------------------------------------------------------------
2583 0 : logic [4:0] dec_tlu_exc_cause_wb1_raw, dec_tlu_exc_cause_wb2;
2584 28 : logic dec_tlu_int_valid_wb1_raw, dec_tlu_int_valid_wb2;
2585 :
2586 : assign {dec_tlu_i0_valid_wb1,
2587 : dec_tlu_i0_exc_valid_wb1,
2588 : dec_tlu_exc_cause_wb1_raw[4:0],
2589 : dec_tlu_int_valid_wb1_raw} = {8{~dec_tlu_trace_disable}} & {i0_valid_wb,
2590 : i0_exception_valid_r_d1 | lsu_i0_exc_r_d1 | (trigger_hit_r_d1 & ~trigger_hit_dmode_r_d1),
2591 : exc_cause_wb[4:0],
2592 : interrupt_valid_r_d1};
2593 :
2594 :
2595 :
2596 : // skid buffer for ints, reduces trace port count by 1
2597 : rvdffie #(.WIDTH(6), .OVERRIDE(1)) traceskidff (.*, .clk(clk),
2598 : .din ({dec_tlu_exc_cause_wb1_raw[4:0],
2599 : dec_tlu_int_valid_wb1_raw}),
2600 : .dout({dec_tlu_exc_cause_wb2[4:0],
2601 : dec_tlu_int_valid_wb2}));
2602 : //skid for ints
2603 : assign dec_tlu_exc_cause_wb1[4:0] = dec_tlu_int_valid_wb2 ? dec_tlu_exc_cause_wb2[4:0] : dec_tlu_exc_cause_wb1_raw[4:0];
2604 : assign dec_tlu_int_valid_wb1 = dec_tlu_int_valid_wb2;
2605 :
2606 : assign dec_tlu_mtval_wb1 = mtval[31:0];
2607 :
2608 : // end trace
2609 : //--------------------------------------------------------------------------------
2610 :
2611 :
2612 : // ----------------------------------------------------------------------
2613 : // CSR read mux
2614 : // ----------------------------------------------------------------------
2615 :
2616 : assign dec_tlu_presync_d = presync & dec_csr_any_unq_d & ~dec_csr_wen_unq_d;
2617 : assign dec_tlu_postsync_d = postsync & dec_csr_any_unq_d;
2618 :
2619 : // allow individual configuration of these features
2620 : assign conditionally_illegal = ((csr_mitcnt0 | csr_mitcnt1 | csr_mitb0 | csr_mitb1 | csr_mitctl0 | csr_mitctl1) & ~|pt.TIMER_LEGAL_EN);
2621 :
2622 : assign valid_csr = ( legal & (~(csr_dcsr | csr_dpc | csr_dmst | csr_dicawics | csr_dicad0 | csr_dicad0h | csr_dicad1 | csr_dicago) | dbg_tlu_halted_f)
2623 : & ~fast_int_meicpct & ~conditionally_illegal);
2624 :
2625 : assign dec_csr_legal_d = ( dec_csr_any_unq_d &
2626 : valid_csr & // of a valid CSR
2627 : ~(dec_csr_wen_unq_d & (csr_mvendorid | csr_marchid | csr_mimpid | csr_mhartid | csr_mdseac | csr_meihap)) // that's not a write to a RO CSR
2628 : );
2629 : // CSR read mux
2630 : assign dec_csr_rddata_d[31:0] = (
2631 : `ifdef RV_USER_MODE
2632 : ({32{csr_misa}} & 32'h40101104) |
2633 : `else
2634 : ({32{csr_misa}} & 32'h40001104) |
2635 : `endif
2636 : ({32{csr_mvendorid}} & 32'h00000045) |
2637 : ({32{csr_marchid}} & 32'h00000010) |
2638 : ({32{csr_mimpid}} & 32'h4) |
2639 : ({32{csr_mhartid}} & {core_id[31:4], 4'b0}) |
2640 : `ifdef RV_USER_MODE
2641 : ({32{csr_mstatus}} & {14'b0, mstatus[MSTATUS_MPRV], 4'b0, ~mstatus[MSTATUS_MPP], ~mstatus[MSTATUS_MPP], 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0}) |
2642 : `else
2643 : ({32{csr_mstatus}} & {19'b0, 2'b11, 3'b0, mstatus[MSTATUS_MPIE], 3'b0, mstatus[MSTATUS_MIE], 3'b0}) |
2644 : `endif
2645 : ({32{csr_mtvec}} & {mtvec[30:1], 1'b0, mtvec[0]}) |
2646 : ({32{csr_mip}} & {1'b0, mip[5:3], 16'b0, mip[2], 3'b0, mip[1], 3'b0, mip[0], 3'b0}) |
2647 : ({32{csr_mie}} & {1'b0, mie[5:3], 16'b0, mie[2], 3'b0, mie[1], 3'b0, mie[0], 3'b0}) |
2648 : ({32{csr_mcyclel}} & mcyclel[31:0]) |
2649 : ({32{csr_mcycleh}} & mcycleh_inc[31:0]) |
2650 : ({32{csr_minstretl}} & minstretl_read[31:0]) |
2651 : ({32{csr_minstreth}} & minstreth_read[31:0]) |
2652 : ({32{csr_mscratch}} & mscratch[31:0]) |
2653 : ({32{csr_mepc}} & {mepc[31:1], 1'b0}) |
2654 : ({32{csr_mcause}} & mcause[31:0]) |
2655 : ({32{csr_mscause}} & {28'b0, mscause[3:0]}) |
2656 : ({32{csr_mtval}} & mtval[31:0]) |
2657 : ({32{csr_mrac}} & mrac[31:0]) |
2658 : ({32{csr_mdseac}} & mdseac[31:0]) |
2659 : ({32{csr_meivt}} & {meivt[31:10], 10'b0}) |
2660 : ({32{csr_meihap}} & {meivt[31:10], meihap[9:2], 2'b0}) |
2661 : ({32{csr_meicurpl}} & {28'b0, meicurpl[3:0]}) |
2662 : ({32{csr_meicidpl}} & {28'b0, meicidpl[3:0]}) |
2663 : ({32{csr_meipt}} & {28'b0, meipt[3:0]}) |
2664 : ({32{csr_mcgc}} & {22'b0, mcgc[9:0]}) |
2665 : ({32{csr_mfdc}} & {13'b0, mfdc[18:0]}) |
2666 : ({32{csr_dcsr}} & {16'h4000, dcsr[15:2], 2'b11}) |
2667 : ({32{csr_dpc}} & {dpc[31:1], 1'b0}) |
2668 : ({32{csr_dicad0}} & dicad0[31:0]) |
2669 : ({32{csr_dicad0h}} & dicad0h[31:0]) |
2670 : ({32{csr_dicad1}} & dicad1[31:0]) |
2671 : ({32{csr_dicawics}} & {7'b0, dicawics[16], 2'b0, dicawics[15:14], 3'b0, dicawics[13:0], 3'b0}) |
2672 : ({32{csr_mtsel}} & {30'b0, mtsel[1:0]}) |
2673 : ({32{csr_mtdata1}} & {mtdata1_tsel_out[31:0]}) |
2674 : ({32{csr_mtdata2}} & {mtdata2_tsel_out[31:0]}) |
2675 : ({32{csr_micect}} & {micect[31:0]}) |
2676 : ({32{csr_miccmect}} & {miccmect[31:0]}) |
2677 : ({32{csr_mdccmect}} & {mdccmect[31:0]}) |
2678 : ({32{csr_mhpmc3}} & mhpmc3[31:0]) |
2679 : ({32{csr_mhpmc4}} & mhpmc4[31:0]) |
2680 : ({32{csr_mhpmc5}} & mhpmc5[31:0]) |
2681 : ({32{csr_mhpmc6}} & mhpmc6[31:0]) |
2682 : ({32{csr_mhpmc3h}} & mhpmc3h[31:0]) |
2683 : ({32{csr_mhpmc4h}} & mhpmc4h[31:0]) |
2684 : ({32{csr_mhpmc5h}} & mhpmc5h[31:0]) |
2685 : ({32{csr_mhpmc6h}} & mhpmc6h[31:0]) |
2686 : ({32{csr_mfdht}} & {26'b0, mfdht[5:0]}) |
2687 : ({32{csr_mfdhs}} & {30'b0, mfdhs[1:0]}) |
2688 : ({32{csr_mhpme3}} & {22'b0,mhpme3[9:0]}) |
2689 : ({32{csr_mhpme4}} & {22'b0,mhpme4[9:0]}) |
2690 : ({32{csr_mhpme5}} & {22'b0,mhpme5[9:0]}) |
2691 : ({32{csr_mhpme6}} & {22'b0,mhpme6[9:0]}) |
2692 : `ifdef RV_USER_MODE
2693 : ({32{csr_menvcfg}} & 32'd0) |
2694 : ({32{csr_menvcfgh}} & 32'd0) |
2695 : ({32{csr_mcounteren}} & {25'b0, mcounteren[5:1], 1'b0, mcounteren[0]}) |
2696 : ({32{csr_cyclel}} & mcyclel[31:0]) |
2697 : ({32{csr_cycleh}} & mcycleh_inc[31:0]) |
2698 : ({32{csr_instretl}} & minstretl_read[31:0]) |
2699 : ({32{csr_instreth}} & minstreth_read[31:0]) |
2700 : ({32{csr_hpmc3}} & mhpmc3[31:0]) |
2701 : ({32{csr_hpmc4}} & mhpmc4[31:0]) |
2702 : ({32{csr_hpmc5}} & mhpmc5[31:0]) |
2703 : ({32{csr_hpmc6}} & mhpmc6[31:0]) |
2704 : ({32{csr_hpmc3h}} & mhpmc3h[31:0]) |
2705 : ({32{csr_hpmc4h}} & mhpmc4h[31:0]) |
2706 : ({32{csr_hpmc5h}} & mhpmc5h[31:0]) |
2707 : ({32{csr_hpmc6h}} & mhpmc6h[31:0]) |
2708 : ({32{csr_mseccfgl}} & {29'd0, mseccfg}) |
2709 : ({32{csr_mseccfgh}} & 32'd0) | // All bits are WPRI
2710 : `endif
2711 : ({32{csr_mcountinhibit}} & {25'b0, mcountinhibit[6:0]}) |
2712 : ({32{csr_mpmc}} & {30'b0, mpmc[1], 1'b0}) |
2713 : ({32{dec_timer_read_d}} & dec_timer_rddata_d[31:0]) |
2714 : ({32{dec_pmp_read_d}} & dec_pmp_rddata_d[31:0])
2715 : );
2716 :
2717 :
2718 :
2719 : endmodule // el2_dec_tlu_ctl
2720 :
2721 : module el2_dec_timer_ctl
2722 : import el2_pkg::*;
2723 : #(
2724 : `include "el2_param.vh"
2725 : )
2726 : (
2727 61843746 : input logic clk,
2728 61843746 : input logic free_l2clk,
2729 61843746 : input logic csr_wr_clk,
2730 316 : input logic rst_l,
2731 41826 : input logic dec_csr_wen_r_mod, // csr write enable at wb
2732 406 : input logic [11:0] dec_csr_wraddr_r, // write address for csr
2733 1640 : input logic [31:0] dec_csr_wrdata_r, // csr write data at wb
2734 :
2735 12 : input logic csr_mitctl0,
2736 12 : input logic csr_mitctl1,
2737 14 : input logic csr_mitb0,
2738 12 : input logic csr_mitb1,
2739 8 : input logic csr_mitcnt0,
2740 16 : input logic csr_mitcnt1,
2741 :
2742 :
2743 0 : input logic dec_pause_state, // Paused
2744 0 : input logic dec_tlu_pmu_fw_halted, // pmu/fw halted
2745 0 : input logic internal_dbg_halt_timers, // debug halted
2746 :
2747 26 : output logic [31:0] dec_timer_rddata_d, // timer CSR read data
2748 74 : output logic dec_timer_read_d, // timer CSR address match
2749 0 : output logic dec_timer_t0_pulse, // timer0 int
2750 0 : output logic dec_timer_t1_pulse, // timer1 int
2751 :
2752 0 : input logic scan_mode
2753 : );
2754 : localparam MITCTL_ENABLE = 0;
2755 : localparam MITCTL_ENABLE_HALTED = 1;
2756 : localparam MITCTL_ENABLE_PAUSED = 2;
2757 :
2758 47083 : logic [31:0] mitcnt0_ns, mitcnt0, mitcnt1_ns, mitcnt1, mitb0, mitb1, mitb0_b, mitb1_b, mitcnt0_inc, mitcnt1_inc;
2759 0 : logic [2:0] mitctl0_ns, mitctl0;
2760 0 : logic [3:0] mitctl1_ns, mitctl1;
2761 0 : logic wr_mitcnt0_r, wr_mitcnt1_r, wr_mitb0_r, wr_mitb1_r, wr_mitctl0_r, wr_mitctl1_r;
2762 317 : logic mitcnt0_inc_ok, mitcnt1_inc_ok;
2763 188615 : logic mitcnt0_inc_cout, mitcnt1_inc_cout;
2764 0 : logic mit0_match_ns;
2765 0 : logic mit1_match_ns;
2766 0 : logic mitctl0_0_b_ns;
2767 0 : logic mitctl0_0_b;
2768 0 : logic mitctl1_0_b_ns;
2769 0 : logic mitctl1_0_b;
2770 :
2771 : assign mit0_match_ns = (mitcnt0[31:0] >= mitb0[31:0]);
2772 : assign mit1_match_ns = (mitcnt1[31:0] >= mitb1[31:0]);
2773 :
2774 : assign dec_timer_t0_pulse = mit0_match_ns;
2775 : assign dec_timer_t1_pulse = mit1_match_ns;
2776 : // ----------------------------------------------------------------------
2777 : // MITCNT0 (RW)
2778 : // [31:0] : Internal Timer Counter 0
2779 :
2780 : localparam MITCNT0 = 12'h7d2;
2781 :
2782 : assign wr_mitcnt0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCNT0);
2783 :
2784 : assign mitcnt0_inc_ok = mitctl0[MITCTL_ENABLE] & (~dec_pause_state | mitctl0[MITCTL_ENABLE_PAUSED]) & (~dec_tlu_pmu_fw_halted | mitctl0[MITCTL_ENABLE_HALTED]) & ~internal_dbg_halt_timers;
2785 :
2786 : assign {mitcnt0_inc_cout, mitcnt0_inc[7:0]} = mitcnt0[7:0] + {7'b0, 1'b1};
2787 : assign mitcnt0_inc[31:8] = mitcnt0[31:8] + {23'b0, mitcnt0_inc_cout};
2788 :
2789 : assign mitcnt0_ns[31:0] = wr_mitcnt0_r ? dec_csr_wrdata_r[31:0] : mit0_match_ns ? 'b0 : mitcnt0_inc[31:0];
2790 :
2791 : rvdffe #(24) mitcnt0_ffb (.*, .clk(free_l2clk), .en(wr_mitcnt0_r | (mitcnt0_inc_ok & mitcnt0_inc_cout) | mit0_match_ns), .din(mitcnt0_ns[31:8]), .dout(mitcnt0[31:8]));
2792 : rvdffe #(8) mitcnt0_ffa (.*, .clk(free_l2clk), .en(wr_mitcnt0_r | mitcnt0_inc_ok | mit0_match_ns), .din(mitcnt0_ns[7:0]), .dout(mitcnt0[7:0]));
2793 :
2794 : // ----------------------------------------------------------------------
2795 : // MITCNT1 (RW)
2796 : // [31:0] : Internal Timer Counter 0
2797 :
2798 : localparam MITCNT1 = 12'h7d5;
2799 :
2800 : assign wr_mitcnt1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCNT1);
2801 :
2802 : assign mitcnt1_inc_ok = mitctl1[MITCTL_ENABLE] &
2803 : (~dec_pause_state | mitctl1[MITCTL_ENABLE_PAUSED]) &
2804 : (~dec_tlu_pmu_fw_halted | mitctl1[MITCTL_ENABLE_HALTED]) &
2805 : ~internal_dbg_halt_timers &
2806 : (~mitctl1[3] | mit0_match_ns);
2807 :
2808 : // only inc MITCNT1 if not cascaded with 0, or if 0 overflows
2809 : assign {mitcnt1_inc_cout, mitcnt1_inc[7:0]} = mitcnt1[7:0] + {7'b0, 1'b1};
2810 : assign mitcnt1_inc[31:8] = mitcnt1[31:8] + {23'b0, mitcnt1_inc_cout};
2811 :
2812 : assign mitcnt1_ns[31:0] = wr_mitcnt1_r ? dec_csr_wrdata_r[31:0] : mit1_match_ns ? 'b0 : mitcnt1_inc[31:0];
2813 :
2814 : rvdffe #(24) mitcnt1_ffb (.*, .clk(free_l2clk), .en(wr_mitcnt1_r | (mitcnt1_inc_ok & mitcnt1_inc_cout) | mit1_match_ns), .din(mitcnt1_ns[31:8]), .dout(mitcnt1[31:8]));
2815 : rvdffe #(8) mitcnt1_ffa (.*, .clk(free_l2clk), .en(wr_mitcnt1_r | mitcnt1_inc_ok | mit1_match_ns), .din(mitcnt1_ns[7:0]), .dout(mitcnt1[7:0]));
2816 :
2817 :
2818 : // ----------------------------------------------------------------------
2819 : // MITB0 (RW)
2820 : // [31:0] : Internal Timer Bound 0
2821 :
2822 : localparam MITB0 = 12'h7d3;
2823 :
2824 : assign wr_mitb0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITB0);
2825 :
2826 : rvdffe #(32) mitb0_ff (.*, .en(wr_mitb0_r), .din(~dec_csr_wrdata_r[31:0]), .dout(mitb0_b[31:0]));
2827 : assign mitb0[31:0] = ~mitb0_b[31:0];
2828 :
2829 : // ----------------------------------------------------------------------
2830 : // MITB1 (RW)
2831 : // [31:0] : Internal Timer Bound 1
2832 :
2833 : localparam MITB1 = 12'h7d6;
2834 :
2835 : assign wr_mitb1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITB1);
2836 :
2837 : rvdffe #(32) mitb1_ff (.*, .en(wr_mitb1_r), .din(~dec_csr_wrdata_r[31:0]), .dout(mitb1_b[31:0]));
2838 : assign mitb1[31:0] = ~mitb1_b[31:0];
2839 :
2840 : // ----------------------------------------------------------------------
2841 : // MITCTL0 (RW) Internal Timer Ctl 0
2842 : // [31:3] : Reserved, reads 0x0
2843 : // [2] : Enable while PAUSEd
2844 : // [1] : Enable while HALTed
2845 : // [0] : Enable (resets to 0x1)
2846 :
2847 : localparam MITCTL0 = 12'h7d4;
2848 :
2849 : assign wr_mitctl0_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCTL0);
2850 : assign mitctl0_ns[2:0] = wr_mitctl0_r ? {dec_csr_wrdata_r[2:0]} : {mitctl0[2:0]};
2851 :
2852 : assign mitctl0_0_b_ns = ~mitctl0_ns[0];
2853 : rvdffs #(3) mitctl0_ff (.*, .clk(csr_wr_clk), .en(wr_mitctl0_r), .din({mitctl0_ns[2:1], mitctl0_0_b_ns}), .dout({mitctl0[2:1], mitctl0_0_b}));
2854 : assign mitctl0[0] = ~mitctl0_0_b;
2855 :
2856 : // ----------------------------------------------------------------------
2857 : // MITCTL1 (RW) Internal Timer Ctl 1
2858 : // [31:4] : Reserved, reads 0x0
2859 : // [3] : Cascade
2860 : // [2] : Enable while PAUSEd
2861 : // [1] : Enable while HALTed
2862 : // [0] : Enable (resets to 0x1)
2863 :
2864 : localparam MITCTL1 = 12'h7d7;
2865 :
2866 : assign wr_mitctl1_r = dec_csr_wen_r_mod & (dec_csr_wraddr_r[11:0] == MITCTL1);
2867 : assign mitctl1_ns[3:0] = wr_mitctl1_r ? {dec_csr_wrdata_r[3:0]} : {mitctl1[3:0]};
2868 :
2869 : assign mitctl1_0_b_ns = ~mitctl1_ns[0];
2870 : rvdffs #(4) mitctl1_ff (.*, .clk(csr_wr_clk), .en(wr_mitctl1_r), .din({mitctl1_ns[3:1], mitctl1_0_b_ns}), .dout({mitctl1[3:1], mitctl1_0_b}));
2871 : assign mitctl1[0] = ~mitctl1_0_b;
2872 : assign dec_timer_read_d = csr_mitcnt1 | csr_mitcnt0 | csr_mitb1 | csr_mitb0 | csr_mitctl0 | csr_mitctl1;
2873 : assign dec_timer_rddata_d[31:0] = ( ({32{csr_mitcnt0}} & mitcnt0[31:0]) |
2874 : ({32{csr_mitcnt1}} & mitcnt1[31:0]) |
2875 : ({32{csr_mitb0}} & mitb0[31:0]) |
2876 : ({32{csr_mitb1}} & mitb1[31:0]) |
2877 : ({32{csr_mitctl0}} & {29'b0, mitctl0[2:0]}) |
2878 : ({32{csr_mitctl1}} & {28'b0, mitctl1[3:0]})
2879 : );
2880 :
2881 :
2882 : endmodule // dec_timer_ctl
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