Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 : module el2_dec_ib_ctl
17 : import el2_pkg::*;
18 : #(
19 : `include "el2_param.vh"
20 : )
21 : (
22 2309 : input logic dbg_cmd_valid, // valid dbg cmd
23 :
24 773 : input logic dbg_cmd_write, // dbg cmd is write
25 1454 : input logic [1:0] dbg_cmd_type, // dbg type
26 353 : input logic [31:0] dbg_cmd_addr, // expand to 31:0
27 :
28 206674 : input el2_br_pkt_t i0_brp, // i0 branch packet from aligner
29 651206 : input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index, // BP index
30 631071 : input logic [pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr, // BP FGHR
31 21223 : input logic [pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag, // BP tag
32 0 : input logic [$clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index, // Fully associt btb index
33 :
34 5774060 : input logic ifu_i0_pc4, // i0 is 4B inst else 2B
35 6018075 : input logic ifu_i0_valid, // i0 valid from ifu
36 208 : input logic ifu_i0_icaf, // i0 instruction access fault
37 274 : input logic [1:0] ifu_i0_icaf_type, // i0 instruction access fault type
38 :
39 86 : input logic ifu_i0_icaf_second, // i0 has access fault on second 2B of 4B inst
40 2 : input logic ifu_i0_dbecc, // i0 double-bit error
41 469288 : input logic [31:0] ifu_i0_instr, // i0 instruction from the aligner
42 1322 : input logic [31:1] ifu_i0_pc, // i0 pc from the aligner
43 :
44 :
45 6020380 : output logic dec_ib0_valid_d, // ib0 valid
46 2305 : output logic dec_debug_valid_d, // Debug read or write at D-stage
47 :
48 :
49 468827 : output logic [31:0] dec_i0_instr_d, // i0 inst at decode
50 :
51 1322 : output logic [31:1] dec_i0_pc_d, // i0 pc at decode
52 :
53 5774060 : output logic dec_i0_pc4_d, // i0 is 4B inst else 2B
54 :
55 206674 : output el2_br_pkt_t dec_i0_brp, // i0 branch packet at decode
56 651206 : output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index, // i0 branch index
57 631071 : output logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr, // BP FGHR
58 21223 : output logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
59 0 : output logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index, // Fully associt btb index
60 :
61 208 : output logic dec_i0_icaf_d, // i0 instruction access fault at decode
62 86 : output logic dec_i0_icaf_second_d, // i0 instruction access fault on second 2B of 4B inst
63 274 : output logic [1:0] dec_i0_icaf_type_d, // i0 instruction access fault type
64 2 : output logic dec_i0_dbecc_d, // i0 double-bit error at decode
65 559 : output logic dec_debug_wdata_rs1_d, // put debug write data onto rs1 source: machine is halted
66 :
67 0 : output logic dec_debug_fence_d // debug fence inst
68 :
69 : );
70 :
71 :
72 2305 : logic debug_valid;
73 846 : logic [4:0] dreg;
74 353 : logic [11:0] dcsr;
75 1 : logic [31:0] ib0, ib0_debug_in;
76 :
77 2752 : logic debug_read;
78 559 : logic debug_write;
79 608 : logic debug_read_gpr;
80 390 : logic debug_write_gpr;
81 2374 : logic debug_read_csr;
82 427 : logic debug_write_csr;
83 :
84 604274 : logic [34:0] ifu_i0_pcdata, pc0;
85 :
86 : assign ifu_i0_pcdata[34:0] = { ifu_i0_icaf_second, ifu_i0_dbecc, ifu_i0_icaf,
87 : ifu_i0_pc[31:1], ifu_i0_pc4 };
88 :
89 : assign pc0[34:0] = ifu_i0_pcdata[34:0];
90 :
91 : assign dec_i0_icaf_second_d = pc0[34]; // icaf's can only decode as i0
92 :
93 : assign dec_i0_dbecc_d = pc0[33];
94 :
95 : assign dec_i0_icaf_d = pc0[32];
96 : assign dec_i0_pc_d[31:1] = pc0[31:1];
97 : assign dec_i0_pc4_d = pc0[0];
98 :
99 : assign dec_i0_icaf_type_d[1:0] = ifu_i0_icaf_type[1:0];
100 :
101 : // GPR accesses
102 :
103 : // put reg to read on rs1
104 : // read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011}
105 :
106 : // put write date on rs1
107 : // write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011}
108 :
109 :
110 : // CSR accesses
111 : // csr is of form rd, csr, rs1
112 :
113 : // read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011}
114 :
115 : // put write data on rs1
116 : // write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011}
117 :
118 : // abstract memory command not done here
119 : assign debug_valid = dbg_cmd_valid & (dbg_cmd_type[1:0] != 2'h2);
120 :
121 :
122 : assign debug_read = debug_valid & ~dbg_cmd_write;
123 : assign debug_write = debug_valid & dbg_cmd_write;
124 :
125 : assign debug_read_gpr = debug_read & (dbg_cmd_type[1:0]==2'h0);
126 : assign debug_write_gpr = debug_write & (dbg_cmd_type[1:0]==2'h0);
127 : assign debug_read_csr = debug_read & (dbg_cmd_type[1:0]==2'h1);
128 : assign debug_write_csr = debug_write & (dbg_cmd_type[1:0]==2'h1);
129 :
130 : assign dreg[4:0] = dbg_cmd_addr[4:0];
131 : assign dcsr[11:0] = dbg_cmd_addr[11:0];
132 :
133 :
134 : assign ib0_debug_in[31:0] = ({32{debug_read_gpr}} & {12'b000000000000,dreg[4:0],15'b110000000110011}) |
135 : ({32{debug_write_gpr}} & {20'b00000000000000000110,dreg[4:0],7'b0110011}) |
136 : ({32{debug_read_csr}} & {dcsr[11:0],20'b00000010000001110011}) |
137 : ({32{debug_write_csr}} & {dcsr[11:0],20'b00000001000001110011});
138 :
139 :
140 :
141 : // machine is in halted state, pipe empty, write will always happen next cycle
142 :
143 : assign dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr;
144 :
145 :
146 : // special fence csr for use only in debug mode
147 :
148 : assign dec_debug_fence_d = debug_write_csr & (dcsr[11:0] == 12'h7c4);
149 :
150 : assign ib0[31:0] = (debug_valid) ? ib0_debug_in[31:0] : ifu_i0_instr[31:0];
151 :
152 : assign dec_ib0_valid_d = ifu_i0_valid | debug_valid;
153 :
154 : assign dec_debug_valid_d = debug_valid;
155 :
156 : assign dec_i0_instr_d[31:0] = ib0[31:0];
157 :
158 : assign dec_i0_brp = i0_brp;
159 : assign dec_i0_bp_index = ifu_i0_bp_index;
160 : assign dec_i0_bp_fghr = ifu_i0_bp_fghr;
161 : assign dec_i0_bp_btag = ifu_i0_bp_btag;
162 : assign dec_i0_bp_fa_index = ifu_i0_fa_index;
163 :
164 : endmodule
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