Line data    Source code

       1              : // SPDX-License-Identifier: Apache-2.0
       2              : // Copyright 2020 Western Digital Corporation or its affiliates.
       3              : //
       4              : // Licensed under the Apache License, Version 2.0 (the "License");
       5              : // you may not use this file except in compliance with the License.
       6              : // You may obtain a copy of the License at
       7              : //
       8              : // http://www.apache.org/licenses/LICENSE-2.0
       9              : //
      10              : // Unless required by applicable law or agreed to in writing, software
      11              : // distributed under the License is distributed on an "AS IS" BASIS,
      12              : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      13              : // See the License for the specific language governing permissions and
      14              : // limitations under the License.
      15              : 
      16              : module el2_dec_gpr_ctl
      17              : import el2_pkg::*;
      18              : #(
      19              :    `include "el2_param.vh"
      20              :  )  (
      21      2497511 :     input logic [4:0]  raddr0,       // logical read addresses
      22      4174324 :     input logic [4:0]  raddr1,
      23              : 
      24      5678794 :     input logic        wen0,         // write enable
      25      2809689 :     input logic [4:0]  waddr0,       // write address
      26       314049 :     input logic [31:0] wd0,          // write data
      27              : 
      28       920884 :     input logic        wen1,         // write enable
      29       368914 :     input logic [4:0]  waddr1,       // write address
      30        71560 :     input logic [31:0] wd1,          // write data
      31              : 
      32       156868 :     input logic        wen2,         // write enable
      33        21351 :     input logic [4:0]  waddr2,       // write address
      34        24784 :     input logic [31:0] wd2,          // write data
      35              : 
      36     61843746 :     input logic        clk,
      37          316 :     input logic        rst_l,
      38              : 
      39       407880 :     output logic [31:0] rd0,         // read data
      40       598740 :     output logic [31:0] rd1,
      41              : 
      42            0 :     input  logic        scan_mode
      43              : );
      44              : 
      45              :    logic [31:1] [31:0] gpr_out;      // 31 x 32 bit GPRs
      46              :    logic [31:1] [31:0] gpr_in;
      47         1324 :    logic [31:1] w0v,w1v,w2v;
      48        63550 :    logic [31:1] gpr_wr_en;
      49              : 
      50              :    // GPR Write Enables
      51              :    assign gpr_wr_en[31:1] = (w0v[31:1] | w1v[31:1] | w2v[31:1]);
      52              :    for ( genvar j=1; j<32; j++ )  begin : gpr
      53              :       rvdffe #(32) gprff (.*, .en(gpr_wr_en[j]), .din(gpr_in[j][31:0]), .dout(gpr_out[j][31:0]));
      54              :    end : gpr
      55              : 
      56              :    // the read out
      57          317 :    always_comb begin
      58          317 :       rd0[31:0] = 32'b0;
      59          317 :       rd1[31:0] = 32'b0;
      60          317 :       w0v[31:1] = 31'b0;
      61          317 :       w1v[31:1] = 31'b0;
      62          317 :       w2v[31:1] = 31'b0;
      63          317 :       gpr_in[31:1] = '0;
      64              : 
      65              :       // GPR Read logic
      66          317 :       for (int j=1; j<32; j++ )  begin
      67         9827 :          rd0[31:0] |= ({32{(raddr0[4:0]== 5'(j))}} & gpr_out[j][31:0]);
      68         9827 :          rd1[31:0] |= ({32{(raddr1[4:0]== 5'(j))}} & gpr_out[j][31:0]);
      69              :       end
      70              : 
      71              :      // GPR Write logic
      72          317 :      for (int j=1; j<32; j++ )  begin
      73         9827 :          w0v[j]     = wen0  & (waddr0[4:0]== 5'(j) );
      74         9827 :          w1v[j]     = wen1  & (waddr1[4:0]== 5'(j) );
      75         9827 :          w2v[j]     = wen2  & (waddr2[4:0]== 5'(j) );
      76         9827 :          gpr_in[j]  =    ({32{w0v[j]}} & wd0[31:0]) |
      77         9827 :                          ({32{w1v[j]}} & wd1[31:0]) |
      78         9827 :                          ({32{w2v[j]}} & wd2[31:0]);
      79              :      end
      80              :    end // always_comb begin
      81              : 
      82              : `ifdef RV_ASSERT_ON
      83              : 
      84              :    logic  write_collision_unused;
      85              :    assign write_collision_unused = ( (w0v[31:1] == w1v[31:1]) & wen0 & wen1 ) |
      86              :                                    ( (w0v[31:1] == w2v[31:1]) & wen0 & wen2 ) |
      87              :                                    ( (w1v[31:1] == w2v[31:1]) & wen1 & wen2 );
      88              : 
      89              : 
      90              :    // asserting that no 2 ports will write to the same gpr simultaneously
      91              :    assert_multiple_wen_to_same_gpr: assert #0 (~( write_collision_unused ) );
      92              : 
      93              : `endif
      94              : 
      95              : endmodule