Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 :
17 : module el2_dec_decode_ctl
18 : import el2_pkg::*;
19 : #(
20 : `include "el2_param.vh"
21 : )
22 : (
23 0 : input logic dec_tlu_trace_disable,
24 0 : input logic dec_debug_valid_d,
25 :
26 0 : input logic dec_tlu_flush_extint, // Flush external interrupt
27 :
28 0 : input logic dec_tlu_force_halt, // invalidate nonblock load cam on a force halt event
29 :
30 0 : output logic dec_extint_stall, // Stall from external interrupt
31 :
32 1427542 : input logic [15:0] ifu_i0_cinst, // 16b compressed instruction
33 579528 : output logic [31:0] dec_i0_inst_wb, // 32b instruction at wb+1 for trace encoder
34 308 : output logic [31:1] dec_i0_pc_wb, // 31b pc at wb+1 for trace encoder
35 :
36 :
37 881640 : input logic lsu_nonblock_load_valid_m, // valid nonblock load at m
38 504869 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // -> corresponding tag
39 0 : input logic lsu_nonblock_load_inv_r, // invalidate request for nonblock load r
40 504866 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag
41 920896 : input logic lsu_nonblock_load_data_valid, // valid nonblock load data back
42 0 : input logic lsu_nonblock_load_data_error, // nonblock load bus error
43 36662 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag
44 :
45 :
46 0 : input logic [3:0] dec_i0_trigger_match_d, // i0 decode trigger matches
47 :
48 0 : input logic dec_tlu_wr_pause_r, // pause instruction at r
49 0 : input logic dec_tlu_pipelining_disable, // pipeline disable - presync, i0 decode only
50 :
51 0 : input logic [3:0] lsu_trigger_match_m, // lsu trigger matches
52 :
53 48786 : input logic lsu_pmu_misaligned_m, // perf mon: load/store misalign
54 0 : input logic dec_tlu_debug_stall, // debug stall decode
55 0 : input logic dec_tlu_flush_leak_one_r, // leak1 instruction
56 :
57 0 : input logic dec_debug_fence_d, // debug fence instruction
58 :
59 0 : input logic [1:0] dbg_cmd_wrdata, // disambiguate fence, fence_i
60 :
61 196 : input logic dec_i0_icaf_d, // icache access fault
62 86 : input logic dec_i0_icaf_second_d, // i0 instruction access fault on second 2B of 4B inst
63 270 : input logic [1:0] dec_i0_icaf_type_d, // i0 instruction access fault type
64 :
65 2 : input logic dec_i0_dbecc_d, // icache/iccm double-bit error
66 :
67 200759 : input el2_br_pkt_t dec_i0_brp, // branch packet
68 651076 : input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index, // i0 branch index
69 631672 : input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr, // BP FGHR
70 21217 : input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
71 0 : input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index, // Fully associt btb index
72 :
73 1346967 : input logic lsu_idle_any, // lsu idle: if fence instr & ~lsu_idle then stall decode
74 :
75 49050 : input logic lsu_load_stall_any, // stall any load at decode
76 59374 : input logic lsu_store_stall_any, // stall any store at decode
77 0 : input logic dma_dccm_stall_any, // stall any load/store at decode
78 :
79 156868 : input logic exu_div_wren, // nonblocking divide write enable to GPR.
80 :
81 29654 : input logic dec_tlu_i0_kill_writeb_wb, // I0 is flushed, don't writeback any results to arch state
82 58638 : input logic dec_tlu_flush_lower_wb, // trap lower flush
83 29654 : input logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state
84 58638 : input logic dec_tlu_flush_lower_r, // trap lower flush
85 0 : input logic dec_tlu_flush_pause_r, // don't clear pause state on initial lower flush
86 510 : input logic dec_tlu_presync_d, // CSR read needs to be presync'd
87 20293 : input logic dec_tlu_postsync_d, // CSR ops that need to be postsync'd
88 :
89 5735369 : input logic dec_i0_pc4_d, // inst is 4B inst else 2B
90 :
91 6941 : input logic [31:0] dec_csr_rddata_d, // csr read data at wb
92 83741 : input logic dec_csr_legal_d, // csr indicates legal operation
93 :
94 3978 : input logic [31:0] exu_csr_rs1_x, // rs1 for csr instr
95 :
96 38395 : input logic [31:0] lsu_result_m, // load result
97 29134 : input logic [31:0] lsu_result_corr_r, // load result - corrected data for writing gpr's, not for bypassing
98 :
99 672565 : input logic exu_flush_final, // lower flush or i0 flush at X or D
100 :
101 308 : input logic [31:1] exu_i0_pc_x, // pcs at e1
102 :
103 468420 : input logic [31:0] dec_i0_instr_d, // inst at decode
104 :
105 6006883 : input logic dec_ib0_valid_d, // inst valid at decode
106 :
107 614701 : input logic [31:0] exu_i0_result_x, // from primary alu's
108 :
109 61843746 : input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
110 61843746 : input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
111 61843746 : input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.
112 :
113 0 : input logic clk_override, // Override non-functional clock gating
114 316 : input logic rst_l, // Flop reset
115 :
116 :
117 :
118 5130925 : output logic dec_i0_rs1_en_d, // rs1 enable at decode
119 3565563 : output logic dec_i0_rs2_en_d, // rs2 enable at decode
120 :
121 2497511 : output logic [4:0] dec_i0_rs1_d, // rs1 logical source
122 4174324 : output logic [4:0] dec_i0_rs2_d, // rs2 logical source
123 :
124 2134567 : output logic [31:0] dec_i0_immed_d, // 32b immediate data decode
125 :
126 :
127 123446 : output logic [12:1] dec_i0_br_immed_d, // 12b branch immediate
128 :
129 1460 : output el2_alu_pkt_t i0_ap, // alu packets
130 :
131 6190087 : output logic dec_i0_decode_d, // i0 decode
132 :
133 5393904 : output logic dec_i0_alu_decode_d, // decode to D-stage alu
134 3841554 : output logic dec_i0_branch_d, // Branch in D-stage
135 :
136 2809689 : output logic [4:0] dec_i0_waddr_r, // i0 logical source to write to gpr's
137 5678794 : output logic dec_i0_wen_r, // i0 write enable
138 314049 : output logic [31:0] dec_i0_wdata_r, // i0 write data
139 :
140 554879 : output logic dec_i0_select_pc_d, // i0 select pc for rs1 - branches
141 :
142 80872 : output logic [3:0] dec_i0_rs1_bypass_en_d, // i0 rs1 bypass enable
143 8634 : output logic [3:0] dec_i0_rs2_bypass_en_d, // i0 rs2 bypass enable
144 314049 : output logic [31:0] dec_i0_result_r, // Result R-stage
145 :
146 623945 : output el2_lsu_pkt_t lsu_p, // load/store packet
147 5476447 : output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands
148 :
149 0 : output el2_mul_pkt_t mul_p, // multiply packet
150 :
151 78138 : output el2_div_pkt_t div_p, // divide packet
152 21351 : output logic [4:0] div_waddr_wb, // DIV write address to GPR
153 2628 : output logic dec_div_cancel, // cancel the divide operation
154 :
155 2276073 : output logic dec_lsu_valid_raw_d,
156 270518 : output logic [11:0] dec_lsu_offset_d,
157 :
158 75092 : output logic dec_csr_ren_d, // valid csr decode
159 41991 : output logic dec_csr_wen_unq_d, // valid csr with write - for csr legal
160 83863 : output logic dec_csr_any_unq_d, // valid csr - for csr legal
161 906 : output logic [11:0] dec_csr_rdaddr_d, // read address for csr
162 41826 : output logic dec_csr_wen_r, // csr write enable at r
163 1559962 : output logic [11:0] dec_csr_rdaddr_r, // read address for csr
164 406 : output logic [11:0] dec_csr_wraddr_r, // write address for csr
165 1640 : output logic [31:0] dec_csr_wrdata_r, // csr write data at r
166 1346 : output logic dec_csr_stall_int_ff, // csr is mie/mstatus
167 :
168 6189442 : output dec_tlu_i0_valid_r, // i0 valid inst at c
169 :
170 264 : output el2_trap_pkt_t dec_tlu_packet_r, // trap packet
171 :
172 308 : output logic [31:1] dec_tlu_i0_pc_r, // i0 trap pc
173 :
174 18 : output logic [31:0] dec_illegal_inst, // illegal inst
175 138654 : output logic [31:1] pred_correct_npc_x, // npc e2 if the prediction is correct
176 :
177 506364 : output el2_predict_pkt_t dec_i0_predict_p_d, // i0 predict packet decode
178 631672 : output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
179 651076 : output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
180 21217 : output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag
181 :
182 0 : output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
183 :
184 6189473 : output logic [1:0] dec_data_en, // clock-gating logic
185 5991939 : output logic [1:0] dec_ctl_en,
186 :
187 6190087 : output logic dec_pmu_instr_decoded, // number of instructions decode this cycle encoded
188 238142 : output logic dec_pmu_decode_stall, // decode is stalled
189 264 : output logic dec_pmu_presync_stall, // decode has presync stall
190 14500 : output logic dec_pmu_postsync_stall, // decode has postsync stall
191 :
192 920884 : output logic dec_nonblock_load_wen, // write enable for nonblock load
193 368914 : output logic [4:0] dec_nonblock_load_waddr, // logical write addr for nonblock load
194 0 : output logic dec_pause_state, // core in pause state
195 0 : output logic dec_pause_state_cg, // pause state for clock-gating
196 :
197 159496 : output logic dec_div_active, // non-block divide is active
198 :
199 0 : input logic scan_mode
200 : );
201 :
202 :
203 :
204 :
205 13730 : el2_dec_pkt_t i0_dp_raw, i0_dp;
206 :
207 468420 : logic [31:0] i0;
208 6006883 : logic i0_valid_d;
209 :
210 314049 : logic [31:0] i0_result_r;
211 :
212 25118 : logic [2:0] i0_rs1bypass, i0_rs2bypass;
213 :
214 442798 : logic i0_jalimm20;
215 430821 : logic i0_uiimm20;
216 :
217 2280185 : logic lsu_decode_d;
218 2134567 : logic [31:0] i0_immed_d;
219 70084 : logic i0_presync;
220 120087 : logic i0_postsync;
221 :
222 110610 : logic postsync_stall;
223 110610 : logic ps_stall;
224 :
225 5991939 : logic prior_inflight, prior_inflight_wb;
226 :
227 10618 : logic csr_clr_d, csr_set_d, csr_write_d;
228 :
229 7868 : logic csr_clr_x,csr_set_x,csr_write_x,csr_imm_x;
230 4282 : logic [31:0] csr_mask_x;
231 2652 : logic [31:0] write_csr_data_x;
232 2652 : logic [31:0] write_csr_data_in;
233 1318 : logic [31:0] write_csr_data;
234 33070 : logic csr_data_wen;
235 :
236 10844 : logic [4:0] csrimm_x;
237 :
238 1554 : logic [31:0] csr_rddata_x;
239 :
240 250948 : logic mul_decode_d;
241 159496 : logic div_decode_d;
242 159496 : logic div_e1_to_r;
243 2628 : logic div_flush;
244 159496 : logic div_active_in;
245 159496 : logic div_active;
246 8228 : logic i0_nonblock_div_stall;
247 1472 : logic i0_div_prior_div_stall;
248 2628 : logic nonblock_div_cancel;
249 :
250 5997067 : logic i0_legal;
251 258 : logic shift_illegal;
252 258 : logic illegal_inst_en;
253 258 : logic illegal_lockout_in, illegal_lockout;
254 6189849 : logic i0_legal_decode_d;
255 315576 : logic i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
256 :
257 1376313 : logic [12:1] last_br_immed_d;
258 1920488 : logic i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
259 170364 : logic i0_rs2_depend_i0_x, i0_rs2_depend_i0_r;
260 :
261 159496 : logic i0_div_decode_d;
262 0 : logic i0_load_block_d;
263 155352 : logic [1:0] i0_rs1_depth_d, i0_rs2_depth_d;
264 :
265 27508 : logic i0_load_stall_d;
266 6856 : logic i0_store_stall_d;
267 :
268 767143 : logic i0_predict_nt, i0_predict_t;
269 :
270 28608 : logic i0_notbr_error, i0_br_toffset_error;
271 396 : logic i0_ret_error;
272 38500 : logic i0_br_error;
273 38510 : logic i0_br_error_all;
274 1571805 : logic [11:0] i0_br_offset;
275 :
276 1432006 : logic [20:1] i0_pcall_imm; // predicted jal's
277 5586531 : logic i0_pcall_12b_offset;
278 122488 : logic i0_pcall_raw;
279 122818 : logic i0_pcall_case;
280 122134 : logic i0_pcall;
281 :
282 312544 : logic i0_pja_raw;
283 321698 : logic i0_pja_case;
284 311586 : logic i0_pja;
285 :
286 167480 : logic i0_pret_case;
287 167480 : logic i0_pret_raw, i0_pret;
288 :
289 106068 : logic i0_jal; // jal's that are not predicted
290 :
291 :
292 3700988 : logic i0_predict_br;
293 :
294 0 : logic store_data_bypass_d, store_data_bypass_m;
295 :
296 4226 : el2_class_pkt_t i0_rs1_class_d, i0_rs2_class_d;
297 :
298 234134 : el2_class_pkt_t i0_d_c, i0_x_c, i0_r_c;
299 :
300 :
301 5735369 : logic i0_ap_pc2, i0_ap_pc4;
302 :
303 6449133 : logic i0_rd_en_d;
304 :
305 69392 : logic load_ldst_bypass_d;
306 :
307 0 : logic leak1_i0_stall_in, leak1_i0_stall;
308 0 : logic leak1_i1_stall_in, leak1_i1_stall;
309 0 : logic leak1_mode;
310 :
311 8779 : logic i0_csr_write_only_d;
312 :
313 5992087 : logic prior_inflight_x, prior_inflight_eff;
314 83863 : logic any_csr_d;
315 :
316 8776 : logic prior_csr_write;
317 :
318 6189398 : logic [3:0] i0_pipe_en;
319 5991905 : logic i0_r_ctl_en, i0_x_ctl_en, i0_wb_ctl_en;
320 6189448 : logic i0_x_data_en, i0_r_data_en, i0_wb_data_en;
321 :
322 0 : logic debug_fence_i;
323 0 : logic debug_fence;
324 :
325 25025 : logic i0_csr_write;
326 264 : logic presync_stall;
327 :
328 198 : logic i0_instr_error;
329 198 : logic i0_icaf_d;
330 :
331 58638 : logic clear_pause;
332 0 : logic pause_state_in, pause_state;
333 0 : logic pause_stall;
334 :
335 3092343 : logic i0_brp_valid;
336 737208 : logic nonblock_load_cancel;
337 1346966 : logic lsu_idle;
338 48786 : logic lsu_pmu_misaligned_r;
339 74956 : logic csr_ren_qual_d;
340 74956 : logic csr_read_x;
341 349570 : logic i0_block_d;
342 315576 : logic i0_block_raw_d; // This is use to create the raw valid
343 110611 : logic ps_stall_in;
344 660429 : logic [31:0] i0_result_x;
345 :
346 31368 : el2_dest_pkt_t d_d, x_d, r_d, wbd;
347 31368 : el2_dest_pkt_t x_d_in, r_d_in;
348 :
349 0 : el2_trap_pkt_t d_t, x_t, x_t_in, r_t_in, r_t;
350 :
351 0 : logic [3:0] lsu_trigger_match_r;
352 :
353 308 : logic [31:1] dec_i0_pc_r;
354 :
355 41933 : logic csr_read, csr_write;
356 106068 : logic i0_br_unpred;
357 :
358 881494 : logic nonblock_load_valid_m_delay;
359 6514124 : logic i0_wen_r;
360 :
361 0 : logic tlu_wr_pause_r1;
362 0 : logic tlu_wr_pause_r2;
363 :
364 672564 : logic flush_final_r;
365 :
366 317 : logic bitmanip_zbb_legal;
367 317 : logic bitmanip_zbs_legal;
368 317 : logic bitmanip_zbe_legal;
369 317 : logic bitmanip_zbc_legal;
370 323 : logic bitmanip_zbp_legal;
371 317 : logic bitmanip_zbr_legal;
372 317 : logic bitmanip_zbf_legal;
373 317 : logic bitmanip_zba_legal;
374 317 : logic bitmanip_zbb_zbp_legal;
375 317 : logic bitmanip_zbp_zbe_zbf_legal;
376 317 : logic bitmanip_zbb_zbp_zbe_zbf_legal;
377 323 : logic bitmanip_legal;
378 :
379 0 : logic data_gate_en;
380 0 : logic data_gate_clk;
381 :
382 :
383 : localparam NBLOAD_SIZE = pt.LSU_NUM_NBLOAD;
384 : localparam NBLOAD_SIZE_MSB = int'(pt.LSU_NUM_NBLOAD)-1;
385 : localparam NBLOAD_TAG_MSB = pt.LSU_NUM_NBLOAD_WIDTH-1;
386 :
387 :
388 920896 : logic cam_write, cam_inv_reset, cam_data_reset;
389 36662 : logic [NBLOAD_TAG_MSB:0] cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
390 5812 : logic [NBLOAD_SIZE_MSB:0] cam_wen;
391 :
392 36662 : logic [NBLOAD_TAG_MSB:0] load_data_tag;
393 6392 : logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
394 :
395 5811 : el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam;
396 5811 : el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_in;
397 5811 : el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_raw;
398 :
399 531394 : logic [4:0] nonblock_load_rd;
400 190690 : logic i0_nonblock_load_stall;
401 89472 : logic i0_nonblock_boundary_stall;
402 :
403 26942 : logic i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d;
404 :
405 881494 : logic i0_load_kill_wen_r;
406 :
407 2411 : logic found;
408 :
409 5808 : logic [NBLOAD_SIZE_MSB:0] cam_inv_reset_val, cam_data_reset_val;
410 :
411 0 : logic debug_fence_raw;
412 :
413 314049 : logic [31:0] i0_result_r_raw;
414 314049 : logic [31:0] i0_result_corr_r;
415 :
416 1134323 : logic [12:1] last_br_immed_x;
417 :
418 897486 : logic [31:0] i0_inst_d;
419 579534 : logic [31:0] i0_inst_x;
420 579533 : logic [31:0] i0_inst_r;
421 579533 : logic [31:0] i0_inst_wb_in;
422 579528 : logic [31:0] i0_inst_wb;
423 :
424 308 : logic [31:1] i0_pc_wb;
425 :
426 6189448 : logic i0_wb_en;
427 :
428 317 : logic trace_enable;
429 :
430 0 : logic debug_valid_x;
431 :
432 2152010 : el2_inst_pkt_t i0_itype;
433 2345922 : el2_reg_pkt_t i0r;
434 :
435 :
436 : rvdffie #(8) misc1ff (.*,
437 : .clk(free_l2clk),
438 : .din( {leak1_i1_stall_in,leak1_i0_stall_in,dec_tlu_flush_extint,pause_state_in ,dec_tlu_wr_pause_r, tlu_wr_pause_r1,illegal_lockout_in,ps_stall_in}),
439 : .dout({leak1_i1_stall, leak1_i0_stall, dec_extint_stall, pause_state, tlu_wr_pause_r1,tlu_wr_pause_r2,illegal_lockout, ps_stall })
440 : );
441 :
442 : rvdffie #(8) misc2ff (.*,
443 : .clk(free_l2clk),
444 : .din( {lsu_trigger_match_m[3:0],lsu_pmu_misaligned_m,div_active_in,exu_flush_final, dec_debug_valid_d}),
445 : .dout({lsu_trigger_match_r[3:0],lsu_pmu_misaligned_r,div_active, flush_final_r, debug_valid_x})
446 : );
447 :
448 : if(pt.BTB_ENABLE==1) begin
449 : // branch prediction
450 :
451 :
452 : // in leak1_mode, ignore any predictions for i0, treat branch as if we haven't seen it before
453 : // in leak1 mode, also ignore branch errors for i0
454 : assign i0_brp_valid = dec_i0_brp.valid & ~leak1_mode & ~i0_icaf_d;
455 :
456 : assign dec_i0_predict_p_d.misp = '0;
457 : assign dec_i0_predict_p_d.ataken = '0;
458 : assign dec_i0_predict_p_d.boffset = '0;
459 :
460 : assign dec_i0_predict_p_d.pcall = i0_pcall; // don't mark as pcall if branch error
461 : assign dec_i0_predict_p_d.pja = i0_pja;
462 : assign dec_i0_predict_p_d.pret = i0_pret;
463 : assign dec_i0_predict_p_d.prett[31:1] = dec_i0_brp.prett[31:1];
464 : assign dec_i0_predict_p_d.pc4 = dec_i0_pc4_d;
465 : assign dec_i0_predict_p_d.hist[1:0] = dec_i0_brp.hist[1:0];
466 : assign dec_i0_predict_p_d.valid = i0_brp_valid & i0_legal_decode_d;
467 : assign i0_notbr_error = i0_brp_valid & ~(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw);
468 :
469 : // no toffset error for a pret
470 : assign i0_br_toffset_error = i0_brp_valid & dec_i0_brp.hist[1] & (dec_i0_brp.toffset[11:0] != i0_br_offset[11:0]) & ~i0_pret_raw;
471 : assign i0_ret_error = i0_brp_valid & (dec_i0_brp.ret ^ i0_pret_raw);
472 : assign i0_br_error = dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error;
473 : assign dec_i0_predict_p_d.br_error = i0_br_error & i0_legal_decode_d & ~leak1_mode;
474 : assign dec_i0_predict_p_d.br_start_error = dec_i0_brp.br_start_error & i0_legal_decode_d & ~leak1_mode;
475 : assign i0_predict_index_d[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = dec_i0_bp_index;
476 :
477 : assign i0_predict_btag_d[pt.BTB_BTAG_SIZE-1:0] = dec_i0_bp_btag[pt.BTB_BTAG_SIZE-1:0];
478 : assign i0_br_error_all = (i0_br_error | dec_i0_brp.br_start_error) & ~leak1_mode;
479 : assign dec_i0_predict_p_d.toffset[11:0] = i0_br_offset[11:0];
480 : assign i0_predict_fghr_d[pt.BHT_GHR_SIZE-1:0] = dec_i0_bp_fghr[pt.BHT_GHR_SIZE-1:0];
481 : assign dec_i0_predict_p_d.way = dec_i0_brp.way;
482 :
483 :
484 : if(pt.BTB_FULLYA) begin : genblock
485 : logic btb_error_found, btb_error_found_f;
486 : logic [$clog2(pt.BTB_SIZE)-1:0] fa_error_index_ns;
487 :
488 : assign btb_error_found = (i0_br_error_all | btb_error_found_f) & ~dec_tlu_flush_lower_r;
489 : assign fa_error_index_ns = (i0_br_error_all & ~btb_error_found_f) ? dec_i0_bp_fa_index : dec_fa_error_index;
490 :
491 : rvdff #($clog2(pt.BTB_SIZE)+1) btberrorfa_f (.*, .clk(active_clk),
492 : .din({btb_error_found, fa_error_index_ns}),
493 : .dout({btb_error_found_f, dec_fa_error_index}));
494 :
495 :
496 : end
497 : else
498 : assign dec_fa_error_index = 'b0;
499 :
500 :
501 : // end
502 : end // if (pt.BTB_ENABLE==1)
503 : else begin
504 :
505 : always_comb begin
506 : dec_i0_predict_p_d = '0;
507 : dec_i0_predict_p_d.pcall = i0_pcall; // don't mark as pcall if branch error
508 : dec_i0_predict_p_d.pja = i0_pja;
509 : dec_i0_predict_p_d.pret = i0_pret;
510 : dec_i0_predict_p_d.pc4 = dec_i0_pc4_d;
511 : end
512 :
513 : assign i0_br_error_all = '0;
514 : assign i0_predict_index_d = '0;
515 : assign i0_predict_btag_d = '0;
516 : assign i0_predict_fghr_d = '0;
517 : assign i0_brp_valid = '0;
518 : end // else: !if(pt.BTB_ENABLE==1)
519 :
520 : // on br error turn anything into a nop
521 : // on i0 instruction fetch access fault turn anything into a nop
522 : // nop => alu rs1 imm12 rd lor
523 :
524 : assign i0_icaf_d = dec_i0_icaf_d | dec_i0_dbecc_d;
525 :
526 : assign i0_instr_error = i0_icaf_d;
527 :
528 317 : always_comb begin
529 317 : i0_dp = i0_dp_raw;
530 1744660 : if (i0_br_error_all | i0_instr_error) begin
531 40180 : i0_dp = '0;
532 40180 : i0_dp.alu = 1'b1;
533 40180 : i0_dp.rs1 = 1'b1;
534 40180 : i0_dp.rs2 = 1'b1;
535 40180 : i0_dp.lor = 1'b1;
536 40180 : i0_dp.legal = 1'b1;
537 40180 : i0_dp.postsync = 1'b1;
538 : end
539 : end
540 :
541 : assign i0[31:0] = dec_i0_instr_d[31:0];
542 :
543 : assign dec_i0_select_pc_d = i0_dp.pc;
544 :
545 : // branches that can be predicted
546 :
547 : assign i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
548 :
549 : assign i0_predict_nt = ~(dec_i0_brp.hist[1] & i0_brp_valid) & i0_predict_br;
550 : assign i0_predict_t = (dec_i0_brp.hist[1] & i0_brp_valid) & i0_predict_br;
551 :
552 : assign i0_ap.add = i0_dp.add;
553 : assign i0_ap.sub = i0_dp.sub;
554 : assign i0_ap.land = i0_dp.land;
555 : assign i0_ap.lor = i0_dp.lor;
556 : assign i0_ap.lxor = i0_dp.lxor;
557 : assign i0_ap.sll = i0_dp.sll;
558 : assign i0_ap.srl = i0_dp.srl;
559 : assign i0_ap.sra = i0_dp.sra;
560 : assign i0_ap.slt = i0_dp.slt;
561 : assign i0_ap.unsign = i0_dp.unsign;
562 : assign i0_ap.beq = i0_dp.beq;
563 : assign i0_ap.bne = i0_dp.bne;
564 : assign i0_ap.blt = i0_dp.blt;
565 : assign i0_ap.bge = i0_dp.bge;
566 :
567 : assign i0_ap.clz = i0_dp.clz;
568 : assign i0_ap.ctz = i0_dp.ctz;
569 : assign i0_ap.cpop = i0_dp.cpop;
570 : assign i0_ap.sext_b = i0_dp.sext_b;
571 : assign i0_ap.sext_h = i0_dp.sext_h;
572 : assign i0_ap.sh1add = i0_dp.sh1add;
573 : assign i0_ap.sh2add = i0_dp.sh2add;
574 : assign i0_ap.sh3add = i0_dp.sh3add;
575 : assign i0_ap.zba = i0_dp.zba;
576 : assign i0_ap.min = i0_dp.min;
577 : assign i0_ap.max = i0_dp.max;
578 : assign i0_ap.pack = i0_dp.pack;
579 : assign i0_ap.packu = i0_dp.packu;
580 : assign i0_ap.packh = i0_dp.packh;
581 : assign i0_ap.rol = i0_dp.rol;
582 : assign i0_ap.ror = i0_dp.ror;
583 : assign i0_ap.grev = i0_dp.grev;
584 : assign i0_ap.gorc = i0_dp.gorc;
585 : assign i0_ap.zbb = i0_dp.zbb;
586 : assign i0_ap.bset = i0_dp.bset;
587 : assign i0_ap.bclr = i0_dp.bclr;
588 : assign i0_ap.binv = i0_dp.binv;
589 : assign i0_ap.bext = i0_dp.bext;
590 :
591 : assign i0_ap.csr_write = i0_csr_write_only_d;
592 : assign i0_ap.csr_imm = i0_dp.csr_imm;
593 : assign i0_ap.jal = i0_jal;
594 :
595 : assign i0_ap_pc2 = ~dec_i0_pc4_d;
596 : assign i0_ap_pc4 = dec_i0_pc4_d;
597 :
598 : assign i0_ap.predict_nt = i0_predict_nt;
599 : assign i0_ap.predict_t = i0_predict_t;
600 :
601 :
602 : // non block load cam logic
603 :
604 317 : always_comb begin
605 317 : found = 0;
606 317 : for (int i=0; i<NBLOAD_SIZE; i++) begin
607 10974 : if (~found) begin
608 2573985 : if (~cam[i].valid) begin
609 23580095 : cam_wen[i] = cam_write;
610 23580095 : found = 1'b1;
611 : end
612 2573985 : else begin
613 2573985 : cam_wen[i] = 0;
614 : end
615 : end
616 : else
617 81057788 : cam_wen[i] = 0;
618 : end
619 : end
620 :
621 : assign cam_write = lsu_nonblock_load_valid_m;
622 : assign cam_write_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_tag_m[NBLOAD_TAG_MSB:0];
623 :
624 : assign cam_inv_reset = lsu_nonblock_load_inv_r;
625 : assign cam_inv_reset_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0];
626 :
627 : assign cam_data_reset = lsu_nonblock_load_data_valid | lsu_nonblock_load_data_error;
628 : assign cam_data_reset_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_data_tag[NBLOAD_TAG_MSB:0];
629 :
630 : assign nonblock_load_rd[4:0] = (x_d.i0load) ? x_d.i0rd[4:0] : 5'b0; // rd data
631 :
632 :
633 : // checks
634 :
635 : `ifdef RV_ASSERT_ON
636 : assert_dec_data_valid_data_error_onehot: assert #0 ($onehot0({lsu_nonblock_load_data_valid,lsu_nonblock_load_data_error}));
637 : assert_dec_cam_inv_reset_onehot: assert #0 ($onehot0(cam_inv_reset_val[NBLOAD_SIZE_MSB:0]));
638 : assert_dec_cam_data_reset_onehot: assert #0 ($onehot0(cam_data_reset_val[NBLOAD_SIZE_MSB:0]));
639 : `endif
640 :
641 :
642 :
643 : // case of multiple loads to same dest ie. x1 ... you have to invalidate the older one
644 :
645 0 : for (genvar i=0; i<NBLOAD_SIZE; i++) begin : cam_array
646 :
647 : assign cam_inv_reset_val[i] = cam_inv_reset & (cam_inv_reset_tag[NBLOAD_TAG_MSB:0] == cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid;
648 :
649 : assign cam_data_reset_val[i] = cam_data_reset & (cam_data_reset_tag[NBLOAD_TAG_MSB:0] == cam_raw[i].tag[NBLOAD_TAG_MSB:0]) & cam_raw[i].valid;
650 :
651 1268 : always_comb begin
652 :
653 1268 : cam[i] = cam_raw[i];
654 :
655 16946563 : if (cam_data_reset_val[i])
656 472907 : cam[i].valid = 1'b0;
657 :
658 1268 : cam_in[i] = '0;
659 :
660 1418800 : if (cam_wen[i]) begin
661 1418800 : cam_in[i].valid = 1'b1;
662 1418800 : cam_in[i].wb = 1'b0;
663 1418800 : cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
664 1418800 : cam_in[i].rd[4:0] = nonblock_load_rd[4:0];
665 : end
666 16654726 : else if ( (cam_inv_reset_val[i]) |
667 : (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
668 56444 : cam_in[i].valid = 1'b0;
669 : else
670 106615504 : cam_in[i] = cam[i];
671 :
672 17892695 : if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
673 1418727 : cam_in[i].wb = 1'b1;
674 :
675 : // force debug halt forces cam valids to 0; highest priority
676 97053128 : if (dec_tlu_force_halt)
677 0 : cam_in[i].valid = 1'b0;
678 : end
679 :
680 :
681 : rvdffie #( $bits(el2_load_cam_pkt_t) ) cam_ff (.*, .din(cam_in[i]), .dout(cam_raw[i]));
682 :
683 :
684 : assign nonblock_load_write[i] = (load_data_tag[NBLOAD_TAG_MSB:0] == cam_raw[i].tag[NBLOAD_TAG_MSB:0]) & cam_raw[i].valid;
685 :
686 :
687 : end : cam_array
688 :
689 :
690 :
691 : assign load_data_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_data_tag[NBLOAD_TAG_MSB:0];
692 :
693 : `ifdef RV_ASSERT_ON
694 : assert_dec_cam_nonblock_load_write_onehot: assert #0 ($onehot0(nonblock_load_write[NBLOAD_SIZE_MSB:0]));
695 : `endif
696 :
697 :
698 : assign nonblock_load_cancel = ((r_d_in.i0rd[4:0] == dec_nonblock_load_waddr[4:0]) & i0_wen_r); // cancel if any younger inst (including another nonblock) committing this cycle
699 :
700 :
701 : assign dec_nonblock_load_wen = lsu_nonblock_load_data_valid & |nonblock_load_write[NBLOAD_SIZE_MSB:0] & ~nonblock_load_cancel;
702 :
703 317 : always_comb begin
704 :
705 317 : dec_nonblock_load_waddr[4:0] = '0;
706 317 : i0_nonblock_load_stall = i0_nonblock_boundary_stall;
707 :
708 317 : for (int i=0; i<NBLOAD_SIZE; i++) begin
709 1268 : dec_nonblock_load_waddr[4:0] |= ({5{nonblock_load_write[i]}} & cam[i].rd[4:0]);
710 1268 : i0_nonblock_load_stall |= dec_i0_rs1_en_d & cam[i].valid & (cam[i].rd[4:0] == i0r.rs1[4:0]);
711 1268 : i0_nonblock_load_stall |= dec_i0_rs2_en_d & cam[i].valid & (cam[i].rd[4:0] == i0r.rs2[4:0]);
712 : end
713 :
714 : end
715 :
716 : assign i0_nonblock_boundary_stall = ((nonblock_load_rd[4:0]==i0r.rs1[4:0]) & lsu_nonblock_load_valid_m & dec_i0_rs1_en_d) |
717 : ((nonblock_load_rd[4:0]==i0r.rs2[4:0]) & lsu_nonblock_load_valid_m & dec_i0_rs2_en_d);
718 :
719 :
720 :
721 : // don't writeback a nonblock load
722 :
723 : rvdffs #(1) wbnbloaddelayff (.*, .clk(active_clk), .en(i0_r_ctl_en ), .din(lsu_nonblock_load_valid_m), .dout(nonblock_load_valid_m_delay) );
724 :
725 : assign i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load;
726 :
727 :
728 :
729 : // end non block load cam logic
730 :
731 : // pmu start
732 :
733 :
734 :
735 :
736 : assign csr_read = csr_ren_qual_d;
737 : assign csr_write = dec_csr_wen_unq_d;
738 :
739 : assign i0_br_unpred = i0_dp.jal & ~i0_predict_br;
740 :
741 : // the classes must be mutually exclusive with one another
742 :
743 317 : always_comb begin
744 317 : i0_itype = NULL_OP;
745 :
746 4523319 : if (i0_legal_decode_d) begin
747 1942801 : if (i0_dp.mul) i0_itype = MUL;
748 2801549 : if (i0_dp.load) i0_itype = LOAD;
749 2380807 : if (i0_dp.store) i0_itype = STORE;
750 3778541 : if (i0_dp.pm_alu) i0_itype = ALU;
751 8195979 : if (i0_dp.zbb | i0_dp.zbs |
752 : i0_dp.zbe | i0_dp.zbc |
753 : i0_dp.zbp | i0_dp.zbr |
754 : i0_dp.zbf | i0_dp.zba)
755 25713 : i0_itype = BITMANIPU;
756 2039335 : if ( csr_read & ~csr_write) i0_itype = CSRREAD;
757 328213 : if (~csr_read & csr_write) i0_itype = CSRWRITE;
758 6967003 : if ( csr_read & csr_write) i0_itype = CSRRW;
759 8035924 : if (i0_dp.ebreak) i0_itype = EBREAK;
760 4867703 : if (i0_dp.ecall) i0_itype = ECALL;
761 6734755 : if (i0_dp.fence) i0_itype = FENCE;
762 7048285 : if (i0_dp.fence_i) i0_itype = FENCEI; // fencei will set this even with fence attribute
763 4850509 : if (i0_dp.mret) i0_itype = MRET;
764 1799266 : if (i0_dp.condbr) i0_itype = CONDBR;
765 419543 : if (i0_dp.jal) i0_itype = JAL;
766 : end
767 : end
768 :
769 :
770 :
771 :
772 :
773 : // end pmu
774 :
775 :
776 : el2_dec_dec_ctl i0_dec (.inst(i0[31:0]),.out(i0_dp_raw));
777 :
778 :
779 :
780 :
781 : rvdff #(1) lsu_idle_ff (.*, .clk(active_clk), .din(lsu_idle_any), .dout(lsu_idle));
782 :
783 :
784 :
785 : assign leak1_i1_stall_in = (dec_tlu_flush_leak_one_r | (leak1_i1_stall & ~dec_tlu_flush_lower_r));
786 :
787 :
788 : assign leak1_mode = leak1_i1_stall;
789 :
790 : assign leak1_i0_stall_in = ((dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & ~dec_tlu_flush_lower_r));
791 :
792 :
793 :
794 :
795 : // 12b jal's can be predicted - these are calls
796 :
797 : assign i0_pcall_imm[20:1] = {i0[31],i0[19:12],i0[20],i0[30:21]};
798 :
799 : assign i0_pcall_12b_offset = (i0_pcall_imm[12]) ? (i0_pcall_imm[20:13] == 8'hff) : (i0_pcall_imm[20:13] == 8'h0);
800 :
801 : assign i0_pcall_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & (i0r.rd[4:0] == 5'd1 | i0r.rd[4:0] == 5'd5);
802 : assign i0_pja_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & ~(i0r.rd[4:0] == 5'd1 | i0r.rd[4:0] == 5'd5);
803 :
804 : assign i0_pcall_raw = i0_dp_raw.jal & i0_pcall_case; // this includes ja
805 : assign i0_pcall = i0_dp.jal & i0_pcall_case;
806 :
807 : assign i0_pja_raw = i0_dp_raw.jal & i0_pja_case;
808 : assign i0_pja = i0_dp.jal & i0_pja_case;
809 :
810 :
811 : assign i0_br_offset[11:0] = (i0_pcall_raw | i0_pja_raw) ? i0_pcall_imm[12:1] : {i0[31],i0[7],i0[30:25],i0[11:8]};
812 :
813 : assign i0_pret_case = (i0_dp_raw.jal & i0_dp_raw.imm12 & (i0r.rd[4:0] == 5'b0) & (i0r.rs1[4:0] == 5'd1 | i0r.rs1[4:0] == 5'd5)); // jalr with rd==0, rs1==1 or rs1==5 is a ret
814 :
815 : assign i0_pret_raw = i0_dp_raw.jal & i0_pret_case;
816 : assign i0_pret = i0_dp.jal & i0_pret_case;
817 :
818 : assign i0_jal = i0_dp.jal & ~i0_pcall_case & ~i0_pja_case & ~i0_pret_case;
819 :
820 : // lsu stuff
821 : // load/store mutually exclusive
822 : assign dec_lsu_offset_d[11:0] = ({12{ ~dec_extint_stall & i0_dp.lsu & i0_dp.load}} & i0[31:20]) |
823 : ({12{ ~dec_extint_stall & i0_dp.lsu & i0_dp.store}} & {i0[31:25],i0[11:7]});
824 :
825 :
826 :
827 : assign div_p.valid = div_decode_d;
828 :
829 : assign div_p.unsign = i0_dp.unsign;
830 : assign div_p.rem = i0_dp.rem;
831 :
832 :
833 : assign mul_p.valid = mul_decode_d;
834 :
835 : assign mul_p.rs1_sign = i0_dp.rs1_sign;
836 : assign mul_p.rs2_sign = i0_dp.rs2_sign;
837 : assign mul_p.low = i0_dp.low;
838 : assign mul_p.bcompress = i0_dp.bcompress;
839 : assign mul_p.bdecompress = i0_dp.bdecompress;
840 : assign mul_p.clmul = i0_dp.clmul;
841 : assign mul_p.clmulh = i0_dp.clmulh;
842 : assign mul_p.clmulr = i0_dp.clmulr;
843 : assign mul_p.grev = i0_dp.grev;
844 : assign mul_p.gorc = i0_dp.gorc;
845 : assign mul_p.shfl = i0_dp.shfl;
846 : assign mul_p.unshfl = i0_dp.unshfl;
847 : assign mul_p.xperm_n = i0_dp.xperm_n;
848 : assign mul_p.xperm_b = i0_dp.xperm_b;
849 : assign mul_p.xperm_h = i0_dp.xperm_h;
850 : assign mul_p.crc32_b = i0_dp.crc32_b;
851 : assign mul_p.crc32_h = i0_dp.crc32_h;
852 : assign mul_p.crc32_w = i0_dp.crc32_w;
853 : assign mul_p.crc32c_b = i0_dp.crc32c_b;
854 : assign mul_p.crc32c_h = i0_dp.crc32c_h;
855 : assign mul_p.crc32c_w = i0_dp.crc32c_w;
856 : assign mul_p.bfp = i0_dp.bfp;
857 :
858 :
859 317 : always_comb begin
860 317 : lsu_p = '0;
861 :
862 24263282 : if (dec_extint_stall) begin
863 0 : lsu_p.load = 1'b1;
864 0 : lsu_p.word = 1'b1;
865 0 : lsu_p.fast_int = 1'b1;
866 0 : lsu_p.valid = 1'b1;
867 : end
868 24263282 : else begin
869 24263282 : lsu_p.valid = lsu_decode_d;
870 :
871 24263282 : lsu_p.load = i0_dp.load ;
872 24263282 : lsu_p.store = i0_dp.store;
873 24263282 : lsu_p.by = i0_dp.by ;
874 24263282 : lsu_p.half = i0_dp.half ;
875 24263282 : lsu_p.word = i0_dp.word ;
876 24263282 : lsu_p.stack = (i0r.rs1[4:0]==5'd2); // stack reference
877 :
878 24263282 : lsu_p.load_ldst_bypass_d = load_ldst_bypass_d ;
879 24263282 : lsu_p.store_data_bypass_d = store_data_bypass_d;
880 24263282 : lsu_p.store_data_bypass_m = store_data_bypass_m;
881 :
882 24263282 : lsu_p.unsign = i0_dp.unsign;
883 : end
884 : end
885 :
886 :
887 : assign dec_lsu_valid_raw_d = (i0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & ~dma_dccm_stall_any & ~i0_block_raw_d) | dec_extint_stall;
888 :
889 :
890 :
891 : assign i0r.rs1[4:0] = i0[19:15];
892 : assign i0r.rs2[4:0] = i0[24:20];
893 : assign i0r.rd[4:0] = i0[11:7];
894 :
895 :
896 : assign dec_i0_rs1_en_d = i0_dp.rs1 & (i0r.rs1[4:0] != 5'd0); // if rs1_en=0 then read will be all 0's
897 : assign dec_i0_rs2_en_d = i0_dp.rs2 & (i0r.rs2[4:0] != 5'd0);
898 : assign i0_rd_en_d = i0_dp.rd & (i0r.rd[4:0] != 5'd0);
899 :
900 : assign dec_i0_rs1_d[4:0] = i0r.rs1[4:0];
901 : assign dec_i0_rs2_d[4:0] = i0r.rs2[4:0];
902 :
903 :
904 : assign i0_jalimm20 = i0_dp.jal & i0_dp.imm20; // jal
905 : assign i0_uiimm20 = ~i0_dp.jal & i0_dp.imm20;
906 :
907 :
908 : // csr logic
909 :
910 : assign dec_csr_ren_d = i0_dp.csr_read & i0_valid_d;
911 : assign csr_ren_qual_d = i0_dp.csr_read & i0_legal_decode_d;
912 :
913 : assign csr_clr_d = i0_dp.csr_clr & i0_legal_decode_d;
914 : assign csr_set_d = i0_dp.csr_set & i0_legal_decode_d;
915 : assign csr_write_d = i0_csr_write & i0_legal_decode_d;
916 :
917 : assign i0_csr_write_only_d = i0_csr_write & ~i0_dp.csr_read;
918 :
919 : assign dec_csr_wen_unq_d = (i0_dp.csr_clr | i0_dp.csr_set | i0_csr_write) & i0_valid_d; // for csr legal, can't write read-only csr
920 :
921 : assign dec_csr_any_unq_d = any_csr_d & i0_valid_d;
922 :
923 :
924 : assign dec_csr_rdaddr_d[11:0] = {12{dec_csr_any_unq_d}} & i0[31:20];
925 : assign dec_csr_rdaddr_r[11:0] = {12{~r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];
926 : assign dec_csr_wraddr_r[11:0] = {12{r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];
927 :
928 :
929 : // make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb
930 : // also use valid so it's flushable
931 : assign dec_csr_wen_r = r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_r;
932 :
933 : // If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write.
934 : assign dec_csr_stall_int_ff = ((r_d.csraddr[11:0] == 12'h300) | (r_d.csraddr[11:0] == 12'h304)) & r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_wb;
935 :
936 :
937 : rvdff #(5) csrmiscff (.*,
938 : .clk (active_clk),
939 : .din ({csr_ren_qual_d, csr_clr_d, csr_set_d, csr_write_d, i0_dp.csr_imm}),
940 : .dout({csr_read_x, csr_clr_x, csr_set_x, csr_write_x, csr_imm_x})
941 : );
942 :
943 :
944 :
945 :
946 : // perform the update operation if any
947 :
948 : rvdffe #(37) csr_rddata_x_ff (.*, .en(i0_x_data_en & any_csr_d), .din( {i0[19:15],dec_csr_rddata_d[31:0]}), .dout({csrimm_x[4:0],csr_rddata_x[31:0]}));
949 :
950 :
951 : assign csr_mask_x[31:0] = ({32{ csr_imm_x}} & {27'b0,csrimm_x[4:0]}) |
952 : ({32{~csr_imm_x}} & exu_csr_rs1_x[31:0] );
953 :
954 :
955 : assign write_csr_data_x[31:0] = ({32{csr_clr_x}} & (csr_rddata_x[31:0] & ~csr_mask_x[31:0])) |
956 : ({32{csr_set_x}} & (csr_rddata_x[31:0] | csr_mask_x[31:0])) |
957 : ({32{csr_write_x}} & ( csr_mask_x[31:0]));
958 :
959 :
960 : // pause instruction
961 :
962 :
963 :
964 :
965 : assign clear_pause = (dec_tlu_flush_lower_r & ~dec_tlu_flush_pause_r) |
966 : (pause_state & (write_csr_data[31:1] == 31'b0)); // if 0 or 1 then exit pause state - 1 cycle pause
967 :
968 : assign pause_state_in = (dec_tlu_wr_pause_r | pause_state) & ~clear_pause;
969 :
970 :
971 :
972 : assign dec_pause_state = pause_state;
973 :
974 :
975 :
976 : assign dec_pause_state_cg = pause_state & ~tlu_wr_pause_r1 & ~tlu_wr_pause_r2;
977 :
978 : // end pause
979 :
980 :
981 : assign csr_data_wen = ((csr_clr_x | csr_set_x | csr_write_x) & csr_read_x) | dec_tlu_wr_pause_r | pause_state;
982 :
983 : assign write_csr_data_in[31:0] = (pause_state) ? (write_csr_data[31:0] - 32'b1) :
984 : (dec_tlu_wr_pause_r) ? dec_csr_wrdata_r[31:0] : write_csr_data_x[31:0];
985 :
986 : // will hold until write-back at which time the CSR will be updated while GPR is possibly written with prior CSR
987 : rvdffe #(32) write_csr_ff (.*, .clk(free_l2clk), .en(csr_data_wen), .din(write_csr_data_in[31:0]), .dout(write_csr_data[31:0]));
988 :
989 : assign pause_stall = pause_state;
990 :
991 : // for csr write only data is produced by the alu
992 : assign dec_csr_wrdata_r[31:0] = (r_d.csrwonly & r_d.i0valid) ? i0_result_corr_r[31:0] : write_csr_data[31:0];
993 :
994 :
995 :
996 : assign dec_i0_immed_d[31:0] = i0_immed_d[31:0];
997 :
998 : assign i0_immed_d[31:0] = ({32{i0_dp.imm12}} & { {20{i0[31]}},i0[31:20] }) | // jalr
999 : ({32{i0_dp.shimm5}} & { 27'b0, i0[24:20] }) |
1000 : ({32{i0_jalimm20}} & { {12{i0[31]}},i0[19:12],i0[20],i0[30:21],1'b0}) |
1001 : ({32{i0_uiimm20}} & { i0[31:12],12'b0 }) |
1002 : ({32{i0_csr_write_only_d & i0_dp.csr_imm}} & { 27'b0, i0[19:15]}); // for csr's that only write csr, dont read csr
1003 :
1004 :
1005 : // all conditional branches are currently predict_nt
1006 : // change this to generate the sequential address for all other cases for NPC requirements at commit
1007 : assign dec_i0_br_immed_d[12:1] = (i0_ap.predict_nt & ~i0_dp.jal) ? i0_br_offset[11:0] : {10'b0,i0_ap_pc4,i0_ap_pc2};
1008 :
1009 :
1010 : assign last_br_immed_d[12:1] = ((i0_ap.predict_nt) ? {10'b0,i0_ap_pc4,i0_ap_pc2} : i0_br_offset[11:0] );
1011 :
1012 : assign i0_valid_d = dec_ib0_valid_d;
1013 :
1014 : // load_stall includes bus_barrier
1015 :
1016 : assign i0_load_stall_d = (i0_dp.load ) & (lsu_load_stall_any | dma_dccm_stall_any);
1017 :
1018 : assign i0_store_stall_d = i0_dp.store & (lsu_store_stall_any | dma_dccm_stall_any);
1019 :
1020 :
1021 :
1022 : // some CSR reads need to be presync'd
1023 : assign i0_presync = i0_dp.presync | dec_tlu_presync_d | debug_fence_i | debug_fence_raw | dec_tlu_pipelining_disable; // both fence's presync
1024 :
1025 : // some CSR writes need to be postsync'd
1026 : assign i0_postsync = i0_dp.postsync | dec_tlu_postsync_d | debug_fence_i | // only fence_i postsync
1027 : (i0_csr_write_only_d & (i0[31:20] == 12'h7c2)); // wr_pause must postsync
1028 :
1029 :
1030 : // debug fence csr
1031 : assign debug_fence_i = dec_debug_fence_d & dbg_cmd_wrdata[0];
1032 : assign debug_fence_raw = dec_debug_fence_d & dbg_cmd_wrdata[1];
1033 :
1034 : assign debug_fence = debug_fence_raw | debug_fence_i; // fence_i causes a fence
1035 :
1036 : assign i0_csr_write = i0_dp.csr_write & ~dec_debug_fence_d;
1037 : // end debug
1038 :
1039 :
1040 : // lets make ebreak, ecall, mret postsync, so break sync into pre and post
1041 :
1042 : assign presync_stall = (i0_presync & prior_inflight_eff);
1043 :
1044 : assign prior_inflight_eff = (i0_dp.div) ? prior_inflight_x : prior_inflight;
1045 :
1046 : assign i0_div_prior_div_stall = i0_dp.div & div_active;
1047 :
1048 : // Raw block has everything excepts the stalls coming from the lsu
1049 : assign i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) |
1050 : dec_extint_stall |
1051 : pause_stall |
1052 : leak1_i0_stall |
1053 : dec_tlu_debug_stall |
1054 : postsync_stall |
1055 : presync_stall |
1056 : ((i0_dp.fence | debug_fence) & ~lsu_idle) |
1057 : i0_nonblock_load_stall |
1058 : i0_load_block_d |
1059 : i0_nonblock_div_stall |
1060 : i0_div_prior_div_stall;
1061 :
1062 : assign i0_block_d = i0_block_raw_d | i0_store_stall_d | i0_load_stall_d;
1063 : assign i0_exublock_d = i0_block_raw_d;
1064 :
1065 :
1066 : // block reads if there is a prior csr write in the pipeline
1067 : assign prior_csr_write = x_d.csrwonly |
1068 : r_d.csrwonly |
1069 : wbd.csrwonly;
1070 :
1071 :
1072 :
1073 : if (pt.BITMANIP_ZBB == 1)
1074 : assign bitmanip_zbb_legal = 1'b1;
1075 : else
1076 : assign bitmanip_zbb_legal = ~(i0_dp.zbb & ~i0_dp.zbp);
1077 :
1078 : if (pt.BITMANIP_ZBS == 1)
1079 : assign bitmanip_zbs_legal = 1'b1;
1080 : else
1081 : assign bitmanip_zbs_legal = ~i0_dp.zbs;
1082 :
1083 : if (pt.BITMANIP_ZBE == 1)
1084 : assign bitmanip_zbe_legal = 1'b1;
1085 : else
1086 : assign bitmanip_zbe_legal = ~(i0_dp.zbe & ~i0_dp.zbp & ~i0_dp.zbf);
1087 :
1088 : if (pt.BITMANIP_ZBC == 1)
1089 : assign bitmanip_zbc_legal = 1'b1;
1090 : else
1091 : assign bitmanip_zbc_legal = ~i0_dp.zbc;
1092 :
1093 : if (pt.BITMANIP_ZBP == 1)
1094 : assign bitmanip_zbp_legal = 1'b1;
1095 : else
1096 : assign bitmanip_zbp_legal = ~(i0_dp.zbp & ~i0_dp.zbb & ~i0_dp.zbe & ~i0_dp.zbf);
1097 :
1098 : if (pt.BITMANIP_ZBR == 1)
1099 : assign bitmanip_zbr_legal = 1'b1;
1100 : else
1101 : assign bitmanip_zbr_legal = ~i0_dp.zbr;
1102 :
1103 : if (pt.BITMANIP_ZBF == 1)
1104 : assign bitmanip_zbf_legal = 1'b1;
1105 : else
1106 : assign bitmanip_zbf_legal = ~(i0_dp.zbf & ~i0_dp.zbp & ~i0_dp.zbe);
1107 :
1108 : if (pt.BITMANIP_ZBA == 1)
1109 : assign bitmanip_zba_legal = 1'b1;
1110 : else
1111 : assign bitmanip_zba_legal = ~i0_dp.zba;
1112 :
1113 : if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) )
1114 : assign bitmanip_zbb_zbp_legal = 1'b1;
1115 : else
1116 : assign bitmanip_zbb_zbp_legal = ~(i0_dp.zbb & i0_dp.zbp & ~i0_dp.zbf); // added ~ZBF to exclude ZEXT.H
1117 :
1118 : if ( (pt.BITMANIP_ZBP == 1) | (pt.BITMANIP_ZBE == 1) | (pt.BITMANIP_ZBF == 1))
1119 : assign bitmanip_zbp_zbe_zbf_legal = 1'b1;
1120 : else
1121 : assign bitmanip_zbp_zbe_zbf_legal = ~(i0_dp.zbp & i0_dp.zbe & i0_dp.zbf & ~i0_dp.zbb); // added ~ZBB to exclude ZEXT.H
1122 :
1123 : if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) | (pt.BITMANIP_ZBE == 1) | (pt.BITMANIP_ZBF == 1))
1124 : assign bitmanip_zbb_zbp_zbe_zbf_legal = 1'b1;
1125 : else
1126 : assign bitmanip_zbb_zbp_zbe_zbf_legal = ~(i0_dp.zbp & i0_dp.zbe & i0_dp.zbf & i0_dp.zbb); // added only for ZEXT.H
1127 :
1128 :
1129 : assign any_csr_d = i0_dp.csr_read | i0_csr_write;
1130 : assign bitmanip_legal = bitmanip_zbb_legal & bitmanip_zbs_legal & bitmanip_zbe_legal & bitmanip_zbc_legal & bitmanip_zbp_legal & bitmanip_zbr_legal & bitmanip_zbf_legal & bitmanip_zba_legal & bitmanip_zbb_zbp_legal & bitmanip_zbp_zbe_zbf_legal & bitmanip_zbb_zbp_zbe_zbf_legal;
1131 :
1132 : assign i0_legal = i0_dp.legal & (~any_csr_d | dec_csr_legal_d) & bitmanip_legal;
1133 :
1134 :
1135 :
1136 : // illegal inst handling
1137 :
1138 :
1139 : assign shift_illegal = dec_i0_decode_d & ~i0_legal;
1140 :
1141 : assign illegal_inst_en = shift_illegal & ~illegal_lockout;
1142 :
1143 : rvdffe #(32) illegal_any_ff (.*, .en(illegal_inst_en), .din(i0_inst_d[31:0]), .dout(dec_illegal_inst[31:0]));
1144 :
1145 : assign illegal_lockout_in = (shift_illegal | illegal_lockout) & ~flush_final_r;
1146 :
1147 :
1148 :
1149 : // allow illegals to flow down the pipe
1150 : assign dec_i0_decode_d = i0_valid_d & ~i0_block_d & ~dec_tlu_flush_lower_r & ~flush_final_r;
1151 : assign i0_exudecode_d = i0_valid_d & ~i0_exublock_d & ~dec_tlu_flush_lower_r & ~flush_final_r;
1152 :
1153 : // define i0 legal decode
1154 : assign i0_legal_decode_d = dec_i0_decode_d & i0_legal;
1155 : assign i0_exulegal_decode_d = i0_exudecode_d & i0_legal;
1156 :
1157 :
1158 : // performance monitor signals
1159 : assign dec_pmu_instr_decoded = dec_i0_decode_d;
1160 :
1161 : assign dec_pmu_decode_stall = i0_valid_d & ~dec_i0_decode_d;
1162 :
1163 : assign dec_pmu_postsync_stall = postsync_stall & i0_valid_d;
1164 : assign dec_pmu_presync_stall = presync_stall & i0_valid_d;
1165 :
1166 :
1167 :
1168 : // illegals will postsync
1169 : assign ps_stall_in = ( dec_i0_decode_d & (i0_postsync | ~i0_legal) ) |
1170 : ( ps_stall & prior_inflight_x );
1171 :
1172 :
1173 :
1174 : assign postsync_stall = ps_stall;
1175 :
1176 :
1177 : assign prior_inflight_x = x_d.i0valid;
1178 : assign prior_inflight_wb = r_d.i0valid;
1179 :
1180 : assign prior_inflight = prior_inflight_x | prior_inflight_wb;
1181 :
1182 : assign dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp.alu;
1183 : assign dec_i0_branch_d = i0_dp.condbr | i0_dp.jal | i0_br_error_all;
1184 :
1185 : assign lsu_decode_d = i0_legal_decode_d & i0_dp.lsu;
1186 : assign mul_decode_d = i0_exulegal_decode_d & i0_dp.mul;
1187 : assign div_decode_d = i0_exulegal_decode_d & i0_dp.div;
1188 :
1189 : assign dec_qual_lsu_d = i0_dp.lsu;
1190 :
1191 :
1192 :
1193 :
1194 :
1195 : // scheduling logic for alu
1196 :
1197 : assign i0_rs1_depend_i0_x = dec_i0_rs1_en_d & x_d.i0v & (x_d.i0rd[4:0] == i0r.rs1[4:0]);
1198 : assign i0_rs1_depend_i0_r = dec_i0_rs1_en_d & r_d.i0v & (r_d.i0rd[4:0] == i0r.rs1[4:0]);
1199 :
1200 : assign i0_rs2_depend_i0_x = dec_i0_rs2_en_d & x_d.i0v & (x_d.i0rd[4:0] == i0r.rs2[4:0]);
1201 : assign i0_rs2_depend_i0_r = dec_i0_rs2_en_d & r_d.i0v & (r_d.i0rd[4:0] == i0r.rs2[4:0]);
1202 :
1203 :
1204 : // order the producers as follows: , i0_x, i0_r, i0_wb
1205 :
1206 : assign {i0_rs1_class_d, i0_rs1_depth_d[1:0]} = (i0_rs1_depend_i0_x ) ? { i0_x_c, 2'd1 } :
1207 : (i0_rs1_depend_i0_r ) ? { i0_r_c, 2'd2 } : '0;
1208 :
1209 : assign {i0_rs2_class_d, i0_rs2_depth_d[1:0]} = (i0_rs2_depend_i0_x ) ? { i0_x_c, 2'd1 } :
1210 : (i0_rs2_depend_i0_r ) ? { i0_r_c, 2'd2 } : '0;
1211 :
1212 :
1213 : // stores will bypass load data in the lsu pipe
1214 :
1215 : if (pt.LOAD_TO_USE_PLUS1 == 1) begin : genblock
1216 : assign i0_load_block_d = (i0_rs1_class_d.load & i0_rs1_depth_d[0]) |
1217 : (i0_rs2_class_d.load & i0_rs2_depth_d[0] & ~i0_dp.store);
1218 :
1219 : assign load_ldst_bypass_d = (i0_dp.load | i0_dp.store) & i0_rs1_depth_d[1] & i0_rs1_class_d.load;
1220 :
1221 : assign store_data_bypass_d = i0_dp.store & i0_rs2_depth_d[1] & i0_rs2_class_d.load;
1222 :
1223 : assign store_data_bypass_m = i0_dp.store & i0_rs2_depth_d[0] & i0_rs2_class_d.load;
1224 : end
1225 : else begin : genblock
1226 :
1227 : assign i0_load_block_d = 1'b0;
1228 :
1229 : assign load_ldst_bypass_d = (i0_dp.load | i0_dp.store) & i0_rs1_depth_d[0] & i0_rs1_class_d.load;
1230 :
1231 : assign store_data_bypass_d = i0_dp.store & i0_rs2_depth_d[0] & i0_rs2_class_d.load;
1232 :
1233 : assign store_data_bypass_m = 1'b0;
1234 : end
1235 :
1236 :
1237 :
1238 :
1239 :
1240 :
1241 : assign dec_tlu_i0_valid_r = r_d.i0valid & ~dec_tlu_flush_lower_wb;
1242 :
1243 :
1244 : assign d_t.legal = i0_legal_decode_d;
1245 : assign d_t.icaf = i0_icaf_d & i0_legal_decode_d; // dbecc is icaf exception
1246 : assign d_t.icaf_second = dec_i0_icaf_second_d & i0_legal_decode_d; // this includes icaf and dbecc
1247 : assign d_t.icaf_type[1:0] = dec_i0_icaf_type_d[1:0];
1248 :
1249 : assign d_t.fence_i = (i0_dp.fence_i | debug_fence_i) & i0_legal_decode_d;
1250 :
1251 : // put pmu info into the trap packet
1252 : assign d_t.pmu_i0_itype = i0_itype;
1253 : assign d_t.pmu_i0_br_unpred = i0_br_unpred;
1254 : assign d_t.pmu_divide = 1'b0;
1255 : assign d_t.pmu_lsu_misaligned = 1'b0;
1256 :
1257 : assign d_t.i0trigger[3:0] = dec_i0_trigger_match_d[3:0] & {4{dec_i0_decode_d}};
1258 :
1259 :
1260 :
1261 : rvdfflie #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_xff (.*, .en(i0_x_ctl_en), .din(d_t), .dout(x_t));
1262 :
1263 317 : always_comb begin
1264 317 : x_t_in = x_t;
1265 317 : x_t_in.i0trigger[3:0] = x_t.i0trigger & ~{4{dec_tlu_flush_lower_wb}};
1266 : end
1267 :
1268 :
1269 : rvdfflie #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_r_ff (.*, .en(i0_x_ctl_en), .din(x_t_in), .dout(r_t));
1270 :
1271 :
1272 317 : always_comb begin
1273 :
1274 317 : r_t_in = r_t;
1275 :
1276 317 : r_t_in.i0trigger[3:0] = ({4{(r_d.i0load | r_d.i0store)}} & lsu_trigger_match_r[3:0]) | r_t.i0trigger[3:0];
1277 317 : r_t_in.pmu_lsu_misaligned = lsu_pmu_misaligned_r; // only valid if a load/store is valid in DC3 stage
1278 :
1279 29372 : if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
1280 :
1281 : end
1282 :
1283 :
1284 317 : always_comb begin
1285 :
1286 317 : dec_tlu_packet_r = r_t_in;
1287 317 : dec_tlu_packet_r.pmu_divide = r_d.i0div & r_d.i0valid;
1288 :
1289 : end
1290 :
1291 :
1292 : // end tlu stuff
1293 :
1294 :
1295 : assign i0_d_c.mul = i0_dp.mul & i0_legal_decode_d;
1296 : assign i0_d_c.load = i0_dp.load & i0_legal_decode_d;
1297 : assign i0_d_c.alu = i0_dp.alu & i0_legal_decode_d;
1298 :
1299 : rvdffs #( $bits(el2_class_pkt_t) ) i0_x_c_ff (.*, .en(i0_x_ctl_en), .clk(active_clk), .din(i0_d_c), .dout(i0_x_c));
1300 : rvdffs #( $bits(el2_class_pkt_t) ) i0_r_c_ff (.*, .en(i0_r_ctl_en), .clk(active_clk), .din(i0_x_c), .dout(i0_r_c));
1301 :
1302 :
1303 : assign d_d.i0rd[4:0] = i0r.rd[4:0];
1304 : assign d_d.i0v = i0_rd_en_d & i0_legal_decode_d;
1305 : assign d_d.i0valid = dec_i0_decode_d; // has flush_final_r
1306 :
1307 : assign d_d.i0load = i0_dp.load & i0_legal_decode_d;
1308 : assign d_d.i0store = i0_dp.store & i0_legal_decode_d;
1309 : assign d_d.i0div = i0_dp.div & i0_legal_decode_d;
1310 :
1311 :
1312 : assign d_d.csrwen = dec_csr_wen_unq_d & i0_legal_decode_d;
1313 : assign d_d.csrwonly = i0_csr_write_only_d & dec_i0_decode_d;
1314 : assign d_d.csraddr[11:0] = i0[31:20]; // csr read/write address
1315 :
1316 :
1317 : rvdff #(3) i0cgff (.*, .clk(active_clk), .din(i0_pipe_en[3:1]), .dout(i0_pipe_en[2:0]));
1318 :
1319 : assign i0_pipe_en[3] = dec_i0_decode_d;
1320 :
1321 : assign i0_x_ctl_en = (|i0_pipe_en[3:2] | clk_override);
1322 : assign i0_r_ctl_en = (|i0_pipe_en[2:1] | clk_override);
1323 : assign i0_wb_ctl_en = (|i0_pipe_en[1:0] | clk_override);
1324 : assign i0_x_data_en = ( i0_pipe_en[3] | clk_override);
1325 : assign i0_r_data_en = ( i0_pipe_en[2] | clk_override);
1326 : assign i0_wb_data_en = ( i0_pipe_en[1] | clk_override);
1327 :
1328 : assign dec_data_en[1:0] = {i0_x_data_en, i0_r_data_en};
1329 : assign dec_ctl_en[1:0] = {i0_x_ctl_en, i0_r_ctl_en};
1330 :
1331 :
1332 :
1333 : rvdfflie #( .WIDTH($bits(el2_dest_pkt_t)),.LEFT(15) ) e1ff (.*, .en(i0_x_ctl_en), .din(d_d), .dout(x_d));
1334 :
1335 317 : always_comb begin
1336 317 : x_d_in = x_d;
1337 :
1338 317 : x_d_in.i0v = x_d.i0v & ~dec_tlu_flush_lower_wb & ~dec_tlu_flush_lower_r;
1339 317 : x_d_in.i0valid = x_d.i0valid & ~dec_tlu_flush_lower_wb & ~dec_tlu_flush_lower_r;
1340 : end
1341 :
1342 : rvdfflie #( .WIDTH($bits(el2_dest_pkt_t)), .LEFT(15) ) r_d_ff (.*, .en(i0_r_ctl_en), .din(x_d_in), .dout(r_d));
1343 :
1344 :
1345 317 : always_comb begin
1346 :
1347 317 : r_d_in = r_d;
1348 :
1349 :
1350 : // for the bench
1351 317 : r_d_in.i0rd[4:0] = r_d.i0rd[4:0];
1352 :
1353 317 : r_d_in.i0v = (r_d.i0v & ~dec_tlu_flush_lower_wb);
1354 317 : r_d_in.i0valid = (r_d.i0valid & ~dec_tlu_flush_lower_wb);
1355 :
1356 317 : r_d_in.i0load = r_d.i0load & ~dec_tlu_flush_lower_wb;
1357 317 : r_d_in.i0store = r_d.i0store & ~dec_tlu_flush_lower_wb;
1358 :
1359 : end
1360 :
1361 :
1362 : rvdfflie #(.WIDTH($bits(el2_dest_pkt_t)), .LEFT(15)) wbff (.*, .en(i0_wb_ctl_en), .din(r_d_in), .dout(wbd));
1363 :
1364 : assign dec_i0_waddr_r[4:0] = r_d_in.i0rd[4:0];
1365 :
1366 : assign i0_wen_r = r_d_in.i0v & ~dec_tlu_i0_kill_writeb_r;
1367 : assign dec_i0_wen_r = i0_wen_r & ~r_d_in.i0div & ~i0_load_kill_wen_r; // don't write a nonblock load 1st time down the pipe
1368 : assign dec_i0_wdata_r[31:0] = i0_result_corr_r[31:0];
1369 :
1370 :
1371 : // divide stuff
1372 : assign div_e1_to_r = (x_d.i0div & x_d.i0valid) |
1373 : (r_d.i0div & r_d.i0valid);
1374 :
1375 : assign div_active_in = i0_div_decode_d | (div_active & ~exu_div_wren & ~nonblock_div_cancel);
1376 :
1377 :
1378 : assign dec_div_active = div_active;
1379 :
1380 : // nonblocking div scheme
1381 :
1382 : assign i0_nonblock_div_stall = (dec_i0_rs1_en_d & div_active & (div_waddr_wb[4:0] == i0r.rs1[4:0])) |
1383 : (dec_i0_rs2_en_d & div_active & (div_waddr_wb[4:0] == i0r.rs2[4:0]));
1384 :
1385 :
1386 : assign div_flush = (x_d.i0div & x_d.i0valid & (x_d.i0rd[4:0]==5'b0) ) |
1387 : (x_d.i0div & x_d.i0valid & dec_tlu_flush_lower_r ) |
1388 : (r_d.i0div & r_d.i0valid & dec_tlu_flush_lower_r & dec_tlu_i0_kill_writeb_r);
1389 :
1390 :
1391 : // cancel if any younger inst committing this cycle to same dest as nonblock divide
1392 : assign nonblock_div_cancel = (div_active & div_flush) |
1393 : (div_active & ~div_e1_to_r & (r_d.i0rd[4:0] == div_waddr_wb[4:0]) & i0_wen_r);
1394 :
1395 : assign dec_div_cancel = nonblock_div_cancel;
1396 :
1397 :
1398 :
1399 : assign i0_div_decode_d = i0_legal_decode_d & i0_dp.div;
1400 :
1401 : // for load_to_use_plus1, the load result data is merged in R stage instead of D
1402 :
1403 : if ( pt.LOAD_TO_USE_PLUS1 == 1 ) begin : genblock1
1404 : assign i0_result_x[31:0] = exu_i0_result_x[31:0];
1405 : assign i0_result_r[31:0] = (r_d.i0v & r_d.i0load) ? lsu_result_m[31:0] : i0_result_r_raw[31:0];
1406 : end
1407 : else begin : genblock1
1408 : assign i0_result_x[31:0] = (x_d.i0v & x_d.i0load) ? lsu_result_m[31:0] : exu_i0_result_x[31:0];
1409 : assign i0_result_r[31:0] = i0_result_r_raw[31:0];
1410 : end
1411 :
1412 :
1413 : rvdffe #(32) i0_result_r_ff (.*, .en(i0_r_data_en & (x_d.i0v | x_d.csrwen | debug_valid_x)), .din(i0_result_x[31:0]), .dout(i0_result_r_raw[31:0]));
1414 :
1415 : // correct lsu load data - don't use for bypass, do pass down the pipe
1416 : assign i0_result_corr_r[31:0] = (r_d.i0v & r_d.i0load) ? lsu_result_corr_r[31:0] : i0_result_r_raw[31:0];
1417 :
1418 :
1419 : rvdffe #(12) e1brpcff (.*, .en(i0_x_data_en), .din(last_br_immed_d[12:1] ), .dout(last_br_immed_x[12:1]));
1420 :
1421 :
1422 :
1423 : assign i0_wb_en = i0_wb_data_en;
1424 :
1425 : assign i0_inst_wb_in[31:0] = i0_inst_r[31:0];
1426 : assign i0_inst_d[31:0] = (dec_i0_pc4_d) ? i0[31:0] : {16'b0, ifu_i0_cinst[15:0]};
1427 :
1428 :
1429 : assign trace_enable = ~dec_tlu_trace_disable;
1430 :
1431 :
1432 : rvdffe #(.WIDTH(5),.OVERRIDE(1)) i0rdff (.*, .en(i0_div_decode_d), .din(i0r.rd[4:0]), .dout(div_waddr_wb[4:0]));
1433 :
1434 : rvdffe #(32) i0xinstff (.*, .en(i0_x_data_en & trace_enable), .din(i0_inst_d[31:0]), .dout(i0_inst_x[31:0]));
1435 : rvdffe #(32) i0cinstff (.*, .en(i0_r_data_en & trace_enable), .din(i0_inst_x[31:0]), .dout(i0_inst_r[31:0]));
1436 :
1437 : rvdffe #(32) i0wbinstff (.*, .en(i0_wb_en & trace_enable), .din(i0_inst_wb_in[31:0]), .dout(i0_inst_wb[31:0]));
1438 : rvdffe #(31) i0wbpcff (.*, .en(i0_wb_en & trace_enable), .din(dec_tlu_i0_pc_r[31:1]), .dout( i0_pc_wb[31:1]));
1439 :
1440 : assign dec_i0_inst_wb[31:0] = i0_inst_wb[31:0];
1441 : assign dec_i0_pc_wb[31:1] = i0_pc_wb[31:1];
1442 :
1443 :
1444 :
1445 : rvdffpcie #(31) i0_pc_r_ff (.*, .en(i0_r_data_en), .din(exu_i0_pc_x[31:1]), .dout(dec_i0_pc_r[31:1]));
1446 :
1447 : assign dec_tlu_i0_pc_r[31:1] = dec_i0_pc_r[31:1];
1448 :
1449 :
1450 : rvbradder ibradder_correct (
1451 : .pc(exu_i0_pc_x[31:1]),
1452 : .offset(last_br_immed_x[12:1]),
1453 : .dout(pred_correct_npc_x[31:1]));
1454 :
1455 :
1456 :
1457 : // add nonblock load rs1/rs2 bypass cases
1458 :
1459 : assign i0_rs1_nonblock_load_bypass_en_d = dec_i0_rs1_en_d & dec_nonblock_load_wen & (dec_nonblock_load_waddr[4:0] == i0r.rs1[4:0]);
1460 :
1461 : assign i0_rs2_nonblock_load_bypass_en_d = dec_i0_rs2_en_d & dec_nonblock_load_wen & (dec_nonblock_load_waddr[4:0] == i0r.rs2[4:0]);
1462 :
1463 :
1464 :
1465 : // bit 2 is priority match, bit 0 lowest priority, i0_x, i0_r
1466 :
1467 : assign i0_rs1bypass[2] = i0_rs1_depth_d[0] & (i0_rs1_class_d.alu | i0_rs1_class_d.mul );
1468 : assign i0_rs1bypass[1] = i0_rs1_depth_d[0] & ( i0_rs1_class_d.load);
1469 : assign i0_rs1bypass[0] = i0_rs1_depth_d[1] & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load);
1470 :
1471 : assign i0_rs2bypass[2] = i0_rs2_depth_d[0] & (i0_rs2_class_d.alu | i0_rs2_class_d.mul );
1472 : assign i0_rs2bypass[1] = i0_rs2_depth_d[0] & ( i0_rs2_class_d.load);
1473 : assign i0_rs2bypass[0] = i0_rs2_depth_d[1] & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load);
1474 :
1475 :
1476 : assign dec_i0_rs1_bypass_en_d[3] = i0_rs1_nonblock_load_bypass_en_d & ~i0_rs1bypass[0] & ~i0_rs1bypass[1] & ~i0_rs1bypass[2];
1477 : assign dec_i0_rs1_bypass_en_d[2] = i0_rs1bypass[2];
1478 : assign dec_i0_rs1_bypass_en_d[1] = i0_rs1bypass[1];
1479 : assign dec_i0_rs1_bypass_en_d[0] = i0_rs1bypass[0];
1480 :
1481 : assign dec_i0_rs2_bypass_en_d[3] = i0_rs2_nonblock_load_bypass_en_d & ~i0_rs2bypass[0] & ~i0_rs2bypass[1] & ~i0_rs2bypass[2];
1482 : assign dec_i0_rs2_bypass_en_d[2] = i0_rs2bypass[2];
1483 : assign dec_i0_rs2_bypass_en_d[1] = i0_rs2bypass[1];
1484 : assign dec_i0_rs2_bypass_en_d[0] = i0_rs2bypass[0];
1485 :
1486 :
1487 : assign dec_i0_result_r[31:0] = i0_result_r[31:0];
1488 :
1489 :
1490 : endmodule // el2_dec_decode_ctl
1491 :
1492 : // file "decode" is human readable file that has all of the instruction decodes
1493 : // defined and is part of git repo. Modify this file as needed.
1494 : //
1495 : // The tools needed are "coredecode", "addasign" and "espresso". The first two
1496 : // can be found in this repo under /tools. Espresso can be found in another
1497 : // repo (https://github.com/chipsalliance/espresso).
1498 : // IMPORTANT: use Espresso v2.4 (git tag v2.4)
1499 : //
1500 : // To generate instruction decoding equations do:
1501 : // 1) coredecode -in decode > coredecode.e
1502 : // 2) espresso -Dso -oeqntott < coredecode.e | addassign -pre out. > equations
1503 : // 3) copy-paste assignments from the file "equations" and replace ones below.
1504 : //
1505 : // To generate instruction legality check equation do:
1506 : // 1) coredecode -in decode -legal > legal.e
1507 : // 2) espresso -Dso -oeqntott < legal.e | addassign -pre out. > legal
1508 : // 3) copy-paste assignment from the file "legal" and replace the one below.
1509 :
1510 : module el2_dec_dec_ctl
1511 : import el2_pkg::*;
1512 : (
1513 468420 : input logic [31:0] inst,
1514 7440 : output el2_dec_pkt_t out
1515 : );
1516 :
1517 468420 : logic [31:0] i;
1518 :
1519 : assign i[31:0] = inst[31:0];
1520 :
1521 : assign out.alu = (i[30]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[5]&i[4]) | (i[30]
1522 : &!i[27]&!i[24]&i[4]) | (!i[30]&!i[25]&i[13]&i[12]) | (!i[29]&!i[27]
1523 : &!i[5]&i[4]) | (i[27]&i[25]&i[14]&i[4]) | (!i[29]&!i[25]&!i[13]&!i[12]
1524 : &i[4]) | (i[29]&i[27]&!i[14]&i[12]&i[4]) | (!i[27]&i[14]&!i[5]&i[4]) | (
1525 : i[30]&!i[29]&!i[13]&i[4]) | (!i[27]&!i[25]&i[5]&i[4]) | (i[13]&!i[5]
1526 : &i[4]) | (i[6]) | (!i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]&i[20]&!i[5]
1527 : &i[4]) | (i[2]) | (!i[12]&!i[5]&i[4]);
1528 :
1529 : assign out.rs1 = (!i[13]&i[11]&!i[2]) | (!i[13]&i[10]&!i[2]) | (i[19]&i[13]&!i[2]) | (
1530 : !i[13]&i[9]&!i[2]) | (i[18]&i[13]&!i[2]) | (!i[13]&i[8]&!i[2]) | (
1531 : i[17]&i[13]&!i[2]) | (!i[13]&i[7]&!i[2]) | (i[16]&i[13]&!i[2]) | (
1532 : i[15]&i[13]&!i[2]) | (!i[4]&!i[2]) | (!i[14]&!i[13]&i[6]&!i[3]) | (
1533 : !i[6]&!i[2]);
1534 :
1535 : assign out.rs2 = (i[5] & !i[4] & !i[2]) | (!i[6] & i[5] & !i[2]);
1536 :
1537 : assign out.imm12 = (!i[4]&!i[3]&i[2]) | (i[13]&!i[5]&i[4]&!i[2]) | (!i[13]&!i[12]
1538 : &i[6]&i[4]) | (!i[12]&!i[5]&i[4]&!i[2]);
1539 :
1540 : assign out.rd = (!i[5] & !i[2]) | (i[5] & i[2]) | (i[4]);
1541 :
1542 : assign out.shimm5 = (!i[29]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[13]&i[12]
1543 : &!i[5]&i[4]&!i[2]) | (i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1544 :
1545 : assign out.imm20 = (i[5] & i[3]) | (i[4] & i[2]);
1546 :
1547 : assign out.pc = (!i[5] & !i[3] & i[2]) | (i[5] & i[3]);
1548 :
1549 : assign out.load = (!i[5] & !i[4] & !i[2]);
1550 :
1551 : assign out.store = (!i[6] & i[5] & !i[4]);
1552 :
1553 : assign out.lsu = (!i[6] & !i[4] & !i[2]);
1554 :
1555 : assign out.add = (!i[14]&!i[13]&!i[12]&!i[5]&i[4]) | (!i[5]&!i[3]&i[2]) | (!i[30]
1556 : &!i[25]&!i[14]&!i[13]&!i[12]&!i[6]&i[4]&!i[2]);
1557 :
1558 : assign out.sub = (i[30]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[29]&!i[25]&!i[14]
1559 : &i[13]&!i[6]&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]) | (
1560 : !i[14]&i[13]&!i[5]&i[4]&!i[2]) | (i[6]&!i[4]&!i[2]);
1561 :
1562 : assign out.land = (!i[27]&!i[25]&i[14]&i[13]&i[12]&!i[6]&!i[2]) | (i[14]&i[13]&i[12]
1563 : &!i[5]&!i[2]);
1564 :
1565 : assign out.lor = (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) | (!i[6]&i[3]) | (
1566 : i[5]&i[4]&i[2]) | (!i[13]&!i[12]&i[6]&i[4]) | (i[14]&i[13]&!i[12]
1567 : &!i[5]&!i[2]);
1568 :
1569 : assign out.lxor = (!i[29]&!i[27]&!i[25]&i[14]&!i[13]&!i[12]&i[4]&!i[2]) | (i[14]
1570 : &!i[13]&!i[12]&!i[5]&i[4]&!i[2]);
1571 :
1572 : assign out.sll = (!i[29] & !i[27] & !i[25] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1573 :
1574 : assign out.sra = (i[30] & !i[29] & !i[27] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1575 :
1576 : assign out.srl = (!i[30] & !i[27] & !i[25] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1577 :
1578 : assign out.slt = (!i[29]&!i[25]&!i[14]&i[13]&!i[6]&i[4]&!i[2]) | (!i[14]&i[13]&!i[5]
1579 : &i[4]&!i[2]);
1580 :
1581 : assign out.unsign = (!i[14]&i[13]&i[12]&!i[5]&!i[2]) | (i[13]&i[6]&!i[4]&!i[2]) | (
1582 : i[14]&!i[5]&!i[4]) | (!i[25]&!i[14]&i[13]&i[12]&!i[6]&!i[2]) | (
1583 : i[25]&i[14]&i[12]&!i[6]&i[5]&!i[2]);
1584 :
1585 : assign out.condbr = (i[6] & !i[4] & !i[2]);
1586 :
1587 : assign out.beq = (!i[14] & !i[12] & i[6] & !i[4] & !i[2]);
1588 :
1589 : assign out.bne = (!i[14] & i[12] & i[6] & !i[4] & !i[2]);
1590 :
1591 : assign out.bge = (i[14] & i[12] & i[5] & !i[4] & !i[2]);
1592 :
1593 : assign out.blt = (i[14] & !i[12] & i[5] & !i[4] & !i[2]);
1594 :
1595 : assign out.jal = (i[6] & i[2]);
1596 :
1597 : assign out.by = (!i[13] & !i[12] & !i[6] & !i[4] & !i[2]);
1598 :
1599 : assign out.half = (i[12] & !i[6] & !i[4] & !i[2]);
1600 :
1601 : assign out.word = (i[13] & !i[6] & !i[4]);
1602 :
1603 : assign out.csr_read = (i[13]&i[6]&i[4]) | (i[7]&i[6]&i[4]) | (i[8]&i[6]&i[4]) | (
1604 : i[9]&i[6]&i[4]) | (i[10]&i[6]&i[4]) | (i[11]&i[6]&i[4]);
1605 :
1606 : assign out.csr_clr = (i[15]&i[13]&i[12]&i[6]&i[4]) | (i[16]&i[13]&i[12]&i[6]&i[4]) | (
1607 : i[17]&i[13]&i[12]&i[6]&i[4]) | (i[18]&i[13]&i[12]&i[6]&i[4]) | (
1608 : i[19]&i[13]&i[12]&i[6]&i[4]);
1609 :
1610 : assign out.csr_set = (i[15]&!i[12]&i[6]&i[4]) | (i[16]&!i[12]&i[6]&i[4]) | (i[17]
1611 : &!i[12]&i[6]&i[4]) | (i[18]&!i[12]&i[6]&i[4]) | (i[19]&!i[12]&i[6]
1612 : &i[4]);
1613 :
1614 : assign out.csr_write = (!i[13] & i[12] & i[6] & i[4]);
1615 :
1616 : assign out.csr_imm = (i[14]&!i[13]&i[6]&i[4]) | (i[15]&i[14]&i[6]&i[4]) | (i[16]
1617 : &i[14]&i[6]&i[4]) | (i[17]&i[14]&i[6]&i[4]) | (i[18]&i[14]&i[6]&i[4]) | (
1618 : i[19]&i[14]&i[6]&i[4]);
1619 :
1620 : assign out.presync = (!i[5]&i[3]) | (!i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&i[4]) | (
1621 : !i[13]&i[9]&i[6]&i[4]) | (!i[13]&i[10]&i[6]&i[4]) | (!i[13]&i[11]
1622 : &i[6]&i[4]) | (i[15]&i[13]&i[6]&i[4]) | (i[16]&i[13]&i[6]&i[4]) | (
1623 : i[17]&i[13]&i[6]&i[4]) | (i[18]&i[13]&i[6]&i[4]) | (i[19]&i[13]&i[6]
1624 : &i[4]);
1625 :
1626 : assign out.postsync = (!i[22]&!i[13]&!i[12]&i[6]&i[4]) | (i[12]&!i[5]&i[3]) | (
1627 : !i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&i[4]) | (!i[13]&i[9]&i[6]
1628 : &i[4]) | (!i[13]&i[10]&i[6]&i[4]) | (!i[13]&i[11]&i[6]&i[4]) | (
1629 : i[15]&i[13]&i[6]&i[4]) | (i[16]&i[13]&i[6]&i[4]) | (i[17]&i[13]&i[6]
1630 : &i[4]) | (i[18]&i[13]&i[6]&i[4]) | (i[19]&i[13]&i[6]&i[4]);
1631 :
1632 : assign out.ebreak = (!i[22] & i[20] & !i[13] & !i[12] & i[6] & i[4]);
1633 :
1634 : assign out.ecall = (!i[21] & !i[20] & !i[13] & !i[12] & i[6] & i[4]);
1635 :
1636 : assign out.mret = (i[29] & !i[13] & !i[12] & i[6] & i[4]);
1637 :
1638 : assign out.mul = (i[29]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30]
1639 : &i[27]&i[13]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[23]&!i[20]
1640 : &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[21]&i[20]
1641 : &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&i[24]&i[21]
1642 : &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[24]&!i[22]
1643 : &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (!i[30]&i[29]&i[23]&i[14]
1644 : &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30]&i[29]&i[27]&i[22]&i[14]
1645 : &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[25]&i[13]&!i[12]&!i[6]
1646 : &i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6]
1647 : &i[4]&!i[2]) | (i[25]&!i[14]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27]
1648 : &i[14]&!i[6]&i[5]&!i[2]);
1649 :
1650 : assign out.rs1_sign = (!i[27]&i[25]&!i[14]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (
1651 : !i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
1652 :
1653 : assign out.rs2_sign = (!i[27] & i[25] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1654 :
1655 : assign out.low = (i[25] & !i[14] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);
1656 :
1657 : assign out.div = (!i[27] & i[25] & i[14] & !i[6] & i[5] & !i[2]);
1658 :
1659 : assign out.rem = (!i[27] & i[25] & i[14] & i[13] & !i[6] & i[5] & !i[2]);
1660 :
1661 : assign out.fence = (!i[5] & i[3]);
1662 :
1663 : assign out.fence_i = (i[12] & !i[5] & i[3]);
1664 :
1665 : assign out.clz = (i[29]&!i[27]&!i[24]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]
1666 : &i[4]&!i[2]);
1667 :
1668 : assign out.ctz = (i[29]&!i[27]&!i[24]&!i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]
1669 : &!i[2]);
1670 :
1671 : assign out.cpop = (i[29]&!i[27]&!i[24]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1672 :
1673 : assign out.sext_b = (i[29]&!i[27]&i[22]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1674 :
1675 : assign out.sext_h = (i[29]&!i[27]&i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1676 :
1677 : assign out.min = (i[27] & i[25] & i[14] & !i[13] & !i[6] & i[5] & !i[2]);
1678 :
1679 : assign out.max = (i[27] & i[25] & i[14] & i[13] & !i[6] & i[5] & !i[2]);
1680 :
1681 : assign out.pack = (!i[30] & !i[29] & i[27] & !i[25] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);
1682 :
1683 : assign out.packu = (i[30] & i[27] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);
1684 :
1685 : assign out.packh = (!i[30] & i[27] & !i[25] & i[13] & i[12] & !i[6] & i[5] & !i[2]);
1686 :
1687 : assign out.rol = (i[29] & !i[27] & !i[14] & i[12] & !i[6] & i[5] & i[4] & !i[2]);
1688 :
1689 : assign out.ror = (i[29] & !i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1690 :
1691 : assign out.zbb = (!i[30]&!i[29]&i[27]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[13]
1692 : &!i[12]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&!i[24]&!i[13]&i[12]&!i[5]
1693 : &i[4]&!i[2]) | (i[29]&!i[27]&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (
1694 : i[30]&!i[27]&i[14]&!i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13]
1695 : &!i[6]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | (
1696 : !i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]&i[20]&i[14]&!i[13]&i[12]&!i[5]
1697 : &i[4]&!i[2]) | (i[30]&i[29]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]
1698 : &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]);
1699 :
1700 : assign out.bset = (!i[30] & i[29] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1701 :
1702 : assign out.bclr = (i[30] & !i[29] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1703 :
1704 : assign out.binv = (i[30] & i[29] & i[27] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1705 :
1706 : assign out.bext = (i[30] & !i[29] & i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1707 :
1708 : assign out.zbs = (i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]) | (i[30]&!i[29]
1709 : &i[27]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
1710 :
1711 : assign out.bcompress = (!i[30]&!i[29]&i[27]&!i[25]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]);
1712 :
1713 : assign out.bdecompress = (i[30] & i[27] & i[13] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);
1714 :
1715 : assign out.zbe = (i[30]&i[27]&i[14]&i[13]&!i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&i[27]
1716 : &!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]
1717 : &!i[12]&!i[6]&i[5]&i[4]&!i[2]);
1718 :
1719 : assign out.clmul = (i[27] & i[25] & !i[14] & !i[13] & !i[6] & i[5] & i[4] & !i[2]);
1720 :
1721 : assign out.clmulh = (i[27] & !i[14] & i[13] & i[12] & !i[6] & i[5] & !i[2]);
1722 :
1723 : assign out.clmulr = (i[27] & i[25] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);
1724 :
1725 : assign out.zbc = (i[27] & i[25] & !i[14] & !i[6] & i[5] & i[4] & !i[2]);
1726 :
1727 : assign out.grev = (i[30] & i[29] & i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1728 :
1729 : assign out.gorc = (!i[30] & i[29] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1730 :
1731 : assign out.shfl = (!i[30]&!i[29]&i[27]&!i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
1732 :
1733 : assign out.unshfl = (!i[30]&!i[29]&i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
1734 :
1735 : assign out.xperm_n = (i[29] & i[27] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);
1736 :
1737 : assign out.xperm_b = (i[29] & i[27] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);
1738 :
1739 : assign out.xperm_h = (i[29] & i[27] & i[14] & i[13] & !i[6] & i[5] & !i[2]);
1740 :
1741 : assign out.zbp = (i[30]&!i[27]&!i[14]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[30]&i[27]
1742 : &!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13]&!i[6]
1743 : &i[5]&i[4]&!i[2]) | (i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (
1744 : i[30]&i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[12]&!i[6]
1745 : &i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6]
1746 : &i[4]&!i[2]) | (i[29]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
1747 :
1748 : assign out.crc32_b = (i[29]&!i[27]&i[24]&!i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]
1749 : &!i[5]&i[4]&!i[2]);
1750 :
1751 : assign out.crc32_h = (i[29]&!i[27]&i[24]&!i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]
1752 : &!i[2]);
1753 :
1754 : assign out.crc32_w = (i[29]&!i[27]&i[24]&!i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]
1755 : &!i[2]);
1756 :
1757 : assign out.crc32c_b = (i[29]&!i[27]&i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]
1758 : &i[4]&!i[2]);
1759 :
1760 : assign out.crc32c_h = (i[29]&!i[27]&i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1761 :
1762 : assign out.crc32c_w = (i[29]&!i[27]&i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1763 :
1764 : assign out.zbr = (i[29] & !i[27] & i[24] & !i[14] & !i[13] & i[12] & !i[5] & i[4] & !i[2]);
1765 :
1766 : assign out.bfp = (i[30] & i[27] & i[13] & i[12] & !i[6] & i[5] & !i[2]);
1767 :
1768 : assign out.zbf = (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (
1769 : i[27]&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]);
1770 :
1771 : assign out.sh1add = (i[29] & !i[27] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);
1772 :
1773 : assign out.sh2add = (i[29] & !i[27] & i[14] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);
1774 :
1775 : assign out.sh3add = (i[29] & !i[27] & i[14] & i[13] & !i[6] & i[5] & !i[2]);
1776 :
1777 : assign out.zba = (i[29] & !i[27] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);
1778 :
1779 : assign out.pm_alu = (i[28]&i[20]&!i[13]&!i[12]&i[4]) | (!i[30]&!i[29]&!i[27]&!i[25]
1780 : &!i[6]&i[4]) | (!i[29]&!i[27]&!i[25]&!i[13]&i[12]&!i[6]&i[4]) | (
1781 : !i[29]&!i[27]&!i[25]&!i[14]&!i[6]&i[4]) | (i[13]&!i[5]&i[4]) | (i[4]
1782 : &i[2]) | (!i[12]&!i[5]&i[4]);
1783 :
1784 :
1785 : assign out.legal = (!i[31]&!i[30]&i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]
1786 : &!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]
1787 : &!i[10]&!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (
1788 : !i[31]&!i[30]&!i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&i[22]
1789 : &!i[21]&i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10]
1790 : &!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]
1791 : &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]
1792 : &!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10]&!i[9]&!i[8]
1793 : &!i[7]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]
1794 : &!i[26]&!i[25]&i[24]&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (
1795 : !i[31]&i[30]&i[29]&!i[28]&!i[26]&!i[25]&i[24]&!i[22]&!i[21]&!i[6]
1796 : &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]&!i[26]
1797 : &!i[25]&!i[23]&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (
1798 : !i[31]&i[30]&i[29]&!i[28]&!i[26]&!i[25]&!i[24]&!i[23]&!i[21]&!i[6]
1799 : &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[26]
1800 : &i[25]&i[13]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[28]&i[27]&!i[26]
1801 : &!i[25]&!i[24]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]
1802 : &i[29]&!i[28]&!i[26]&!i[25]&i[13]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (
1803 : !i[31]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[13]&!i[12]&!i[6]&i[4]
1804 : &!i[3]&i[1]&i[0]) | (!i[31]&i[30]&!i[28]&!i[26]&!i[25]&i[14]&!i[6]
1805 : &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[26]
1806 : &!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]
1807 : &!i[28]&!i[27]&!i[26]&!i[25]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]
1808 : &i[30]&i[29]&!i[28]&!i[26]&!i[25]&!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2]
1809 : &i[1]&i[0]) | (!i[31]&i[30]&!i[28]&i[27]&!i[26]&!i[25]&!i[13]&i[12]
1810 : &!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[29]&!i[28]&!i[26]&!i[25]
1811 : &i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&i[27]
1812 : &!i[26]&!i[25]&!i[13]&i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]
1813 : &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | (
1814 : !i[31]&!i[30]&!i[29]&!i[28]&!i[26]&i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1]
1815 : &i[0]) | (!i[14]&!i[13]&!i[12]&i[6]&i[5]&!i[4]&!i[3]&i[1]&i[0]) | (
1816 : i[14]&i[6]&i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&!i[13]&i[5]
1817 : &!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[12]&!i[6]&!i[5]&i[4]&!i[3]&i[1]
1818 : &i[0]) | (!i[13]&i[12]&i[6]&i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[13]&i[6]
1819 : &i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&!i[29]&!i[28]&!i[14]
1820 : &!i[13]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]
1821 : &!i[26]&!i[25]&i[14]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[14]
1822 : &!i[13]&i[12]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (i[6]&i[5]
1823 : &!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[14]&!i[12]&!i[6]&!i[4]&!i[3]&!i[2]
1824 : &i[1]&i[0]) | (!i[13]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (
1825 : i[13]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[6]&i[4]&!i[3]&i[2]&i[1]
1826 : &i[0]);
1827 :
1828 : endmodule // el2_dec_dec_ctl
|
