Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 :
16 :
17 : module el2_dec_decode_ctl
18 : import el2_pkg::*;
19 : #(
20 : `include "el2_param.vh"
21 : )
22 : (
23 0 : input logic dec_tlu_trace_disable,
24 2378 : input logic dec_debug_valid_d,
25 :
26 0 : input logic dec_tlu_flush_extint, // Flush external interrupt
27 :
28 0 : input logic dec_tlu_force_halt, // invalidate nonblock load cam on a force halt event
29 :
30 0 : output logic dec_extint_stall, // Stall from external interrupt
31 :
32 1428046 : input logic [15:0] ifu_i0_cinst, // 16b compressed instruction
33 579000 : output logic [31:0] dec_i0_inst_wb, // 32b instruction at wb+1 for trace encoder
34 339 : output logic [31:1] dec_i0_pc_wb, // 31b pc at wb+1 for trace encoder
35 :
36 :
37 881246 : input logic lsu_nonblock_load_valid_m, // valid nonblock load at m
38 504987 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m, // -> corresponding tag
39 0 : input logic lsu_nonblock_load_inv_r, // invalidate request for nonblock load r
40 504984 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r, // -> corresponding tag
41 920472 : input logic lsu_nonblock_load_data_valid, // valid nonblock load data back
42 2 : input logic lsu_nonblock_load_data_error, // nonblock load bus error
43 36572 : input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag, // -> corresponding tag
44 :
45 :
46 0 : input logic [3:0] dec_i0_trigger_match_d, // i0 decode trigger matches
47 :
48 2 : input logic dec_tlu_wr_pause_r, // pause instruction at r
49 0 : input logic dec_tlu_pipelining_disable, // pipeline disable - presync, i0 decode only
50 :
51 0 : input logic [3:0] lsu_trigger_match_m, // lsu trigger matches
52 :
53 48802 : input logic lsu_pmu_misaligned_m, // perf mon: load/store misalign
54 122 : input logic dec_tlu_debug_stall, // debug stall decode
55 2 : input logic dec_tlu_flush_leak_one_r, // leak1 instruction
56 :
57 0 : input logic dec_debug_fence_d, // debug fence instruction
58 :
59 578 : input logic [1:0] dbg_cmd_wrdata, // disambiguate fence, fence_i
60 :
61 208 : input logic dec_i0_icaf_d, // icache access fault
62 86 : input logic dec_i0_icaf_second_d, // i0 instruction access fault on second 2B of 4B inst
63 274 : input logic [1:0] dec_i0_icaf_type_d, // i0 instruction access fault type
64 :
65 2 : input logic dec_i0_dbecc_d, // icache/iccm double-bit error
66 :
67 206047 : input el2_br_pkt_t dec_i0_brp, // branch packet
68 651101 : input logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index, // i0 branch index
69 630514 : input logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr, // BP FGHR
70 21223 : input logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag, // BP tag
71 0 : input logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index, // Fully associt btb index
72 :
73 1346584 : input logic lsu_idle_any, // lsu idle: if fence instr & ~lsu_idle then stall decode
74 :
75 48822 : input logic lsu_load_stall_any, // stall any load at decode
76 59146 : input logic lsu_store_stall_any, // stall any store at decode
77 0 : input logic dma_dccm_stall_any, // stall any load/store at decode
78 :
79 156860 : input logic exu_div_wren, // nonblocking divide write enable to GPR.
80 :
81 29690 : input logic dec_tlu_i0_kill_writeb_wb, // I0 is flushed, don't writeback any results to arch state
82 59234 : input logic dec_tlu_flush_lower_wb, // trap lower flush
83 29690 : input logic dec_tlu_i0_kill_writeb_r, // I0 is flushed, don't writeback any results to arch state
84 59234 : input logic dec_tlu_flush_lower_r, // trap lower flush
85 2 : input logic dec_tlu_flush_pause_r, // don't clear pause state on initial lower flush
86 534 : input logic dec_tlu_presync_d, // CSR read needs to be presync'd
87 20525 : input logic dec_tlu_postsync_d, // CSR ops that need to be postsync'd
88 :
89 5773026 : input logic dec_i0_pc4_d, // inst is 4B inst else 2B
90 :
91 9105 : input logic [31:0] dec_csr_rddata_d, // csr read data at wb
92 86179 : input logic dec_csr_legal_d, // csr indicates legal operation
93 :
94 3978 : input logic [31:0] exu_csr_rs1_x, // rs1 for csr instr
95 :
96 45313 : input logic [31:0] lsu_result_m, // load result
97 36052 : input logic [31:0] lsu_result_corr_r, // load result - corrected data for writing gpr's, not for bypassing
98 :
99 673895 : input logic exu_flush_final, // lower flush or i0 flush at X or D
100 :
101 339 : input logic [31:1] exu_i0_pc_x, // pcs at e1
102 :
103 468714 : input logic [31:0] dec_i0_instr_d, // inst at decode
104 :
105 6016113 : input logic dec_ib0_valid_d, // inst valid at decode
106 :
107 614631 : input logic [31:0] exu_i0_result_x, // from primary alu's
108 :
109 69830461 : input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
110 69830461 : input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
111 69830461 : input logic free_l2clk, // Clock always. Through one clock header. For flops with second header built in.
112 :
113 2 : input logic clk_override, // Override non-functional clock gating
114 338 : input logic rst_l, // Flop reset
115 :
116 :
117 :
118 5138059 : output logic dec_i0_rs1_en_d, // rs1 enable at decode
119 3571415 : output logic dec_i0_rs2_en_d, // rs2 enable at decode
120 :
121 2496807 : output logic [4:0] dec_i0_rs1_d, // rs1 logical source
122 4217340 : output logic [4:0] dec_i0_rs2_d, // rs2 logical source
123 :
124 2171149 : output logic [31:0] dec_i0_immed_d, // 32b immediate data decode
125 :
126 :
127 123424 : output logic [12:1] dec_i0_br_immed_d, // 12b branch immediate
128 :
129 1460 : output el2_alu_pkt_t i0_ap, // alu packets
130 :
131 6199021 : output logic dec_i0_decode_d, // i0 decode
132 :
133 5410176 : output logic dec_i0_alu_decode_d, // decode to D-stage alu
134 3885446 : output logic dec_i0_branch_d, // Branch in D-stage
135 :
136 2809304 : output logic [4:0] dec_i0_waddr_r, // i0 logical source to write to gpr's
137 5729108 : output logic dec_i0_wen_r, // i0 write enable
138 314095 : output logic [31:0] dec_i0_wdata_r, // i0 write data
139 :
140 555531 : output logic dec_i0_select_pc_d, // i0 select pc for rs1 - branches
141 :
142 80550 : output logic [3:0] dec_i0_rs1_bypass_en_d, // i0 rs1 bypass enable
143 8620 : output logic [3:0] dec_i0_rs2_bypass_en_d, // i0 rs2 bypass enable
144 314095 : output logic [31:0] dec_i0_result_r, // Result R-stage
145 :
146 623733 : output el2_lsu_pkt_t lsu_p, // load/store packet
147 5492615 : output logic dec_qual_lsu_d, // LSU instruction at D. Use to quiet LSU operands
148 :
149 0 : output el2_mul_pkt_t mul_p, // multiply packet
150 :
151 78134 : output el2_div_pkt_t div_p, // divide packet
152 21351 : output logic [4:0] div_waddr_wb, // DIV write address to GPR
153 2628 : output logic dec_div_cancel, // cancel the divide operation
154 :
155 2283261 : output logic dec_lsu_valid_raw_d,
156 270454 : output logic [11:0] dec_lsu_offset_d,
157 :
158 77218 : output logic dec_csr_ren_d, // valid csr decode
159 42341 : output logic dec_csr_wen_unq_d, // valid csr with write - for csr legal
160 86301 : output logic dec_csr_any_unq_d, // valid csr - for csr legal
161 984 : output logic [11:0] dec_csr_rdaddr_d, // read address for csr
162 42176 : output logic dec_csr_wen_r, // csr write enable at r
163 1566569 : output logic [11:0] dec_csr_rdaddr_r, // read address for csr
164 536 : output logic [11:0] dec_csr_wraddr_r, // write address for csr
165 1686 : output logic [31:0] dec_csr_wrdata_r, // csr write data at r
166 1424 : output logic dec_csr_stall_int_ff, // csr is mie/mstatus
167 :
168 6198377 : output dec_tlu_i0_valid_r, // i0 valid inst at c
169 :
170 280 : output el2_trap_pkt_t dec_tlu_packet_r, // trap packet
171 :
172 339 : output logic [31:1] dec_tlu_i0_pc_r, // i0 trap pc
173 :
174 18 : output logic [31:0] dec_illegal_inst, // illegal inst
175 138775 : output logic [31:1] pred_correct_npc_x, // npc e2 if the prediction is correct
176 :
177 506276 : output el2_predict_pkt_t dec_i0_predict_p_d, // i0 predict packet decode
178 630514 : output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d, // i0 predict fghr
179 651101 : output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d, // i0 predict index
180 21223 : output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d, // i0_predict branch tag
181 :
182 0 : output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index, // Fully associt btb error index
183 :
184 6198405 : output logic [1:0] dec_data_en, // clock-gating logic
185 5993280 : output logic [1:0] dec_ctl_en,
186 :
187 6199021 : output logic dec_pmu_instr_decoded, // number of instructions decode this cycle encoded
188 237922 : output logic dec_pmu_decode_stall, // decode is stalled
189 266 : output logic dec_pmu_presync_stall, // decode has presync stall
190 14672 : output logic dec_pmu_postsync_stall, // decode has postsync stall
191 :
192 920460 : output logic dec_nonblock_load_wen, // write enable for nonblock load
193 368828 : output logic [4:0] dec_nonblock_load_waddr, // logical write addr for nonblock load
194 2 : output logic dec_pause_state, // core in pause state
195 2 : output logic dec_pause_state_cg, // pause state for clock-gating
196 :
197 159488 : output logic dec_div_active, // non-block divide is active
198 :
199 : // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
200 : /*verilator coverage_off*/
201 : input logic scan_mode
202 : /*verilator coverage_on*/
203 : );
204 :
205 :
206 :
207 :
208 13730 : el2_dec_pkt_t i0_dp_raw, i0_dp;
209 :
210 468714 : logic [31:0] i0;
211 6016113 : logic i0_valid_d;
212 :
213 314095 : logic [31:0] i0_result_r;
214 :
215 32306 : logic [2:0] i0_rs1bypass, i0_rs2bypass;
216 :
217 443200 : logic i0_jalimm20;
218 438399 : logic i0_uiimm20;
219 :
220 2287125 : logic lsu_decode_d;
221 2171149 : logic [31:0] i0_immed_d;
222 70110 : logic i0_presync;
223 120301 : logic i0_postsync;
224 :
225 110918 : logic postsync_stall;
226 110918 : logic ps_stall;
227 :
228 5993284 : logic prior_inflight, prior_inflight_wb;
229 :
230 10968 : logic csr_clr_d, csr_set_d, csr_write_d;
231 :
232 7876 : logic csr_clr_x,csr_set_x,csr_write_x,csr_imm_x;
233 4282 : logic [31:0] csr_mask_x;
234 2652 : logic [31:0] write_csr_data_x;
235 2660 : logic [31:0] write_csr_data_in;
236 1326 : logic [31:0] write_csr_data;
237 33072 : logic csr_data_wen;
238 :
239 10844 : logic [4:0] csrimm_x;
240 :
241 1592 : logic [31:0] csr_rddata_x;
242 :
243 250948 : logic mul_decode_d;
244 159488 : logic div_decode_d;
245 159488 : logic div_e1_to_r;
246 2628 : logic div_flush;
247 159488 : logic div_active_in;
248 159488 : logic div_active;
249 8228 : logic i0_nonblock_div_stall;
250 1472 : logic i0_div_prior_div_stall;
251 2628 : logic nonblock_div_cancel;
252 :
253 6006301 : logic i0_legal;
254 284 : logic shift_illegal;
255 284 : logic illegal_inst_en;
256 284 : logic illegal_lockout_in, illegal_lockout;
257 6198759 : logic i0_legal_decode_d;
258 315818 : logic i0_exulegal_decode_d, i0_exudecode_d, i0_exublock_d;
259 :
260 1382304 : logic [12:1] last_br_immed_d;
261 1956863 : logic i0_rs1_depend_i0_x, i0_rs1_depend_i0_r;
262 170384 : logic i0_rs2_depend_i0_x, i0_rs2_depend_i0_r;
263 :
264 159488 : logic i0_div_decode_d;
265 0 : logic i0_load_block_d;
266 155366 : logic [1:0] i0_rs1_depth_d, i0_rs2_depth_d;
267 :
268 27422 : logic i0_load_stall_d;
269 6718 : logic i0_store_stall_d;
270 :
271 766900 : logic i0_predict_nt, i0_predict_t;
272 :
273 28576 : logic i0_notbr_error, i0_br_toffset_error;
274 396 : logic i0_ret_error;
275 38468 : logic i0_br_error;
276 38478 : logic i0_br_error_all;
277 1571409 : logic [11:0] i0_br_offset;
278 :
279 1432100 : logic [20:1] i0_pcall_imm; // predicted jal's
280 5596447 : logic i0_pcall_12b_offset;
281 122554 : logic i0_pcall_raw;
282 122884 : logic i0_pcall_case;
283 122198 : logic i0_pcall;
284 :
285 312884 : logic i0_pja_raw;
286 322126 : logic i0_pja_case;
287 311924 : logic i0_pja;
288 :
289 167546 : logic i0_pret_case;
290 167546 : logic i0_pret_raw, i0_pret;
291 :
292 106054 : logic i0_jal; // jal's that are not predicted
293 :
294 :
295 3744930 : logic i0_predict_br;
296 :
297 0 : logic store_data_bypass_d, store_data_bypass_m;
298 :
299 4226 : el2_class_pkt_t i0_rs1_class_d, i0_rs2_class_d;
300 :
301 234134 : el2_class_pkt_t i0_d_c, i0_x_c, i0_r_c;
302 :
303 :
304 5773026 : logic i0_ap_pc2, i0_ap_pc4;
305 :
306 6499453 : logic i0_rd_en_d;
307 :
308 69392 : logic load_ldst_bypass_d;
309 :
310 2 : logic leak1_i0_stall_in, leak1_i0_stall;
311 2 : logic leak1_i1_stall_in, leak1_i1_stall;
312 2 : logic leak1_mode;
313 :
314 9129 : logic i0_csr_write_only_d;
315 :
316 5993432 : logic prior_inflight_x, prior_inflight_eff;
317 86301 : logic any_csr_d;
318 :
319 9122 : logic prior_csr_write;
320 :
321 6198319 : logic [3:0] i0_pipe_en;
322 5993245 : logic i0_r_ctl_en, i0_x_ctl_en, i0_wb_ctl_en;
323 6198377 : logic i0_x_data_en, i0_r_data_en, i0_wb_data_en;
324 :
325 0 : logic debug_fence_i;
326 0 : logic debug_fence;
327 :
328 25375 : logic i0_csr_write;
329 266 : logic presync_stall;
330 :
331 210 : logic i0_instr_error;
332 210 : logic i0_icaf_d;
333 :
334 59232 : logic clear_pause;
335 2 : logic pause_state_in, pause_state;
336 2 : logic pause_stall;
337 :
338 3136159 : logic i0_brp_valid;
339 736464 : logic nonblock_load_cancel;
340 1346583 : logic lsu_idle;
341 48802 : logic lsu_pmu_misaligned_r;
342 77082 : logic csr_ren_qual_d;
343 77082 : logic csr_read_x;
344 349590 : logic i0_block_d;
345 315818 : logic i0_block_raw_d; // This is use to create the raw valid
346 110919 : logic ps_stall_in;
347 660319 : logic [31:0] i0_result_x;
348 :
349 34660 : el2_dest_pkt_t d_d, x_d, r_d, wbd;
350 34660 : el2_dest_pkt_t x_d_in, r_d_in;
351 :
352 0 : el2_trap_pkt_t d_t, x_t, x_t_in, r_t_in, r_t;
353 :
354 0 : logic [3:0] lsu_trigger_match_r;
355 :
356 339 : logic [31:1] dec_i0_pc_r;
357 :
358 42139 : logic csr_read, csr_write;
359 106054 : logic i0_br_unpred;
360 :
361 881100 : logic nonblock_load_valid_m_delay;
362 6564130 : logic i0_wen_r;
363 :
364 2 : logic tlu_wr_pause_r1;
365 2 : logic tlu_wr_pause_r2;
366 :
367 673894 : logic flush_final_r;
368 :
369 339 : logic bitmanip_zbb_legal;
370 339 : logic bitmanip_zbs_legal;
371 339 : logic bitmanip_zbe_legal;
372 339 : logic bitmanip_zbc_legal;
373 345 : logic bitmanip_zbp_legal;
374 339 : logic bitmanip_zbr_legal;
375 339 : logic bitmanip_zbf_legal;
376 339 : logic bitmanip_zba_legal;
377 339 : logic bitmanip_zbb_zbp_legal;
378 339 : logic bitmanip_zbp_zbe_zbf_legal;
379 339 : logic bitmanip_zbb_zbp_zbe_zbf_legal;
380 345 : logic bitmanip_legal;
381 :
382 0 : logic data_gate_en;
383 0 : logic data_gate_clk;
384 :
385 :
386 : localparam NBLOAD_SIZE = pt.LSU_NUM_NBLOAD;
387 : localparam NBLOAD_SIZE_MSB = int'(pt.LSU_NUM_NBLOAD)-1;
388 : localparam NBLOAD_TAG_MSB = pt.LSU_NUM_NBLOAD_WIDTH-1;
389 :
390 :
391 920474 : logic cam_write, cam_inv_reset, cam_data_reset;
392 36572 : logic [NBLOAD_TAG_MSB:0] cam_write_tag, cam_inv_reset_tag, cam_data_reset_tag;
393 5788 : logic [NBLOAD_SIZE_MSB:0] cam_wen;
394 :
395 36572 : logic [NBLOAD_TAG_MSB:0] load_data_tag;
396 6368 : logic [NBLOAD_SIZE_MSB:0] nonblock_load_write;
397 :
398 5787 : el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam;
399 5787 : el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_in;
400 5787 : el2_load_cam_pkt_t [NBLOAD_SIZE_MSB:0] cam_raw;
401 :
402 531294 : logic [4:0] nonblock_load_rd;
403 190462 : logic i0_nonblock_load_stall;
404 89248 : logic i0_nonblock_boundary_stall;
405 :
406 26928 : logic i0_rs1_nonblock_load_bypass_en_d, i0_rs2_nonblock_load_bypass_en_d;
407 :
408 881100 : logic i0_load_kill_wen_r;
409 :
410 2427 : logic found;
411 :
412 5784 : logic [NBLOAD_SIZE_MSB:0] cam_inv_reset_val, cam_data_reset_val;
413 :
414 0 : logic debug_fence_raw;
415 :
416 314095 : logic [31:0] i0_result_r_raw;
417 314095 : logic [31:0] i0_result_corr_r;
418 :
419 1140368 : logic [12:1] last_br_immed_x;
420 :
421 896716 : logic [31:0] i0_inst_d;
422 579006 : logic [31:0] i0_inst_x;
423 579005 : logic [31:0] i0_inst_r;
424 579005 : logic [31:0] i0_inst_wb_in;
425 579000 : logic [31:0] i0_inst_wb;
426 :
427 339 : logic [31:1] i0_pc_wb;
428 :
429 6198377 : logic i0_wb_en;
430 :
431 339 : logic trace_enable;
432 :
433 2378 : logic debug_valid_x;
434 :
435 2159011 : el2_inst_pkt_t i0_itype;
436 2344926 : el2_reg_pkt_t i0r;
437 :
438 :
439 : rvdffie #(8) misc1ff (.*,
440 : .clk(free_l2clk),
441 : .din( {leak1_i1_stall_in,leak1_i0_stall_in,dec_tlu_flush_extint,pause_state_in ,dec_tlu_wr_pause_r, tlu_wr_pause_r1,illegal_lockout_in,ps_stall_in}),
442 : .dout({leak1_i1_stall, leak1_i0_stall, dec_extint_stall, pause_state, tlu_wr_pause_r1,tlu_wr_pause_r2,illegal_lockout, ps_stall })
443 : );
444 :
445 : rvdffie #(8) misc2ff (.*,
446 : .clk(free_l2clk),
447 : .din( {lsu_trigger_match_m[3:0],lsu_pmu_misaligned_m,div_active_in,exu_flush_final, dec_debug_valid_d}),
448 : .dout({lsu_trigger_match_r[3:0],lsu_pmu_misaligned_r,div_active, flush_final_r, debug_valid_x})
449 : );
450 :
451 : if(pt.BTB_ENABLE==1) begin
452 : // branch prediction
453 :
454 :
455 : // in leak1_mode, ignore any predictions for i0, treat branch as if we haven't seen it before
456 : // in leak1 mode, also ignore branch errors for i0
457 : assign i0_brp_valid = dec_i0_brp.valid & ~leak1_mode & ~i0_icaf_d;
458 :
459 : assign dec_i0_predict_p_d.misp = '0;
460 : assign dec_i0_predict_p_d.ataken = '0;
461 : assign dec_i0_predict_p_d.boffset = '0;
462 :
463 : assign dec_i0_predict_p_d.pcall = i0_pcall; // don't mark as pcall if branch error
464 : assign dec_i0_predict_p_d.pja = i0_pja;
465 : assign dec_i0_predict_p_d.pret = i0_pret;
466 : assign dec_i0_predict_p_d.prett[31:1] = dec_i0_brp.prett[31:1];
467 : assign dec_i0_predict_p_d.pc4 = dec_i0_pc4_d;
468 : assign dec_i0_predict_p_d.hist[1:0] = dec_i0_brp.hist[1:0];
469 : assign dec_i0_predict_p_d.valid = i0_brp_valid & i0_legal_decode_d;
470 : assign i0_notbr_error = i0_brp_valid & ~(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw);
471 :
472 : // no toffset error for a pret
473 : assign i0_br_toffset_error = i0_brp_valid & dec_i0_brp.hist[1] & (dec_i0_brp.toffset[11:0] != i0_br_offset[11:0]) & ~i0_pret_raw;
474 : assign i0_ret_error = i0_brp_valid & (dec_i0_brp.ret ^ i0_pret_raw);
475 : assign i0_br_error = dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error;
476 : assign dec_i0_predict_p_d.br_error = i0_br_error & i0_legal_decode_d & ~leak1_mode;
477 : assign dec_i0_predict_p_d.br_start_error = dec_i0_brp.br_start_error & i0_legal_decode_d & ~leak1_mode;
478 : assign i0_predict_index_d[pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] = dec_i0_bp_index;
479 :
480 : assign i0_predict_btag_d[pt.BTB_BTAG_SIZE-1:0] = dec_i0_bp_btag[pt.BTB_BTAG_SIZE-1:0];
481 : assign i0_br_error_all = (i0_br_error | dec_i0_brp.br_start_error) & ~leak1_mode;
482 : assign dec_i0_predict_p_d.toffset[11:0] = i0_br_offset[11:0];
483 : assign i0_predict_fghr_d[pt.BHT_GHR_SIZE-1:0] = dec_i0_bp_fghr[pt.BHT_GHR_SIZE-1:0];
484 : assign dec_i0_predict_p_d.way = dec_i0_brp.way;
485 :
486 :
487 : if(pt.BTB_FULLYA) begin : genblock
488 : logic btb_error_found, btb_error_found_f;
489 : logic [$clog2(pt.BTB_SIZE)-1:0] fa_error_index_ns;
490 :
491 : assign btb_error_found = (i0_br_error_all | btb_error_found_f) & ~dec_tlu_flush_lower_r;
492 : assign fa_error_index_ns = (i0_br_error_all & ~btb_error_found_f) ? dec_i0_bp_fa_index : dec_fa_error_index;
493 :
494 : rvdff #($clog2(pt.BTB_SIZE)+1) btberrorfa_f (.*, .clk(active_clk),
495 : .din({btb_error_found, fa_error_index_ns}),
496 : .dout({btb_error_found_f, dec_fa_error_index}));
497 :
498 :
499 : end
500 : else
501 : assign dec_fa_error_index = 'b0;
502 :
503 :
504 : // end
505 : end // if (pt.BTB_ENABLE==1)
506 : else begin
507 :
508 : always_comb begin
509 : dec_i0_predict_p_d = '0;
510 : dec_i0_predict_p_d.pcall = i0_pcall; // don't mark as pcall if branch error
511 : dec_i0_predict_p_d.pja = i0_pja;
512 : dec_i0_predict_p_d.pret = i0_pret;
513 : dec_i0_predict_p_d.pc4 = dec_i0_pc4_d;
514 : end
515 :
516 : assign i0_br_error_all = '0;
517 : assign i0_predict_index_d = '0;
518 : assign i0_predict_btag_d = '0;
519 : assign i0_predict_fghr_d = '0;
520 : assign i0_brp_valid = '0;
521 : end // else: !if(pt.BTB_ENABLE==1)
522 :
523 : // on br error turn anything into a nop
524 : // on i0 instruction fetch access fault turn anything into a nop
525 : // nop => alu rs1 imm12 rd lor
526 :
527 : assign i0_icaf_d = dec_i0_icaf_d | dec_i0_dbecc_d;
528 :
529 : assign i0_instr_error = i0_icaf_d;
530 :
531 339 : always_comb begin
532 339 : i0_dp = i0_dp_raw;
533 5755422 : if (i0_br_error_all | i0_instr_error) begin
534 39880 : i0_dp = '0;
535 39880 : i0_dp.alu = 1'b1;
536 39880 : i0_dp.rs1 = 1'b1;
537 39880 : i0_dp.rs2 = 1'b1;
538 39880 : i0_dp.lor = 1'b1;
539 39880 : i0_dp.legal = 1'b1;
540 39880 : i0_dp.postsync = 1'b1;
541 : end
542 : end
543 :
544 : assign i0[31:0] = dec_i0_instr_d[31:0];
545 :
546 : assign dec_i0_select_pc_d = i0_dp.pc;
547 :
548 : // branches that can be predicted
549 :
550 : assign i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
551 :
552 : assign i0_predict_nt = ~(dec_i0_brp.hist[1] & i0_brp_valid) & i0_predict_br;
553 : assign i0_predict_t = (dec_i0_brp.hist[1] & i0_brp_valid) & i0_predict_br;
554 :
555 : assign i0_ap.add = i0_dp.add;
556 : assign i0_ap.sub = i0_dp.sub;
557 : assign i0_ap.land = i0_dp.land;
558 : assign i0_ap.lor = i0_dp.lor;
559 : assign i0_ap.lxor = i0_dp.lxor;
560 : assign i0_ap.sll = i0_dp.sll;
561 : assign i0_ap.srl = i0_dp.srl;
562 : assign i0_ap.sra = i0_dp.sra;
563 : assign i0_ap.slt = i0_dp.slt;
564 : assign i0_ap.unsign = i0_dp.unsign;
565 : assign i0_ap.beq = i0_dp.beq;
566 : assign i0_ap.bne = i0_dp.bne;
567 : assign i0_ap.blt = i0_dp.blt;
568 : assign i0_ap.bge = i0_dp.bge;
569 :
570 : assign i0_ap.clz = i0_dp.clz;
571 : assign i0_ap.ctz = i0_dp.ctz;
572 : assign i0_ap.cpop = i0_dp.cpop;
573 : assign i0_ap.sext_b = i0_dp.sext_b;
574 : assign i0_ap.sext_h = i0_dp.sext_h;
575 : assign i0_ap.sh1add = i0_dp.sh1add;
576 : assign i0_ap.sh2add = i0_dp.sh2add;
577 : assign i0_ap.sh3add = i0_dp.sh3add;
578 : assign i0_ap.zba = i0_dp.zba;
579 : assign i0_ap.min = i0_dp.min;
580 : assign i0_ap.max = i0_dp.max;
581 : assign i0_ap.pack = i0_dp.pack;
582 : assign i0_ap.packu = i0_dp.packu;
583 : assign i0_ap.packh = i0_dp.packh;
584 : assign i0_ap.rol = i0_dp.rol;
585 : assign i0_ap.ror = i0_dp.ror;
586 : assign i0_ap.grev = i0_dp.grev;
587 : assign i0_ap.gorc = i0_dp.gorc;
588 : assign i0_ap.zbb = i0_dp.zbb;
589 : assign i0_ap.bset = i0_dp.bset;
590 : assign i0_ap.bclr = i0_dp.bclr;
591 : assign i0_ap.binv = i0_dp.binv;
592 : assign i0_ap.bext = i0_dp.bext;
593 :
594 : assign i0_ap.csr_write = i0_csr_write_only_d;
595 : assign i0_ap.csr_imm = i0_dp.csr_imm;
596 : assign i0_ap.jal = i0_jal;
597 :
598 : assign i0_ap_pc2 = ~dec_i0_pc4_d;
599 : assign i0_ap_pc4 = dec_i0_pc4_d;
600 :
601 : assign i0_ap.predict_nt = i0_predict_nt;
602 : assign i0_ap.predict_t = i0_predict_t;
603 :
604 :
605 : // non block load cam logic
606 :
607 339 : always_comb begin
608 339 : found = 0;
609 339 : for (int i=0; i<NBLOAD_SIZE; i++) begin
610 10978 : if (~found) begin
611 2571731 : if (~cam[i].valid) begin
612 27579443 : cam_wen[i] = cam_write;
613 27579443 : found = 1'b1;
614 : end
615 2571731 : else begin
616 2571731 : cam_wen[i] = 0;
617 : end
618 : end
619 : else
620 178276088 : cam_wen[i] = 0;
621 : end
622 : end
623 :
624 : assign cam_write = lsu_nonblock_load_valid_m;
625 : assign cam_write_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_tag_m[NBLOAD_TAG_MSB:0];
626 :
627 : assign cam_inv_reset = lsu_nonblock_load_inv_r;
628 : assign cam_inv_reset_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0];
629 :
630 : assign cam_data_reset = lsu_nonblock_load_data_valid | lsu_nonblock_load_data_error;
631 : assign cam_data_reset_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_data_tag[NBLOAD_TAG_MSB:0];
632 :
633 : assign nonblock_load_rd[4:0] = (x_d.i0load) ? x_d.i0rd[4:0] : 5'b0; // rd data
634 :
635 :
636 : // checks
637 :
638 : `ifdef RV_ASSERT_ON
639 : assert_dec_data_valid_data_error_onehot: assert #0 ($onehot0({lsu_nonblock_load_data_valid,lsu_nonblock_load_data_error}));
640 : assert_dec_cam_inv_reset_onehot: assert #0 ($onehot0(cam_inv_reset_val[NBLOAD_SIZE_MSB:0]));
641 : assert_dec_cam_data_reset_onehot: assert #0 ($onehot0(cam_data_reset_val[NBLOAD_SIZE_MSB:0]));
642 : `endif
643 :
644 :
645 :
646 : // case of multiple loads to same dest ie. x1 ... you have to invalidate the older one
647 :
648 0 : for (genvar i=0; i<NBLOAD_SIZE; i++) begin : cam_array
649 :
650 : assign cam_inv_reset_val[i] = cam_inv_reset & (cam_inv_reset_tag[NBLOAD_TAG_MSB:0] == cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid;
651 :
652 : assign cam_data_reset_val[i] = cam_data_reset & (cam_data_reset_tag[NBLOAD_TAG_MSB:0] == cam_raw[i].tag[NBLOAD_TAG_MSB:0]) & cam_raw[i].valid;
653 :
654 1356 : always_comb begin
655 :
656 1356 : cam[i] = cam_raw[i];
657 :
658 32952789 : if (cam_data_reset_val[i])
659 472837 : cam[i].valid = 1'b0;
660 :
661 1356 : cam_in[i] = '0;
662 :
663 1756371 : if (cam_wen[i]) begin
664 1756371 : cam_in[i].valid = 1'b1;
665 1756371 : cam_in[i].wb = 1'b0;
666 1756371 : cam_in[i].tag[NBLOAD_TAG_MSB:0] = cam_write_tag[NBLOAD_TAG_MSB:0];
667 1756371 : cam_in[i].rd[4:0] = nonblock_load_rd[4:0];
668 : end
669 54176282 : else if ( (cam_inv_reset_val[i]) |
670 : (i0_wen_r & (r_d_in.i0rd[4:0] == cam[i].rd[4:0]) & cam[i].wb) )
671 89690 : cam_in[i].valid = 1'b0;
672 : else
673 235869063 : cam_in[i] = cam[i];
674 :
675 33899037 : if (nonblock_load_valid_m_delay & (lsu_nonblock_load_inv_tag_r[NBLOAD_TAG_MSB:0]==cam[i].tag[NBLOAD_TAG_MSB:0]) & cam[i].valid)
676 1418517 : cam_in[i].wb = 1'b1;
677 :
678 : // force debug halt forces cam valids to 0; highest priority
679 113042008 : if (dec_tlu_force_halt)
680 0 : cam_in[i].valid = 1'b0;
681 : end
682 :
683 :
684 : rvdffie #( $bits(el2_load_cam_pkt_t) ) cam_ff (.*, .din(cam_in[i]), .dout(cam_raw[i]));
685 :
686 :
687 : assign nonblock_load_write[i] = (load_data_tag[NBLOAD_TAG_MSB:0] == cam_raw[i].tag[NBLOAD_TAG_MSB:0]) & cam_raw[i].valid;
688 :
689 :
690 : end : cam_array
691 :
692 :
693 :
694 : assign load_data_tag[NBLOAD_TAG_MSB:0] = lsu_nonblock_load_data_tag[NBLOAD_TAG_MSB:0];
695 :
696 : `ifdef RV_ASSERT_ON
697 : assert_dec_cam_nonblock_load_write_onehot: assert #0 ($onehot0(nonblock_load_write[NBLOAD_SIZE_MSB:0]));
698 : `endif
699 :
700 :
701 : assign nonblock_load_cancel = ((r_d_in.i0rd[4:0] == dec_nonblock_load_waddr[4:0]) & i0_wen_r); // cancel if any younger inst (including another nonblock) committing this cycle
702 :
703 :
704 : assign dec_nonblock_load_wen = lsu_nonblock_load_data_valid & |nonblock_load_write[NBLOAD_SIZE_MSB:0] & ~nonblock_load_cancel;
705 :
706 339 : always_comb begin
707 :
708 339 : dec_nonblock_load_waddr[4:0] = '0;
709 339 : i0_nonblock_load_stall = i0_nonblock_boundary_stall;
710 :
711 339 : for (int i=0; i<NBLOAD_SIZE; i++) begin
712 1356 : dec_nonblock_load_waddr[4:0] |= ({5{nonblock_load_write[i]}} & cam[i].rd[4:0]);
713 1356 : i0_nonblock_load_stall |= dec_i0_rs1_en_d & cam[i].valid & (cam[i].rd[4:0] == i0r.rs1[4:0]);
714 1356 : i0_nonblock_load_stall |= dec_i0_rs2_en_d & cam[i].valid & (cam[i].rd[4:0] == i0r.rs2[4:0]);
715 : end
716 :
717 : end
718 :
719 : assign i0_nonblock_boundary_stall = ((nonblock_load_rd[4:0]==i0r.rs1[4:0]) & lsu_nonblock_load_valid_m & dec_i0_rs1_en_d) |
720 : ((nonblock_load_rd[4:0]==i0r.rs2[4:0]) & lsu_nonblock_load_valid_m & dec_i0_rs2_en_d);
721 :
722 :
723 :
724 : // don't writeback a nonblock load
725 :
726 : rvdffs #(1) wbnbloaddelayff (.*, .clk(active_clk), .en(i0_r_ctl_en ), .din(lsu_nonblock_load_valid_m), .dout(nonblock_load_valid_m_delay) );
727 :
728 : assign i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load;
729 :
730 :
731 :
732 : // end non block load cam logic
733 :
734 : // pmu start
735 :
736 :
737 :
738 :
739 : assign csr_read = csr_ren_qual_d;
740 : assign csr_write = dec_csr_wen_unq_d;
741 :
742 : assign i0_br_unpred = i0_dp.jal & ~i0_predict_br;
743 :
744 : // the classes must be mutually exclusive with one another
745 :
746 339 : always_comb begin
747 339 : i0_itype = NULL_OP;
748 :
749 10537155 : if (i0_legal_decode_d) begin
750 4682292 : if (i0_dp.mul) i0_itype = MUL;
751 6233624 : if (i0_dp.load) i0_itype = LOAD;
752 5540595 : if (i0_dp.store) i0_itype = STORE;
753 7687312 : if (i0_dp.pm_alu) i0_itype = ALU;
754 16655314 : if (i0_dp.zbb | i0_dp.zbs |
755 : i0_dp.zbe | i0_dp.zbc |
756 : i0_dp.zbp | i0_dp.zbr |
757 : i0_dp.zbf | i0_dp.zba)
758 75265 : i0_itype = BITMANIPU;
759 4275491 : if ( csr_read & ~csr_write) i0_itype = CSRREAD;
760 977377 : if (~csr_read & csr_write) i0_itype = CSRWRITE;
761 13248003 : if ( csr_read & csr_write) i0_itype = CSRRW;
762 16195797 : if (i0_dp.ebreak) i0_itype = EBREAK;
763 9354741 : if (i0_dp.ecall) i0_itype = ECALL;
764 12505354 : if (i0_dp.fence) i0_itype = FENCE;
765 13440559 : if (i0_dp.fence_i) i0_itype = FENCEI; // fencei will set this even with fence attribute
766 9288621 : if (i0_dp.mret) i0_itype = MRET;
767 3734510 : if (i0_dp.condbr) i0_itype = CONDBR;
768 797746 : if (i0_dp.jal) i0_itype = JAL;
769 : end
770 : end
771 :
772 :
773 :
774 :
775 :
776 : // end pmu
777 :
778 :
779 : el2_dec_dec_ctl i0_dec (.inst(i0[31:0]),.out(i0_dp_raw));
780 :
781 :
782 :
783 :
784 : rvdff #(1) lsu_idle_ff (.*, .clk(active_clk), .din(lsu_idle_any), .dout(lsu_idle));
785 :
786 :
787 :
788 : assign leak1_i1_stall_in = (dec_tlu_flush_leak_one_r | (leak1_i1_stall & ~dec_tlu_flush_lower_r));
789 :
790 :
791 : assign leak1_mode = leak1_i1_stall;
792 :
793 : assign leak1_i0_stall_in = ((dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & ~dec_tlu_flush_lower_r));
794 :
795 :
796 :
797 :
798 : // 12b jal's can be predicted - these are calls
799 :
800 : assign i0_pcall_imm[20:1] = {i0[31],i0[19:12],i0[20],i0[30:21]};
801 :
802 : assign i0_pcall_12b_offset = (i0_pcall_imm[12]) ? (i0_pcall_imm[20:13] == 8'hff) : (i0_pcall_imm[20:13] == 8'h0);
803 :
804 : assign i0_pcall_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & (i0r.rd[4:0] == 5'd1 | i0r.rd[4:0] == 5'd5);
805 : assign i0_pja_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & ~(i0r.rd[4:0] == 5'd1 | i0r.rd[4:0] == 5'd5);
806 :
807 : assign i0_pcall_raw = i0_dp_raw.jal & i0_pcall_case; // this includes ja
808 : assign i0_pcall = i0_dp.jal & i0_pcall_case;
809 :
810 : assign i0_pja_raw = i0_dp_raw.jal & i0_pja_case;
811 : assign i0_pja = i0_dp.jal & i0_pja_case;
812 :
813 :
814 : assign i0_br_offset[11:0] = (i0_pcall_raw | i0_pja_raw) ? i0_pcall_imm[12:1] : {i0[31],i0[7],i0[30:25],i0[11:8]};
815 :
816 : assign i0_pret_case = (i0_dp_raw.jal & i0_dp_raw.imm12 & (i0r.rd[4:0] == 5'b0) & (i0r.rs1[4:0] == 5'd1 | i0r.rs1[4:0] == 5'd5)); // jalr with rd==0, rs1==1 or rs1==5 is a ret
817 :
818 : assign i0_pret_raw = i0_dp_raw.jal & i0_pret_case;
819 : assign i0_pret = i0_dp.jal & i0_pret_case;
820 :
821 : assign i0_jal = i0_dp.jal & ~i0_pcall_case & ~i0_pja_case & ~i0_pret_case;
822 :
823 : // lsu stuff
824 : // load/store mutually exclusive
825 : assign dec_lsu_offset_d[11:0] = ({12{ ~dec_extint_stall & i0_dp.lsu & i0_dp.load}} & i0[31:20]) |
826 : ({12{ ~dec_extint_stall & i0_dp.lsu & i0_dp.store}} & {i0[31:25],i0[11:7]});
827 :
828 :
829 :
830 : assign div_p.valid = div_decode_d;
831 :
832 : assign div_p.unsign = i0_dp.unsign;
833 : assign div_p.rem = i0_dp.rem;
834 :
835 :
836 : assign mul_p.valid = mul_decode_d;
837 :
838 : assign mul_p.rs1_sign = i0_dp.rs1_sign;
839 : assign mul_p.rs2_sign = i0_dp.rs2_sign;
840 : assign mul_p.low = i0_dp.low;
841 : assign mul_p.bcompress = i0_dp.bcompress;
842 : assign mul_p.bdecompress = i0_dp.bdecompress;
843 : assign mul_p.clmul = i0_dp.clmul;
844 : assign mul_p.clmulh = i0_dp.clmulh;
845 : assign mul_p.clmulr = i0_dp.clmulr;
846 : assign mul_p.grev = i0_dp.grev;
847 : assign mul_p.gorc = i0_dp.gorc;
848 : assign mul_p.shfl = i0_dp.shfl;
849 : assign mul_p.unshfl = i0_dp.unshfl;
850 : assign mul_p.xperm_n = i0_dp.xperm_n;
851 : assign mul_p.xperm_b = i0_dp.xperm_b;
852 : assign mul_p.xperm_h = i0_dp.xperm_h;
853 : assign mul_p.crc32_b = i0_dp.crc32_b;
854 : assign mul_p.crc32_h = i0_dp.crc32_h;
855 : assign mul_p.crc32_w = i0_dp.crc32_w;
856 : assign mul_p.crc32c_b = i0_dp.crc32c_b;
857 : assign mul_p.crc32c_h = i0_dp.crc32c_h;
858 : assign mul_p.crc32c_w = i0_dp.crc32c_w;
859 : assign mul_p.bfp = i0_dp.bfp;
860 :
861 :
862 339 : always_comb begin
863 339 : lsu_p = '0;
864 :
865 28260502 : if (dec_extint_stall) begin
866 0 : lsu_p.load = 1'b1;
867 0 : lsu_p.word = 1'b1;
868 0 : lsu_p.fast_int = 1'b1;
869 0 : lsu_p.valid = 1'b1;
870 : end
871 28260502 : else begin
872 28260502 : lsu_p.valid = lsu_decode_d;
873 :
874 28260502 : lsu_p.load = i0_dp.load ;
875 28260502 : lsu_p.store = i0_dp.store;
876 28260502 : lsu_p.by = i0_dp.by ;
877 28260502 : lsu_p.half = i0_dp.half ;
878 28260502 : lsu_p.word = i0_dp.word ;
879 28260502 : lsu_p.stack = (i0r.rs1[4:0]==5'd2); // stack reference
880 :
881 28260502 : lsu_p.load_ldst_bypass_d = load_ldst_bypass_d ;
882 28260502 : lsu_p.store_data_bypass_d = store_data_bypass_d;
883 28260502 : lsu_p.store_data_bypass_m = store_data_bypass_m;
884 :
885 28260502 : lsu_p.unsign = i0_dp.unsign;
886 : end
887 : end
888 :
889 :
890 : assign dec_lsu_valid_raw_d = (i0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & ~dma_dccm_stall_any & ~i0_block_raw_d) | dec_extint_stall;
891 :
892 :
893 :
894 : assign i0r.rs1[4:0] = i0[19:15];
895 : assign i0r.rs2[4:0] = i0[24:20];
896 : assign i0r.rd[4:0] = i0[11:7];
897 :
898 :
899 : assign dec_i0_rs1_en_d = i0_dp.rs1 & (i0r.rs1[4:0] != 5'd0); // if rs1_en=0 then read will be all 0's
900 : assign dec_i0_rs2_en_d = i0_dp.rs2 & (i0r.rs2[4:0] != 5'd0);
901 : assign i0_rd_en_d = i0_dp.rd & (i0r.rd[4:0] != 5'd0);
902 :
903 : assign dec_i0_rs1_d[4:0] = i0r.rs1[4:0];
904 : assign dec_i0_rs2_d[4:0] = i0r.rs2[4:0];
905 :
906 :
907 : assign i0_jalimm20 = i0_dp.jal & i0_dp.imm20; // jal
908 : assign i0_uiimm20 = ~i0_dp.jal & i0_dp.imm20;
909 :
910 :
911 : // csr logic
912 :
913 : assign dec_csr_ren_d = i0_dp.csr_read & i0_valid_d;
914 : assign csr_ren_qual_d = i0_dp.csr_read & i0_legal_decode_d;
915 :
916 : assign csr_clr_d = i0_dp.csr_clr & i0_legal_decode_d;
917 : assign csr_set_d = i0_dp.csr_set & i0_legal_decode_d;
918 : assign csr_write_d = i0_csr_write & i0_legal_decode_d;
919 :
920 : assign i0_csr_write_only_d = i0_csr_write & ~i0_dp.csr_read;
921 :
922 : assign dec_csr_wen_unq_d = (i0_dp.csr_clr | i0_dp.csr_set | i0_csr_write) & i0_valid_d; // for csr legal, can't write read-only csr
923 :
924 : assign dec_csr_any_unq_d = any_csr_d & i0_valid_d;
925 :
926 :
927 : assign dec_csr_rdaddr_d[11:0] = {12{dec_csr_any_unq_d}} & i0[31:20];
928 : assign dec_csr_rdaddr_r[11:0] = {12{~r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];
929 : assign dec_csr_wraddr_r[11:0] = {12{r_d.csrwen & r_d.i0valid}} & r_d.csraddr[11:0];
930 :
931 :
932 : // make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb
933 : // also use valid so it's flushable
934 : assign dec_csr_wen_r = r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_r;
935 :
936 : // If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write.
937 : assign dec_csr_stall_int_ff = ((r_d.csraddr[11:0] == 12'h300) | (r_d.csraddr[11:0] == 12'h304)) & r_d.csrwen & r_d.i0valid & ~dec_tlu_i0_kill_writeb_wb;
938 :
939 :
940 : rvdff #(5) csrmiscff (.*,
941 : .clk (active_clk),
942 : .din ({csr_ren_qual_d, csr_clr_d, csr_set_d, csr_write_d, i0_dp.csr_imm}),
943 : .dout({csr_read_x, csr_clr_x, csr_set_x, csr_write_x, csr_imm_x})
944 : );
945 :
946 :
947 :
948 :
949 : // perform the update operation if any
950 :
951 : rvdffe #(37) csr_rddata_x_ff (.*, .en(i0_x_data_en & any_csr_d), .din( {i0[19:15],dec_csr_rddata_d[31:0]}), .dout({csrimm_x[4:0],csr_rddata_x[31:0]}));
952 :
953 :
954 : assign csr_mask_x[31:0] = ({32{ csr_imm_x}} & {27'b0,csrimm_x[4:0]}) |
955 : ({32{~csr_imm_x}} & exu_csr_rs1_x[31:0] );
956 :
957 :
958 : assign write_csr_data_x[31:0] = ({32{csr_clr_x}} & (csr_rddata_x[31:0] & ~csr_mask_x[31:0])) |
959 : ({32{csr_set_x}} & (csr_rddata_x[31:0] | csr_mask_x[31:0])) |
960 : ({32{csr_write_x}} & ( csr_mask_x[31:0]));
961 :
962 :
963 : // pause instruction
964 :
965 :
966 :
967 :
968 : assign clear_pause = (dec_tlu_flush_lower_r & ~dec_tlu_flush_pause_r) |
969 : (pause_state & (write_csr_data[31:1] == 31'b0)); // if 0 or 1 then exit pause state - 1 cycle pause
970 :
971 : assign pause_state_in = (dec_tlu_wr_pause_r | pause_state) & ~clear_pause;
972 :
973 :
974 :
975 : assign dec_pause_state = pause_state;
976 :
977 :
978 :
979 : assign dec_pause_state_cg = pause_state & ~tlu_wr_pause_r1 & ~tlu_wr_pause_r2;
980 :
981 : // end pause
982 :
983 :
984 : assign csr_data_wen = ((csr_clr_x | csr_set_x | csr_write_x) & csr_read_x) | dec_tlu_wr_pause_r | pause_state;
985 :
986 : assign write_csr_data_in[31:0] = (pause_state) ? (write_csr_data[31:0] - 32'b1) :
987 : (dec_tlu_wr_pause_r) ? dec_csr_wrdata_r[31:0] : write_csr_data_x[31:0];
988 :
989 : // will hold until write-back at which time the CSR will be updated while GPR is possibly written with prior CSR
990 : rvdffe #(32) write_csr_ff (.*, .clk(free_l2clk), .en(csr_data_wen), .din(write_csr_data_in[31:0]), .dout(write_csr_data[31:0]));
991 :
992 : assign pause_stall = pause_state;
993 :
994 : // for csr write only data is produced by the alu
995 : assign dec_csr_wrdata_r[31:0] = (r_d.csrwonly & r_d.i0valid) ? i0_result_corr_r[31:0] : write_csr_data[31:0];
996 :
997 :
998 :
999 : assign dec_i0_immed_d[31:0] = i0_immed_d[31:0];
1000 :
1001 : assign i0_immed_d[31:0] = ({32{i0_dp.imm12}} & { {20{i0[31]}},i0[31:20] }) | // jalr
1002 : ({32{i0_dp.shimm5}} & { 27'b0, i0[24:20] }) |
1003 : ({32{i0_jalimm20}} & { {12{i0[31]}},i0[19:12],i0[20],i0[30:21],1'b0}) |
1004 : ({32{i0_uiimm20}} & { i0[31:12],12'b0 }) |
1005 : ({32{i0_csr_write_only_d & i0_dp.csr_imm}} & { 27'b0, i0[19:15]}); // for csr's that only write csr, dont read csr
1006 :
1007 :
1008 : // all conditional branches are currently predict_nt
1009 : // change this to generate the sequential address for all other cases for NPC requirements at commit
1010 : assign dec_i0_br_immed_d[12:1] = (i0_ap.predict_nt & ~i0_dp.jal) ? i0_br_offset[11:0] : {10'b0,i0_ap_pc4,i0_ap_pc2};
1011 :
1012 :
1013 : assign last_br_immed_d[12:1] = ((i0_ap.predict_nt) ? {10'b0,i0_ap_pc4,i0_ap_pc2} : i0_br_offset[11:0] );
1014 :
1015 : assign i0_valid_d = dec_ib0_valid_d;
1016 :
1017 : // load_stall includes bus_barrier
1018 :
1019 : assign i0_load_stall_d = (i0_dp.load ) & (lsu_load_stall_any | dma_dccm_stall_any);
1020 :
1021 : assign i0_store_stall_d = i0_dp.store & (lsu_store_stall_any | dma_dccm_stall_any);
1022 :
1023 :
1024 :
1025 : // some CSR reads need to be presync'd
1026 : assign i0_presync = i0_dp.presync | dec_tlu_presync_d | debug_fence_i | debug_fence_raw | dec_tlu_pipelining_disable; // both fence's presync
1027 :
1028 : // some CSR writes need to be postsync'd
1029 : assign i0_postsync = i0_dp.postsync | dec_tlu_postsync_d | debug_fence_i | // only fence_i postsync
1030 : (i0_csr_write_only_d & (i0[31:20] == 12'h7c2)); // wr_pause must postsync
1031 :
1032 :
1033 : // debug fence csr
1034 : assign debug_fence_i = dec_debug_fence_d & dbg_cmd_wrdata[0];
1035 : assign debug_fence_raw = dec_debug_fence_d & dbg_cmd_wrdata[1];
1036 :
1037 : assign debug_fence = debug_fence_raw | debug_fence_i; // fence_i causes a fence
1038 :
1039 : assign i0_csr_write = i0_dp.csr_write & ~dec_debug_fence_d;
1040 : // end debug
1041 :
1042 :
1043 : // lets make ebreak, ecall, mret postsync, so break sync into pre and post
1044 :
1045 : assign presync_stall = (i0_presync & prior_inflight_eff);
1046 :
1047 : assign prior_inflight_eff = (i0_dp.div) ? prior_inflight_x : prior_inflight;
1048 :
1049 : assign i0_div_prior_div_stall = i0_dp.div & div_active;
1050 :
1051 : // Raw block has everything excepts the stalls coming from the lsu
1052 : assign i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) |
1053 : dec_extint_stall |
1054 : pause_stall |
1055 : leak1_i0_stall |
1056 : dec_tlu_debug_stall |
1057 : postsync_stall |
1058 : presync_stall |
1059 : ((i0_dp.fence | debug_fence) & ~lsu_idle) |
1060 : i0_nonblock_load_stall |
1061 : i0_load_block_d |
1062 : i0_nonblock_div_stall |
1063 : i0_div_prior_div_stall;
1064 :
1065 : assign i0_block_d = i0_block_raw_d | i0_store_stall_d | i0_load_stall_d;
1066 : assign i0_exublock_d = i0_block_raw_d;
1067 :
1068 :
1069 : // block reads if there is a prior csr write in the pipeline
1070 : assign prior_csr_write = x_d.csrwonly |
1071 : r_d.csrwonly |
1072 : wbd.csrwonly;
1073 :
1074 :
1075 :
1076 : if (pt.BITMANIP_ZBB == 1)
1077 : assign bitmanip_zbb_legal = 1'b1;
1078 : else
1079 : assign bitmanip_zbb_legal = ~(i0_dp.zbb & ~i0_dp.zbp);
1080 :
1081 : if (pt.BITMANIP_ZBS == 1)
1082 : assign bitmanip_zbs_legal = 1'b1;
1083 : else
1084 : assign bitmanip_zbs_legal = ~i0_dp.zbs;
1085 :
1086 : if (pt.BITMANIP_ZBE == 1)
1087 : assign bitmanip_zbe_legal = 1'b1;
1088 : else
1089 : assign bitmanip_zbe_legal = ~(i0_dp.zbe & ~i0_dp.zbp & ~i0_dp.zbf);
1090 :
1091 : if (pt.BITMANIP_ZBC == 1)
1092 : assign bitmanip_zbc_legal = 1'b1;
1093 : else
1094 : assign bitmanip_zbc_legal = ~i0_dp.zbc;
1095 :
1096 : if (pt.BITMANIP_ZBP == 1)
1097 : assign bitmanip_zbp_legal = 1'b1;
1098 : else
1099 : assign bitmanip_zbp_legal = ~(i0_dp.zbp & ~i0_dp.zbb & ~i0_dp.zbe & ~i0_dp.zbf);
1100 :
1101 : if (pt.BITMANIP_ZBR == 1)
1102 : assign bitmanip_zbr_legal = 1'b1;
1103 : else
1104 : assign bitmanip_zbr_legal = ~i0_dp.zbr;
1105 :
1106 : if (pt.BITMANIP_ZBF == 1)
1107 : assign bitmanip_zbf_legal = 1'b1;
1108 : else
1109 : assign bitmanip_zbf_legal = ~(i0_dp.zbf & ~i0_dp.zbp & ~i0_dp.zbe);
1110 :
1111 : if (pt.BITMANIP_ZBA == 1)
1112 : assign bitmanip_zba_legal = 1'b1;
1113 : else
1114 : assign bitmanip_zba_legal = ~i0_dp.zba;
1115 :
1116 : if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) )
1117 : assign bitmanip_zbb_zbp_legal = 1'b1;
1118 : else
1119 : assign bitmanip_zbb_zbp_legal = ~(i0_dp.zbb & i0_dp.zbp & ~i0_dp.zbf); // added ~ZBF to exclude ZEXT.H
1120 :
1121 : if ( (pt.BITMANIP_ZBP == 1) | (pt.BITMANIP_ZBE == 1) | (pt.BITMANIP_ZBF == 1))
1122 : assign bitmanip_zbp_zbe_zbf_legal = 1'b1;
1123 : else
1124 : assign bitmanip_zbp_zbe_zbf_legal = ~(i0_dp.zbp & i0_dp.zbe & i0_dp.zbf & ~i0_dp.zbb); // added ~ZBB to exclude ZEXT.H
1125 :
1126 : if ( (pt.BITMANIP_ZBB == 1) | (pt.BITMANIP_ZBP == 1) | (pt.BITMANIP_ZBE == 1) | (pt.BITMANIP_ZBF == 1))
1127 : assign bitmanip_zbb_zbp_zbe_zbf_legal = 1'b1;
1128 : else
1129 : assign bitmanip_zbb_zbp_zbe_zbf_legal = ~(i0_dp.zbp & i0_dp.zbe & i0_dp.zbf & i0_dp.zbb); // added only for ZEXT.H
1130 :
1131 :
1132 : assign any_csr_d = i0_dp.csr_read | i0_csr_write;
1133 : assign bitmanip_legal = bitmanip_zbb_legal & bitmanip_zbs_legal & bitmanip_zbe_legal & bitmanip_zbc_legal & bitmanip_zbp_legal & bitmanip_zbr_legal & bitmanip_zbf_legal & bitmanip_zba_legal & bitmanip_zbb_zbp_legal & bitmanip_zbp_zbe_zbf_legal & bitmanip_zbb_zbp_zbe_zbf_legal;
1134 :
1135 : assign i0_legal = i0_dp.legal & (~any_csr_d | dec_csr_legal_d) & bitmanip_legal;
1136 :
1137 :
1138 :
1139 : // illegal inst handling
1140 :
1141 :
1142 : assign shift_illegal = dec_i0_decode_d & ~i0_legal;
1143 :
1144 : assign illegal_inst_en = shift_illegal & ~illegal_lockout;
1145 :
1146 : rvdffe #(32) illegal_any_ff (.*, .en(illegal_inst_en), .din(i0_inst_d[31:0]), .dout(dec_illegal_inst[31:0]));
1147 :
1148 : assign illegal_lockout_in = (shift_illegal | illegal_lockout) & ~flush_final_r;
1149 :
1150 :
1151 :
1152 : // allow illegals to flow down the pipe
1153 : assign dec_i0_decode_d = i0_valid_d & ~i0_block_d & ~dec_tlu_flush_lower_r & ~flush_final_r;
1154 : assign i0_exudecode_d = i0_valid_d & ~i0_exublock_d & ~dec_tlu_flush_lower_r & ~flush_final_r;
1155 :
1156 : // define i0 legal decode
1157 : assign i0_legal_decode_d = dec_i0_decode_d & i0_legal;
1158 : assign i0_exulegal_decode_d = i0_exudecode_d & i0_legal;
1159 :
1160 :
1161 : // performance monitor signals
1162 : assign dec_pmu_instr_decoded = dec_i0_decode_d;
1163 :
1164 : assign dec_pmu_decode_stall = i0_valid_d & ~dec_i0_decode_d;
1165 :
1166 : assign dec_pmu_postsync_stall = postsync_stall & i0_valid_d;
1167 : assign dec_pmu_presync_stall = presync_stall & i0_valid_d;
1168 :
1169 :
1170 :
1171 : // illegals will postsync
1172 : assign ps_stall_in = ( dec_i0_decode_d & (i0_postsync | ~i0_legal) ) |
1173 : ( ps_stall & prior_inflight_x );
1174 :
1175 :
1176 :
1177 : assign postsync_stall = ps_stall;
1178 :
1179 :
1180 : assign prior_inflight_x = x_d.i0valid;
1181 : assign prior_inflight_wb = r_d.i0valid;
1182 :
1183 : assign prior_inflight = prior_inflight_x | prior_inflight_wb;
1184 :
1185 : assign dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp.alu;
1186 : assign dec_i0_branch_d = i0_dp.condbr | i0_dp.jal | i0_br_error_all;
1187 :
1188 : assign lsu_decode_d = i0_legal_decode_d & i0_dp.lsu;
1189 : assign mul_decode_d = i0_exulegal_decode_d & i0_dp.mul;
1190 : assign div_decode_d = i0_exulegal_decode_d & i0_dp.div;
1191 :
1192 : assign dec_qual_lsu_d = i0_dp.lsu;
1193 :
1194 :
1195 :
1196 :
1197 :
1198 : // scheduling logic for alu
1199 :
1200 : assign i0_rs1_depend_i0_x = dec_i0_rs1_en_d & x_d.i0v & (x_d.i0rd[4:0] == i0r.rs1[4:0]);
1201 : assign i0_rs1_depend_i0_r = dec_i0_rs1_en_d & r_d.i0v & (r_d.i0rd[4:0] == i0r.rs1[4:0]);
1202 :
1203 : assign i0_rs2_depend_i0_x = dec_i0_rs2_en_d & x_d.i0v & (x_d.i0rd[4:0] == i0r.rs2[4:0]);
1204 : assign i0_rs2_depend_i0_r = dec_i0_rs2_en_d & r_d.i0v & (r_d.i0rd[4:0] == i0r.rs2[4:0]);
1205 :
1206 :
1207 : // order the producers as follows: , i0_x, i0_r, i0_wb
1208 :
1209 : assign {i0_rs1_class_d, i0_rs1_depth_d[1:0]} = (i0_rs1_depend_i0_x ) ? { i0_x_c, 2'd1 } :
1210 : (i0_rs1_depend_i0_r ) ? { i0_r_c, 2'd2 } : '0;
1211 :
1212 : assign {i0_rs2_class_d, i0_rs2_depth_d[1:0]} = (i0_rs2_depend_i0_x ) ? { i0_x_c, 2'd1 } :
1213 : (i0_rs2_depend_i0_r ) ? { i0_r_c, 2'd2 } : '0;
1214 :
1215 :
1216 : // stores will bypass load data in the lsu pipe
1217 :
1218 : if (pt.LOAD_TO_USE_PLUS1 == 1) begin : genblock
1219 : assign i0_load_block_d = (i0_rs1_class_d.load & i0_rs1_depth_d[0]) |
1220 : (i0_rs2_class_d.load & i0_rs2_depth_d[0] & ~i0_dp.store);
1221 :
1222 : assign load_ldst_bypass_d = (i0_dp.load | i0_dp.store) & i0_rs1_depth_d[1] & i0_rs1_class_d.load;
1223 :
1224 : assign store_data_bypass_d = i0_dp.store & i0_rs2_depth_d[1] & i0_rs2_class_d.load;
1225 :
1226 : assign store_data_bypass_m = i0_dp.store & i0_rs2_depth_d[0] & i0_rs2_class_d.load;
1227 : end
1228 : else begin : genblock
1229 :
1230 : assign i0_load_block_d = 1'b0;
1231 :
1232 : assign load_ldst_bypass_d = (i0_dp.load | i0_dp.store) & i0_rs1_depth_d[0] & i0_rs1_class_d.load;
1233 :
1234 : assign store_data_bypass_d = i0_dp.store & i0_rs2_depth_d[0] & i0_rs2_class_d.load;
1235 :
1236 : assign store_data_bypass_m = 1'b0;
1237 : end
1238 :
1239 :
1240 :
1241 :
1242 :
1243 :
1244 : assign dec_tlu_i0_valid_r = r_d.i0valid & ~dec_tlu_flush_lower_wb;
1245 :
1246 :
1247 : assign d_t.legal = i0_legal_decode_d;
1248 : assign d_t.icaf = i0_icaf_d & i0_legal_decode_d; // dbecc is icaf exception
1249 : assign d_t.icaf_second = dec_i0_icaf_second_d & i0_legal_decode_d; // this includes icaf and dbecc
1250 : assign d_t.icaf_type[1:0] = dec_i0_icaf_type_d[1:0];
1251 :
1252 : assign d_t.fence_i = (i0_dp.fence_i | debug_fence_i) & i0_legal_decode_d;
1253 :
1254 : // put pmu info into the trap packet
1255 : assign d_t.pmu_i0_itype = i0_itype;
1256 : assign d_t.pmu_i0_br_unpred = i0_br_unpred;
1257 : assign d_t.pmu_divide = 1'b0;
1258 : assign d_t.pmu_lsu_misaligned = 1'b0;
1259 :
1260 : assign d_t.i0trigger[3:0] = dec_i0_trigger_match_d[3:0] & {4{dec_i0_decode_d}};
1261 :
1262 :
1263 :
1264 : rvdfflie #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_xff (.*, .en(i0_x_ctl_en), .din(d_t), .dout(x_t));
1265 :
1266 339 : always_comb begin
1267 339 : x_t_in = x_t;
1268 339 : x_t_in.i0trigger[3:0] = x_t.i0trigger & ~{4{dec_tlu_flush_lower_wb}};
1269 : end
1270 :
1271 :
1272 : rvdfflie #( .WIDTH($bits(el2_trap_pkt_t)),.LEFT(9) ) trap_r_ff (.*, .en(i0_x_ctl_en), .din(x_t_in), .dout(r_t));
1273 :
1274 :
1275 339 : always_comb begin
1276 :
1277 339 : r_t_in = r_t;
1278 :
1279 339 : r_t_in.i0trigger[3:0] = ({4{(r_d.i0load | r_d.i0store)}} & lsu_trigger_match_r[3:0]) | r_t.i0trigger[3:0];
1280 339 : r_t_in.pmu_lsu_misaligned = lsu_pmu_misaligned_r; // only valid if a load/store is valid in DC3 stage
1281 :
1282 29666 : if (dec_tlu_flush_lower_wb) r_t_in = '0 ;
1283 :
1284 : end
1285 :
1286 :
1287 339 : always_comb begin
1288 :
1289 339 : dec_tlu_packet_r = r_t_in;
1290 339 : dec_tlu_packet_r.pmu_divide = r_d.i0div & r_d.i0valid;
1291 :
1292 : end
1293 :
1294 :
1295 : // end tlu stuff
1296 :
1297 :
1298 : assign i0_d_c.mul = i0_dp.mul & i0_legal_decode_d;
1299 : assign i0_d_c.load = i0_dp.load & i0_legal_decode_d;
1300 : assign i0_d_c.alu = i0_dp.alu & i0_legal_decode_d;
1301 :
1302 : rvdffs #( $bits(el2_class_pkt_t) ) i0_x_c_ff (.*, .en(i0_x_ctl_en), .clk(active_clk), .din(i0_d_c), .dout(i0_x_c));
1303 : rvdffs #( $bits(el2_class_pkt_t) ) i0_r_c_ff (.*, .en(i0_r_ctl_en), .clk(active_clk), .din(i0_x_c), .dout(i0_r_c));
1304 :
1305 :
1306 : assign d_d.i0rd[4:0] = i0r.rd[4:0];
1307 : assign d_d.i0v = i0_rd_en_d & i0_legal_decode_d;
1308 : assign d_d.i0valid = dec_i0_decode_d; // has flush_final_r
1309 :
1310 : assign d_d.i0load = i0_dp.load & i0_legal_decode_d;
1311 : assign d_d.i0store = i0_dp.store & i0_legal_decode_d;
1312 : assign d_d.i0div = i0_dp.div & i0_legal_decode_d;
1313 :
1314 :
1315 : assign d_d.csrwen = dec_csr_wen_unq_d & i0_legal_decode_d;
1316 : assign d_d.csrwonly = i0_csr_write_only_d & dec_i0_decode_d;
1317 : assign d_d.csraddr[11:0] = i0[31:20]; // csr read/write address
1318 :
1319 :
1320 : rvdff #(3) i0cgff (.*, .clk(active_clk), .din(i0_pipe_en[3:1]), .dout(i0_pipe_en[2:0]));
1321 :
1322 : assign i0_pipe_en[3] = dec_i0_decode_d;
1323 :
1324 : assign i0_x_ctl_en = (|i0_pipe_en[3:2] | clk_override);
1325 : assign i0_r_ctl_en = (|i0_pipe_en[2:1] | clk_override);
1326 : assign i0_wb_ctl_en = (|i0_pipe_en[1:0] | clk_override);
1327 : assign i0_x_data_en = ( i0_pipe_en[3] | clk_override);
1328 : assign i0_r_data_en = ( i0_pipe_en[2] | clk_override);
1329 : assign i0_wb_data_en = ( i0_pipe_en[1] | clk_override);
1330 :
1331 : assign dec_data_en[1:0] = {i0_x_data_en, i0_r_data_en};
1332 : assign dec_ctl_en[1:0] = {i0_x_ctl_en, i0_r_ctl_en};
1333 :
1334 :
1335 :
1336 : rvdfflie #( .WIDTH($bits(el2_dest_pkt_t)),.LEFT(15) ) e1ff (.*, .en(i0_x_ctl_en), .din(d_d), .dout(x_d));
1337 :
1338 339 : always_comb begin
1339 339 : x_d_in = x_d;
1340 :
1341 339 : x_d_in.i0v = x_d.i0v & ~dec_tlu_flush_lower_wb & ~dec_tlu_flush_lower_r;
1342 339 : x_d_in.i0valid = x_d.i0valid & ~dec_tlu_flush_lower_wb & ~dec_tlu_flush_lower_r;
1343 : end
1344 :
1345 : rvdfflie #( .WIDTH($bits(el2_dest_pkt_t)), .LEFT(15) ) r_d_ff (.*, .en(i0_r_ctl_en), .din(x_d_in), .dout(r_d));
1346 :
1347 :
1348 339 : always_comb begin
1349 :
1350 339 : r_d_in = r_d;
1351 :
1352 :
1353 : // for the bench
1354 339 : r_d_in.i0rd[4:0] = r_d.i0rd[4:0];
1355 :
1356 339 : r_d_in.i0v = (r_d.i0v & ~dec_tlu_flush_lower_wb);
1357 339 : r_d_in.i0valid = (r_d.i0valid & ~dec_tlu_flush_lower_wb);
1358 :
1359 339 : r_d_in.i0load = r_d.i0load & ~dec_tlu_flush_lower_wb;
1360 339 : r_d_in.i0store = r_d.i0store & ~dec_tlu_flush_lower_wb;
1361 :
1362 : end
1363 :
1364 :
1365 : rvdfflie #(.WIDTH($bits(el2_dest_pkt_t)), .LEFT(15)) wbff (.*, .en(i0_wb_ctl_en), .din(r_d_in), .dout(wbd));
1366 :
1367 : assign dec_i0_waddr_r[4:0] = r_d_in.i0rd[4:0];
1368 :
1369 : assign i0_wen_r = r_d_in.i0v & ~dec_tlu_i0_kill_writeb_r;
1370 : assign dec_i0_wen_r = i0_wen_r & ~r_d_in.i0div & ~i0_load_kill_wen_r; // don't write a nonblock load 1st time down the pipe
1371 : assign dec_i0_wdata_r[31:0] = i0_result_corr_r[31:0];
1372 :
1373 :
1374 : // divide stuff
1375 : assign div_e1_to_r = (x_d.i0div & x_d.i0valid) |
1376 : (r_d.i0div & r_d.i0valid);
1377 :
1378 : assign div_active_in = i0_div_decode_d | (div_active & ~exu_div_wren & ~nonblock_div_cancel);
1379 :
1380 :
1381 : assign dec_div_active = div_active;
1382 :
1383 : // nonblocking div scheme
1384 :
1385 : assign i0_nonblock_div_stall = (dec_i0_rs1_en_d & div_active & (div_waddr_wb[4:0] == i0r.rs1[4:0])) |
1386 : (dec_i0_rs2_en_d & div_active & (div_waddr_wb[4:0] == i0r.rs2[4:0]));
1387 :
1388 :
1389 : assign div_flush = (x_d.i0div & x_d.i0valid & (x_d.i0rd[4:0]==5'b0) ) |
1390 : (x_d.i0div & x_d.i0valid & dec_tlu_flush_lower_r ) |
1391 : (r_d.i0div & r_d.i0valid & dec_tlu_flush_lower_r & dec_tlu_i0_kill_writeb_r);
1392 :
1393 :
1394 : // cancel if any younger inst committing this cycle to same dest as nonblock divide
1395 : assign nonblock_div_cancel = (div_active & div_flush) |
1396 : (div_active & ~div_e1_to_r & (r_d.i0rd[4:0] == div_waddr_wb[4:0]) & i0_wen_r);
1397 :
1398 : assign dec_div_cancel = nonblock_div_cancel;
1399 :
1400 :
1401 :
1402 : assign i0_div_decode_d = i0_legal_decode_d & i0_dp.div;
1403 :
1404 : // for load_to_use_plus1, the load result data is merged in R stage instead of D
1405 :
1406 : if ( pt.LOAD_TO_USE_PLUS1 == 1 ) begin : genblock1
1407 : assign i0_result_x[31:0] = exu_i0_result_x[31:0];
1408 : assign i0_result_r[31:0] = (r_d.i0v & r_d.i0load) ? lsu_result_m[31:0] : i0_result_r_raw[31:0];
1409 : end
1410 : else begin : genblock1
1411 : assign i0_result_x[31:0] = (x_d.i0v & x_d.i0load) ? lsu_result_m[31:0] : exu_i0_result_x[31:0];
1412 : assign i0_result_r[31:0] = i0_result_r_raw[31:0];
1413 : end
1414 :
1415 :
1416 : rvdffe #(32) i0_result_r_ff (.*, .en(i0_r_data_en & (x_d.i0v | x_d.csrwen | debug_valid_x)), .din(i0_result_x[31:0]), .dout(i0_result_r_raw[31:0]));
1417 :
1418 : // correct lsu load data - don't use for bypass, do pass down the pipe
1419 : assign i0_result_corr_r[31:0] = (r_d.i0v & r_d.i0load) ? lsu_result_corr_r[31:0] : i0_result_r_raw[31:0];
1420 :
1421 :
1422 : rvdffe #(12) e1brpcff (.*, .en(i0_x_data_en), .din(last_br_immed_d[12:1] ), .dout(last_br_immed_x[12:1]));
1423 :
1424 :
1425 :
1426 : assign i0_wb_en = i0_wb_data_en;
1427 :
1428 : assign i0_inst_wb_in[31:0] = i0_inst_r[31:0];
1429 : assign i0_inst_d[31:0] = (dec_i0_pc4_d) ? i0[31:0] : {16'b0, ifu_i0_cinst[15:0]};
1430 :
1431 :
1432 : assign trace_enable = ~dec_tlu_trace_disable;
1433 :
1434 :
1435 : rvdffe #(.WIDTH(5),.OVERRIDE(1)) i0rdff (.*, .en(i0_div_decode_d), .din(i0r.rd[4:0]), .dout(div_waddr_wb[4:0]));
1436 :
1437 : rvdffe #(32) i0xinstff (.*, .en(i0_x_data_en & trace_enable), .din(i0_inst_d[31:0]), .dout(i0_inst_x[31:0]));
1438 : rvdffe #(32) i0cinstff (.*, .en(i0_r_data_en & trace_enable), .din(i0_inst_x[31:0]), .dout(i0_inst_r[31:0]));
1439 :
1440 : rvdffe #(32) i0wbinstff (.*, .en(i0_wb_en & trace_enable), .din(i0_inst_wb_in[31:0]), .dout(i0_inst_wb[31:0]));
1441 : rvdffe #(31) i0wbpcff (.*, .en(i0_wb_en & trace_enable), .din(dec_tlu_i0_pc_r[31:1]), .dout( i0_pc_wb[31:1]));
1442 :
1443 : assign dec_i0_inst_wb[31:0] = i0_inst_wb[31:0];
1444 : assign dec_i0_pc_wb[31:1] = i0_pc_wb[31:1];
1445 :
1446 :
1447 :
1448 : rvdffpcie #(31) i0_pc_r_ff (.*, .en(i0_r_data_en), .din(exu_i0_pc_x[31:1]), .dout(dec_i0_pc_r[31:1]));
1449 :
1450 : assign dec_tlu_i0_pc_r[31:1] = dec_i0_pc_r[31:1];
1451 :
1452 :
1453 : rvbradder ibradder_correct (
1454 : .pc(exu_i0_pc_x[31:1]),
1455 : .offset(last_br_immed_x[12:1]),
1456 : .dout(pred_correct_npc_x[31:1]));
1457 :
1458 :
1459 :
1460 : // add nonblock load rs1/rs2 bypass cases
1461 :
1462 : assign i0_rs1_nonblock_load_bypass_en_d = dec_i0_rs1_en_d & dec_nonblock_load_wen & (dec_nonblock_load_waddr[4:0] == i0r.rs1[4:0]);
1463 :
1464 : assign i0_rs2_nonblock_load_bypass_en_d = dec_i0_rs2_en_d & dec_nonblock_load_wen & (dec_nonblock_load_waddr[4:0] == i0r.rs2[4:0]);
1465 :
1466 :
1467 :
1468 : // bit 2 is priority match, bit 0 lowest priority, i0_x, i0_r
1469 :
1470 : assign i0_rs1bypass[2] = i0_rs1_depth_d[0] & (i0_rs1_class_d.alu | i0_rs1_class_d.mul );
1471 : assign i0_rs1bypass[1] = i0_rs1_depth_d[0] & ( i0_rs1_class_d.load);
1472 : assign i0_rs1bypass[0] = i0_rs1_depth_d[1] & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load);
1473 :
1474 : assign i0_rs2bypass[2] = i0_rs2_depth_d[0] & (i0_rs2_class_d.alu | i0_rs2_class_d.mul );
1475 : assign i0_rs2bypass[1] = i0_rs2_depth_d[0] & ( i0_rs2_class_d.load);
1476 : assign i0_rs2bypass[0] = i0_rs2_depth_d[1] & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load);
1477 :
1478 :
1479 : assign dec_i0_rs1_bypass_en_d[3] = i0_rs1_nonblock_load_bypass_en_d & ~i0_rs1bypass[0] & ~i0_rs1bypass[1] & ~i0_rs1bypass[2];
1480 : assign dec_i0_rs1_bypass_en_d[2] = i0_rs1bypass[2];
1481 : assign dec_i0_rs1_bypass_en_d[1] = i0_rs1bypass[1];
1482 : assign dec_i0_rs1_bypass_en_d[0] = i0_rs1bypass[0];
1483 :
1484 : assign dec_i0_rs2_bypass_en_d[3] = i0_rs2_nonblock_load_bypass_en_d & ~i0_rs2bypass[0] & ~i0_rs2bypass[1] & ~i0_rs2bypass[2];
1485 : assign dec_i0_rs2_bypass_en_d[2] = i0_rs2bypass[2];
1486 : assign dec_i0_rs2_bypass_en_d[1] = i0_rs2bypass[1];
1487 : assign dec_i0_rs2_bypass_en_d[0] = i0_rs2bypass[0];
1488 :
1489 :
1490 : assign dec_i0_result_r[31:0] = i0_result_r[31:0];
1491 :
1492 :
1493 : endmodule // el2_dec_decode_ctl
1494 :
1495 : // file "decode" is human readable file that has all of the instruction decodes
1496 : // defined and is part of git repo. Modify this file as needed.
1497 : //
1498 : // The tools needed are "coredecode", "addasign" and "espresso". The first two
1499 : // can be found in this repo under /tools. Espresso can be found in another
1500 : // repo (https://github.com/chipsalliance/espresso).
1501 : // IMPORTANT: use Espresso v2.4 (git tag v2.4)
1502 : //
1503 : // To generate instruction decoding equations do:
1504 : // 1) coredecode -in decode > coredecode.e
1505 : // 2) espresso -Dso -oeqntott < coredecode.e | addassign -pre out. > equations
1506 : // 3) copy-paste assignments from the file "equations" and replace ones below.
1507 : //
1508 : // To generate instruction legality check equation do:
1509 : // 1) coredecode -in decode -legal > legal.e
1510 : // 2) espresso -Dso -oeqntott < legal.e | addassign -pre out. > legal
1511 : // 3) copy-paste assignment from the file "legal" and replace the one below.
1512 :
1513 : module el2_dec_dec_ctl
1514 : import el2_pkg::*;
1515 : (
1516 468714 : input logic [31:0] inst,
1517 7440 : output el2_dec_pkt_t out
1518 : );
1519 :
1520 468714 : logic [31:0] i;
1521 :
1522 : assign i[31:0] = inst[31:0];
1523 :
1524 : assign out.alu = (i[30]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]&!i[5]&i[4]) | (i[30]
1525 : &!i[27]&!i[24]&i[4]) | (!i[30]&!i[25]&i[13]&i[12]) | (!i[29]&!i[27]
1526 : &!i[5]&i[4]) | (i[27]&i[25]&i[14]&i[4]) | (!i[29]&!i[25]&!i[13]&!i[12]
1527 : &i[4]) | (i[29]&i[27]&!i[14]&i[12]&i[4]) | (!i[27]&i[14]&!i[5]&i[4]) | (
1528 : i[30]&!i[29]&!i[13]&i[4]) | (!i[27]&!i[25]&i[5]&i[4]) | (i[13]&!i[5]
1529 : &i[4]) | (i[6]) | (!i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]&i[20]&!i[5]
1530 : &i[4]) | (i[2]) | (!i[12]&!i[5]&i[4]);
1531 :
1532 : assign out.rs1 = (!i[13]&i[11]&!i[2]) | (!i[13]&i[10]&!i[2]) | (i[19]&i[13]&!i[2]) | (
1533 : !i[13]&i[9]&!i[2]) | (i[18]&i[13]&!i[2]) | (!i[13]&i[8]&!i[2]) | (
1534 : i[17]&i[13]&!i[2]) | (!i[13]&i[7]&!i[2]) | (i[16]&i[13]&!i[2]) | (
1535 : i[15]&i[13]&!i[2]) | (!i[4]&!i[2]) | (!i[14]&!i[13]&i[6]&!i[3]) | (
1536 : !i[6]&!i[2]);
1537 :
1538 : assign out.rs2 = (i[5] & !i[4] & !i[2]) | (!i[6] & i[5] & !i[2]);
1539 :
1540 : assign out.imm12 = (!i[4]&!i[3]&i[2]) | (i[13]&!i[5]&i[4]&!i[2]) | (!i[13]&!i[12]
1541 : &i[6]&i[4]) | (!i[12]&!i[5]&i[4]&!i[2]);
1542 :
1543 : assign out.rd = (!i[5] & !i[2]) | (i[5] & i[2]) | (i[4]);
1544 :
1545 : assign out.shimm5 = (!i[29]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[13]&i[12]
1546 : &!i[5]&i[4]&!i[2]) | (i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1547 :
1548 : assign out.imm20 = (i[5] & i[3]) | (i[4] & i[2]);
1549 :
1550 : assign out.pc = (!i[5] & !i[3] & i[2]) | (i[5] & i[3]);
1551 :
1552 : assign out.load = (!i[5] & !i[4] & !i[2]);
1553 :
1554 : assign out.store = (!i[6] & i[5] & !i[4]);
1555 :
1556 : assign out.lsu = (!i[6] & !i[4] & !i[2]);
1557 :
1558 : assign out.add = (!i[14]&!i[13]&!i[12]&!i[5]&i[4]) | (!i[5]&!i[3]&i[2]) | (!i[30]
1559 : &!i[25]&!i[14]&!i[13]&!i[12]&!i[6]&i[4]&!i[2]);
1560 :
1561 : assign out.sub = (i[30]&!i[14]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[29]&!i[25]&!i[14]
1562 : &i[13]&!i[6]&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]) | (
1563 : !i[14]&i[13]&!i[5]&i[4]&!i[2]) | (i[6]&!i[4]&!i[2]);
1564 :
1565 : assign out.land = (!i[27]&!i[25]&i[14]&i[13]&i[12]&!i[6]&!i[2]) | (i[14]&i[13]&i[12]
1566 : &!i[5]&!i[2]);
1567 :
1568 : assign out.lor = (!i[29]&!i[27]&!i[25]&i[14]&i[13]&!i[12]&!i[6]&!i[2]) | (!i[6]&i[3]) | (
1569 : i[5]&i[4]&i[2]) | (!i[13]&!i[12]&i[6]&i[4]) | (i[14]&i[13]&!i[12]
1570 : &!i[5]&!i[2]);
1571 :
1572 : assign out.lxor = (!i[29]&!i[27]&!i[25]&i[14]&!i[13]&!i[12]&i[4]&!i[2]) | (i[14]
1573 : &!i[13]&!i[12]&!i[5]&i[4]&!i[2]);
1574 :
1575 : assign out.sll = (!i[29] & !i[27] & !i[25] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1576 :
1577 : assign out.sra = (i[30] & !i[29] & !i[27] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1578 :
1579 : assign out.srl = (!i[30] & !i[27] & !i[25] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1580 :
1581 : assign out.slt = (!i[29]&!i[25]&!i[14]&i[13]&!i[6]&i[4]&!i[2]) | (!i[14]&i[13]&!i[5]
1582 : &i[4]&!i[2]);
1583 :
1584 : assign out.unsign = (!i[14]&i[13]&i[12]&!i[5]&!i[2]) | (i[13]&i[6]&!i[4]&!i[2]) | (
1585 : i[14]&!i[5]&!i[4]) | (!i[25]&!i[14]&i[13]&i[12]&!i[6]&!i[2]) | (
1586 : i[25]&i[14]&i[12]&!i[6]&i[5]&!i[2]);
1587 :
1588 : assign out.condbr = (i[6] & !i[4] & !i[2]);
1589 :
1590 : assign out.beq = (!i[14] & !i[12] & i[6] & !i[4] & !i[2]);
1591 :
1592 : assign out.bne = (!i[14] & i[12] & i[6] & !i[4] & !i[2]);
1593 :
1594 : assign out.bge = (i[14] & i[12] & i[5] & !i[4] & !i[2]);
1595 :
1596 : assign out.blt = (i[14] & !i[12] & i[5] & !i[4] & !i[2]);
1597 :
1598 : assign out.jal = (i[6] & i[2]);
1599 :
1600 : assign out.by = (!i[13] & !i[12] & !i[6] & !i[4] & !i[2]);
1601 :
1602 : assign out.half = (i[12] & !i[6] & !i[4] & !i[2]);
1603 :
1604 : assign out.word = (i[13] & !i[6] & !i[4]);
1605 :
1606 : assign out.csr_read = (i[13]&i[6]&i[4]) | (i[7]&i[6]&i[4]) | (i[8]&i[6]&i[4]) | (
1607 : i[9]&i[6]&i[4]) | (i[10]&i[6]&i[4]) | (i[11]&i[6]&i[4]);
1608 :
1609 : assign out.csr_clr = (i[15]&i[13]&i[12]&i[6]&i[4]) | (i[16]&i[13]&i[12]&i[6]&i[4]) | (
1610 : i[17]&i[13]&i[12]&i[6]&i[4]) | (i[18]&i[13]&i[12]&i[6]&i[4]) | (
1611 : i[19]&i[13]&i[12]&i[6]&i[4]);
1612 :
1613 : assign out.csr_set = (i[15]&!i[12]&i[6]&i[4]) | (i[16]&!i[12]&i[6]&i[4]) | (i[17]
1614 : &!i[12]&i[6]&i[4]) | (i[18]&!i[12]&i[6]&i[4]) | (i[19]&!i[12]&i[6]
1615 : &i[4]);
1616 :
1617 : assign out.csr_write = (!i[13] & i[12] & i[6] & i[4]);
1618 :
1619 : assign out.csr_imm = (i[14]&!i[13]&i[6]&i[4]) | (i[15]&i[14]&i[6]&i[4]) | (i[16]
1620 : &i[14]&i[6]&i[4]) | (i[17]&i[14]&i[6]&i[4]) | (i[18]&i[14]&i[6]&i[4]) | (
1621 : i[19]&i[14]&i[6]&i[4]);
1622 :
1623 : assign out.presync = (!i[5]&i[3]) | (!i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&i[4]) | (
1624 : !i[13]&i[9]&i[6]&i[4]) | (!i[13]&i[10]&i[6]&i[4]) | (!i[13]&i[11]
1625 : &i[6]&i[4]) | (i[15]&i[13]&i[6]&i[4]) | (i[16]&i[13]&i[6]&i[4]) | (
1626 : i[17]&i[13]&i[6]&i[4]) | (i[18]&i[13]&i[6]&i[4]) | (i[19]&i[13]&i[6]
1627 : &i[4]);
1628 :
1629 : assign out.postsync = (!i[22]&!i[13]&!i[12]&i[6]&i[4]) | (i[12]&!i[5]&i[3]) | (
1630 : !i[13]&i[7]&i[6]&i[4]) | (!i[13]&i[8]&i[6]&i[4]) | (!i[13]&i[9]&i[6]
1631 : &i[4]) | (!i[13]&i[10]&i[6]&i[4]) | (!i[13]&i[11]&i[6]&i[4]) | (
1632 : i[15]&i[13]&i[6]&i[4]) | (i[16]&i[13]&i[6]&i[4]) | (i[17]&i[13]&i[6]
1633 : &i[4]) | (i[18]&i[13]&i[6]&i[4]) | (i[19]&i[13]&i[6]&i[4]);
1634 :
1635 : assign out.ebreak = (!i[22] & i[20] & !i[13] & !i[12] & i[6] & i[4]);
1636 :
1637 : assign out.ecall = (!i[21] & !i[20] & !i[13] & !i[12] & i[6] & i[4]);
1638 :
1639 : assign out.mret = (i[29] & !i[13] & !i[12] & i[6] & i[4]);
1640 :
1641 : assign out.mul = (i[29]&!i[27]&i[24]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30]
1642 : &i[27]&i[13]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[23]&!i[20]
1643 : &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[21]&i[20]
1644 : &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&i[24]&i[21]
1645 : &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[24]&!i[22]
1646 : &i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (!i[30]&i[29]&i[23]&i[14]
1647 : &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[30]&i[29]&i[27]&i[22]&i[14]
1648 : &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&!i[25]&i[13]&!i[12]&!i[6]
1649 : &i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6]
1650 : &i[4]&!i[2]) | (i[25]&!i[14]&!i[6]&i[5]&i[4]&!i[2]) | (i[29]&i[27]
1651 : &i[14]&!i[6]&i[5]&!i[2]);
1652 :
1653 : assign out.rs1_sign = (!i[27]&i[25]&!i[14]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]) | (
1654 : !i[27]&i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
1655 :
1656 : assign out.rs2_sign = (!i[27] & i[25] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1657 :
1658 : assign out.low = (i[25] & !i[14] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);
1659 :
1660 : assign out.div = (!i[27] & i[25] & i[14] & !i[6] & i[5] & !i[2]);
1661 :
1662 : assign out.rem = (!i[27] & i[25] & i[14] & i[13] & !i[6] & i[5] & !i[2]);
1663 :
1664 : assign out.fence = (!i[5] & i[3]);
1665 :
1666 : assign out.fence_i = (i[12] & !i[5] & i[3]);
1667 :
1668 : assign out.clz = (i[29]&!i[27]&!i[24]&!i[22]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]
1669 : &i[4]&!i[2]);
1670 :
1671 : assign out.ctz = (i[29]&!i[27]&!i[24]&!i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]
1672 : &!i[2]);
1673 :
1674 : assign out.cpop = (i[29]&!i[27]&!i[24]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1675 :
1676 : assign out.sext_b = (i[29]&!i[27]&i[22]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1677 :
1678 : assign out.sext_h = (i[29]&!i[27]&i[22]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1679 :
1680 : assign out.min = (i[27] & i[25] & i[14] & !i[13] & !i[6] & i[5] & !i[2]);
1681 :
1682 : assign out.max = (i[27] & i[25] & i[14] & i[13] & !i[6] & i[5] & !i[2]);
1683 :
1684 : assign out.pack = (!i[30] & !i[29] & i[27] & !i[25] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);
1685 :
1686 : assign out.packu = (i[30] & i[27] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);
1687 :
1688 : assign out.packh = (!i[30] & i[27] & !i[25] & i[13] & i[12] & !i[6] & i[5] & !i[2]);
1689 :
1690 : assign out.rol = (i[29] & !i[27] & !i[14] & i[12] & !i[6] & i[5] & i[4] & !i[2]);
1691 :
1692 : assign out.ror = (i[29] & !i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1693 :
1694 : assign out.zbb = (!i[30]&!i[29]&i[27]&!i[24]&!i[23]&!i[22]&!i[21]&!i[20]&!i[13]
1695 : &!i[12]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&!i[24]&!i[13]&i[12]&!i[5]
1696 : &i[4]&!i[2]) | (i[29]&!i[27]&i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (
1697 : i[30]&!i[27]&i[14]&!i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13]
1698 : &!i[6]&i[5]&i[4]&!i[2]) | (i[29]&!i[27]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | (
1699 : !i[30]&i[29]&!i[24]&!i[23]&i[22]&i[21]&i[20]&i[14]&!i[13]&i[12]&!i[5]
1700 : &i[4]&!i[2]) | (i[30]&i[29]&i[24]&i[23]&!i[22]&!i[21]&!i[20]&i[14]
1701 : &!i[13]&i[12]&!i[5]&i[4]&!i[2]) | (i[27]&i[25]&i[14]&!i[6]&i[5]&!i[2]);
1702 :
1703 : assign out.bset = (!i[30] & i[29] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1704 :
1705 : assign out.bclr = (i[30] & !i[29] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1706 :
1707 : assign out.binv = (i[30] & i[29] & i[27] & !i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1708 :
1709 : assign out.bext = (i[30] & !i[29] & i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1710 :
1711 : assign out.zbs = (i[29]&i[27]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]) | (i[30]&!i[29]
1712 : &i[27]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
1713 :
1714 : assign out.bcompress = (!i[30]&!i[29]&i[27]&!i[25]&i[13]&!i[12]&!i[6]&i[5]&i[4]&!i[2]);
1715 :
1716 : assign out.bdecompress = (i[30] & i[27] & i[13] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);
1717 :
1718 : assign out.zbe = (i[30]&i[27]&i[14]&i[13]&!i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&i[27]
1719 : &!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]
1720 : &!i[12]&!i[6]&i[5]&i[4]&!i[2]);
1721 :
1722 : assign out.clmul = (i[27] & i[25] & !i[14] & !i[13] & !i[6] & i[5] & i[4] & !i[2]);
1723 :
1724 : assign out.clmulh = (i[27] & !i[14] & i[13] & i[12] & !i[6] & i[5] & !i[2]);
1725 :
1726 : assign out.clmulr = (i[27] & i[25] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);
1727 :
1728 : assign out.zbc = (i[27] & i[25] & !i[14] & !i[6] & i[5] & i[4] & !i[2]);
1729 :
1730 : assign out.grev = (i[30] & i[29] & i[27] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1731 :
1732 : assign out.gorc = (!i[30] & i[29] & i[14] & !i[13] & i[12] & !i[6] & i[4] & !i[2]);
1733 :
1734 : assign out.shfl = (!i[30]&!i[29]&i[27]&!i[25]&!i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
1735 :
1736 : assign out.unshfl = (!i[30]&!i[29]&i[27]&!i[25]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
1737 :
1738 : assign out.xperm_n = (i[29] & i[27] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);
1739 :
1740 : assign out.xperm_b = (i[29] & i[27] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);
1741 :
1742 : assign out.xperm_h = (i[29] & i[27] & i[14] & i[13] & !i[6] & i[5] & !i[2]);
1743 :
1744 : assign out.zbp = (i[30]&!i[27]&!i[14]&i[12]&!i[6]&i[5]&i[4]&!i[2]) | (!i[30]&i[27]
1745 : &!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]) | (i[30]&!i[27]&i[13]&!i[6]
1746 : &i[5]&i[4]&!i[2]) | (i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (
1747 : i[30]&i[14]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (i[29]&i[27]&!i[12]&!i[6]
1748 : &i[5]&i[4]&!i[2]) | (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&i[12]&!i[6]
1749 : &i[4]&!i[2]) | (i[29]&i[14]&!i[13]&i[12]&!i[6]&i[4]&!i[2]);
1750 :
1751 : assign out.crc32_b = (i[29]&!i[27]&i[24]&!i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]
1752 : &!i[5]&i[4]&!i[2]);
1753 :
1754 : assign out.crc32_h = (i[29]&!i[27]&i[24]&!i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]
1755 : &!i[2]);
1756 :
1757 : assign out.crc32_w = (i[29]&!i[27]&i[24]&!i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]
1758 : &!i[2]);
1759 :
1760 : assign out.crc32c_b = (i[29]&!i[27]&i[23]&!i[21]&!i[20]&!i[14]&!i[13]&i[12]&!i[5]
1761 : &i[4]&!i[2]);
1762 :
1763 : assign out.crc32c_h = (i[29]&!i[27]&i[23]&i[20]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1764 :
1765 : assign out.crc32c_w = (i[29]&!i[27]&i[23]&i[21]&!i[14]&!i[13]&i[12]&!i[5]&i[4]&!i[2]);
1766 :
1767 : assign out.zbr = (i[29] & !i[27] & i[24] & !i[14] & !i[13] & i[12] & !i[5] & i[4] & !i[2]);
1768 :
1769 : assign out.bfp = (i[30] & i[27] & i[13] & i[12] & !i[6] & i[5] & !i[2]);
1770 :
1771 : assign out.zbf = (!i[30]&!i[29]&i[27]&!i[25]&!i[13]&!i[12]&i[5]&i[4]&!i[2]) | (
1772 : i[27]&!i[25]&i[13]&i[12]&!i[6]&i[5]&!i[2]);
1773 :
1774 : assign out.sh1add = (i[29] & !i[27] & !i[14] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);
1775 :
1776 : assign out.sh2add = (i[29] & !i[27] & i[14] & !i[13] & !i[12] & i[5] & i[4] & !i[2]);
1777 :
1778 : assign out.sh3add = (i[29] & !i[27] & i[14] & i[13] & !i[6] & i[5] & !i[2]);
1779 :
1780 : assign out.zba = (i[29] & !i[27] & !i[12] & !i[6] & i[5] & i[4] & !i[2]);
1781 :
1782 : assign out.pm_alu = (i[28]&i[20]&!i[13]&!i[12]&i[4]) | (!i[30]&!i[29]&!i[27]&!i[25]
1783 : &!i[6]&i[4]) | (!i[29]&!i[27]&!i[25]&!i[13]&i[12]&!i[6]&i[4]) | (
1784 : !i[29]&!i[27]&!i[25]&!i[14]&!i[6]&i[4]) | (i[13]&!i[5]&i[4]) | (i[4]
1785 : &i[2]) | (!i[12]&!i[5]&i[4]);
1786 :
1787 :
1788 : assign out.legal = (!i[31]&!i[30]&i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]
1789 : &!i[22]&i[21]&!i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]
1790 : &!i[10]&!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (
1791 : !i[31]&!i[30]&!i[29]&i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&i[22]
1792 : &!i[21]&i[20]&!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10]
1793 : &!i[9]&!i[8]&!i[7]&i[6]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]
1794 : &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[24]&!i[23]&!i[22]&!i[21]
1795 : &!i[19]&!i[18]&!i[17]&!i[16]&!i[15]&!i[14]&!i[11]&!i[10]&!i[9]&!i[8]
1796 : &!i[7]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]
1797 : &!i[26]&!i[25]&i[24]&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (
1798 : !i[31]&i[30]&i[29]&!i[28]&!i[26]&!i[25]&i[24]&!i[22]&!i[21]&!i[6]
1799 : &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[30]&i[29]&!i[28]&!i[26]
1800 : &!i[25]&!i[23]&!i[22]&!i[20]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (
1801 : !i[31]&i[30]&i[29]&!i[28]&!i[26]&!i[25]&!i[24]&!i[23]&!i[21]&!i[6]
1802 : &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[26]
1803 : &i[25]&i[13]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[28]&i[27]&!i[26]
1804 : &!i[25]&!i[24]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]
1805 : &i[29]&!i[28]&!i[26]&!i[25]&i[13]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (
1806 : !i[31]&!i[29]&!i[28]&!i[27]&!i[26]&!i[25]&!i[13]&!i[12]&!i[6]&i[4]
1807 : &!i[3]&i[1]&i[0]) | (!i[31]&i[30]&!i[28]&!i[26]&!i[25]&i[14]&!i[6]
1808 : &!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]&!i[28]&!i[26]
1809 : &!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[29]
1810 : &!i[28]&!i[27]&!i[26]&!i[25]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]
1811 : &i[30]&i[29]&!i[28]&!i[26]&!i[25]&!i[13]&i[12]&i[5]&i[4]&!i[3]&!i[2]
1812 : &i[1]&i[0]) | (!i[31]&i[30]&!i[28]&i[27]&!i[26]&!i[25]&!i[13]&i[12]
1813 : &!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&!i[29]&!i[28]&!i[26]&!i[25]
1814 : &i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]&i[29]&!i[28]&i[27]
1815 : &!i[26]&!i[25]&!i[13]&i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[31]
1816 : &!i[30]&!i[29]&!i[28]&!i[27]&!i[26]&!i[6]&i[5]&i[4]&!i[3]&i[1]&i[0]) | (
1817 : !i[31]&!i[30]&!i[29]&!i[28]&!i[26]&i[14]&!i[6]&i[5]&i[4]&!i[3]&i[1]
1818 : &i[0]) | (!i[14]&!i[13]&!i[12]&i[6]&i[5]&!i[4]&!i[3]&i[1]&i[0]) | (
1819 : i[14]&i[6]&i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[14]&!i[13]&i[5]
1820 : &!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[12]&!i[6]&!i[5]&i[4]&!i[3]&i[1]
1821 : &i[0]) | (!i[13]&i[12]&i[6]&i[5]&!i[3]&!i[2]&i[1]&i[0]) | (i[13]&i[6]
1822 : &i[5]&i[4]&!i[3]&!i[2]&i[1]&i[0]) | (!i[30]&!i[29]&!i[28]&!i[14]
1823 : &!i[13]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[31]&!i[30]&!i[28]
1824 : &!i[26]&!i[25]&i[14]&!i[12]&!i[6]&i[4]&!i[3]&i[1]&i[0]) | (!i[14]
1825 : &!i[13]&i[12]&!i[6]&!i[5]&!i[4]&i[3]&i[2]&i[1]&i[0]) | (i[6]&i[5]
1826 : &!i[4]&i[3]&i[2]&i[1]&i[0]) | (!i[14]&!i[12]&!i[6]&!i[4]&!i[3]&!i[2]
1827 : &i[1]&i[0]) | (!i[13]&!i[6]&!i[5]&!i[4]&!i[3]&!i[2]&i[1]&i[0]) | (
1828 : i[13]&!i[6]&!i[5]&i[4]&!i[3]&i[1]&i[0]) | (!i[6]&i[4]&!i[3]&i[2]&i[1]
1829 : &i[0]);
1830 :
1831 : endmodule // el2_dec_dec_ctl
|
