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Current view: Cores-VeeR-EL2—Cores-VeeR-EL2—design—dec—el2_dec.sv Coverage Hit Total
Test Date: 21-11-2024 Toggle 85.5% 219 256
Test: all Branch 0.0% 0 0

            Line data    Source code
       1              : // SPDX-License-Identifier: Apache-2.0
       2              : // Copyright 2020 Western Digital Corporation or its affiliates.
       3              : //
       4              : // Licensed under the Apache License, Version 2.0 (the "License");
       5              : // you may not use this file except in compliance with the License.
       6              : // You may obtain a copy of the License at
       7              : //
       8              : // http://www.apache.org/licenses/LICENSE-2.0
       9              : //
      10              : // Unless required by applicable law or agreed to in writing, software
      11              : // distributed under the License is distributed on an "AS IS" BASIS,
      12              : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
      13              : // See the License for the specific language governing permissions and
      14              : // limitations under the License.
      15              : 
      16              : // dec: decode unit - decode, bypassing, ARF, interrupts
      17              : //
      18              : //********************************************************************************
      19              : // $Id$
      20              : //
      21              : //
      22              : // Function: Decode
      23              : // Comments: Decode, dependency scoreboard, ARF
      24              : //
      25              : //
      26              : // A -> D -> EX1 ... WB
      27              : //
      28              : //********************************************************************************
      29              : 
      30              : module el2_dec
      31              :   import el2_pkg::*;
      32              : #(
      33              :     `include "el2_param.vh"
      34              : ) (
      35     69840565 :     input logic clk,                          // Clock only while core active.  Through one clock header.  For flops with    second clock header built in.  Connected to ACTIVE_L2CLK.
      36     69840565 :     input logic active_clk,                   // Clock only while core active.  Through two clock headers. For flops without second clock header built in.
      37     69840565 :     input logic free_clk,                     // Clock always.                  Through two clock headers. For flops without second clock header built in.
      38     69840565 :     input logic free_l2clk,                   // Clock always.                  Through one clock header.  For flops with    second header built in.
      39              : 
      40            4 :     input logic lsu_fastint_stall_any,        // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
      41              : 
      42            0 :     output logic dec_extint_stall,  // Stall on external interrupt
      43              : 
      44      6195679 :     output logic dec_i0_decode_d,    // Valid instruction at D-stage and not blocked
      45            2 :     output logic dec_pause_state_cg, // to top for active state clock gating
      46              : 
      47      2090538 :     output logic dec_tlu_core_empty,
      48              : 
      49          338 :     input logic        rst_l,   // reset, active low
      50            0 :     input logic [31:1] rst_vec, // reset vector, from core pins
      51              : 
      52            4 :     input logic        nmi_int,  // NMI pin
      53           16 :     input logic [31:1] nmi_vec,  // NMI vector, from pins
      54              : 
      55          108 :     input logic i_cpu_halt_req,  // Asynchronous Halt request to CPU
      56          108 :     input logic i_cpu_run_req,   // Asynchronous Restart request to CPU
      57              : 
      58          108 :     output logic o_cpu_halt_status,  // Halt status of core (pmu/fw)
      59          108 :     output logic o_cpu_halt_ack,  // Halt request ack
      60          108 :     output logic o_cpu_run_ack,  // Run request ack
      61          118 :     output logic o_debug_mode_status,         // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
      62              : 
      63            0 :     input logic [31:4] core_id,  // CORE ID
      64              : 
      65              :     // external MPC halt/run interface
      66          108 :     input  logic mpc_debug_halt_req,  // Async halt request
      67          108 :     input  logic mpc_debug_run_req,   // Async run request
      68          338 :     input  logic mpc_reset_run_req,   // Run/halt after reset
      69          108 :     output logic mpc_debug_halt_ack,  // Halt ack
      70          108 :     output logic mpc_debug_run_ack,   // Run ack
      71            2 :     output logic debug_brkpt_status,  // debug breakpoint
      72              : 
      73       410552 :     input logic exu_pmu_i0_br_misp,    // slot 0 branch misp
      74      2911037 :     input logic exu_pmu_i0_br_ataken,  // slot 0 branch actual taken
      75      3495269 :     input logic exu_pmu_i0_pc4,        // slot 0 4 byte branch
      76              : 
      77              : 
      78       880628 :     input logic lsu_nonblock_load_valid_m,  // valid nonblock load at m
      79       504631 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_tag_m,  // -> corresponding tag
      80            0 :     input logic lsu_nonblock_load_inv_r,  // invalidate request for nonblock load r
      81       504628 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_inv_tag_r,  // -> corresponding tag
      82       919880 :     input logic lsu_nonblock_load_data_valid,  // valid nonblock load data back
      83            2 :     input logic lsu_nonblock_load_data_error,  // nonblock load bus error
      84        36606 :     input logic [pt.LSU_NUM_NBLOAD_WIDTH-1:0] lsu_nonblock_load_data_tag,  // -> corresponding tag
      85        71598 :     input logic [31:0] lsu_nonblock_load_data,  // nonblock load data
      86              : 
      87      1673139 :     input logic lsu_pmu_bus_trxn,          // D side bus transaction
      88        36422 :     input logic lsu_pmu_bus_misaligned,    // D side bus misaligned
      89            4 :     input logic lsu_pmu_bus_error,         // D side bus error
      90        67742 :     input logic lsu_pmu_bus_busy,          // D side bus busy
      91        48802 :     input logic lsu_pmu_misaligned_m,      // D side load or store misaligned
      92       890738 :     input logic lsu_pmu_load_external_m,   // D side bus load
      93       812872 :     input logic lsu_pmu_store_external_m,  // D side bus store
      94            0 :     input logic dma_pmu_dccm_read,         // DMA DCCM read
      95            0 :     input logic dma_pmu_dccm_write,        // DMA DCCM write
      96            0 :     input logic dma_pmu_any_read,          // DMA read
      97           66 :     input logic dma_pmu_any_write,         // DMA write
      98              : 
      99        24696 :     input logic [31:1] lsu_fir_addr,  // Fast int address
     100            0 :     input logic [ 1:0] lsu_fir_error, // Fast int lookup error
     101              : 
     102      6195679 :     input logic ifu_pmu_instr_aligned,  // aligned instructions
     103       614908 :     input logic ifu_pmu_fetch_stall,    // fetch unit stalled
     104      5888394 :     input logic ifu_pmu_ic_miss,        // icache miss
     105       745248 :     input logic ifu_pmu_ic_hit,         // icache hit
     106            8 :     input logic ifu_pmu_bus_error,      // Instruction side bus error
     107      4461583 :     input logic ifu_pmu_bus_busy,       // Instruction side bus busy
     108     10349957 :     input logic ifu_pmu_bus_trxn,       // Instruction side bus transaction
     109              : 
     110            0 :     input logic ifu_ic_error_start,         // IC single bit error
     111            8 :     input logic ifu_iccm_rd_ecc_single_err, // ICCM single bit error
     112              : 
     113            0 :     input logic [ 3:0] lsu_trigger_match_m,
     114         2562 :     input logic        dbg_cmd_valid,        // debugger abstract command valid
     115          300 :     input logic        dbg_cmd_write,        // command is a write
     116         1456 :     input logic [ 1:0] dbg_cmd_type,         // command type
     117           14 :     input logic [31:0] dbg_cmd_addr,         // command address
     118          596 :     input logic [ 1:0] dbg_cmd_wrdata,       // command write data, for fence/fence_i
     119              : 
     120              : 
     121          206 :     input logic       ifu_i0_icaf,      // icache access fault
     122          274 :     input logic [1:0] ifu_i0_icaf_type, // icache access fault type
     123              : 
     124           86 :     input logic ifu_i0_icaf_second,  // i0 has access fault on second 2B of 4B inst
     125            2 :     input logic ifu_i0_dbecc,        // icache/iccm double-bit error
     126              : 
     127      1345827 :     input logic lsu_idle_any,  // lsu idle for halting
     128              : 
     129       206055 :     input el2_br_pkt_t                                 i0_brp,           // branch packet
     130       651059 :     input logic        [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] ifu_i0_bp_index,  // BP index
     131       628591 :     input logic        [          pt.BHT_GHR_SIZE-1:0] ifu_i0_bp_fghr,   // BP FGHR
     132        21223 :     input logic        [         pt.BTB_BTAG_SIZE-1:0] ifu_i0_bp_btag,   // BP tag
     133            0 :     input logic        [      $clog2(pt.BTB_SIZE)-1:0] ifu_i0_fa_index,  // Fully associt btb index
     134              : 
     135            4 :     input el2_lsu_error_pkt_t lsu_error_pkt_r,           // LSU exception/error packet
     136            4 :     input logic               lsu_single_ecc_error_incr, // LSU inc SB error counter
     137              : 
     138            2 :     input logic        lsu_imprecise_error_load_any,   // LSU imprecise load bus error
     139            2 :     input logic        lsu_imprecise_error_store_any,  // LSU imprecise store bus error
     140          292 :     input logic [31:0] lsu_imprecise_error_addr_any,   // LSU imprecise bus error address
     141              : 
     142        24784 :     input logic [31:0] exu_div_result,  // final div result
     143       156852 :     input logic        exu_div_wren,    // Divide write enable to GPR
     144              : 
     145         3978 :     input logic [31:0] exu_csr_rs1_x,  // rs1 for csr instruction
     146              : 
     147        45313 :     input logic [31:0] lsu_result_m,      // load result
     148        36052 :     input logic [31:0] lsu_result_corr_r, // load result - corrected load data
     149              : 
     150        48806 :     input logic lsu_load_stall_any,   // This is for blocking loads
     151        59130 :     input logic lsu_store_stall_any,  // This is for blocking stores
     152            0 :     input logic dma_dccm_stall_any,   // stall any load/store at decode, pmu event
     153           26 :     input logic dma_iccm_stall_any,   // iccm stalled, pmu event
     154              : 
     155            0 :     input logic iccm_dma_sb_error,  // ICCM DMA single bit error
     156              : 
     157       673974 :     input logic exu_flush_final,  // slot0 flush
     158              : 
     159          344 :     input logic [31:1] exu_npc_r,  // next PC
     160              : 
     161       614539 :     input logic [31:0] exu_i0_result_x,  // alu result x
     162              : 
     163              : 
     164      6010401 :     input logic        ifu_i0_valid,  // fetch valids to instruction buffer
     165       468702 :     input logic [31:0] ifu_i0_instr,  // fetch inst's to instruction buffer
     166         1321 :     input logic [31:1] ifu_i0_pc,     // pc's for instruction buffer
     167      5770511 :     input logic        ifu_i0_pc4,    // indication of 4B or 2B for corresponding inst
     168          339 :     input logic [31:1] exu_i0_pc_x,   // pc's for e1 from the alu's
     169              : 
     170            0 :     input logic mexintpend,  // External interrupt pending
     171           15 :     input logic timer_int,   // Timer interrupt pending (from pin)
     172           17 :     input logic soft_int,    // Software interrupt pending (from pin)
     173              : 
     174            0 :     input logic [7:0] pic_claimid,  // PIC claimid
     175            0 :     input logic [3:0] pic_pl,       // PIC priv level
     176            0 :     input logic       mhwakeup,     // High priority wakeup
     177              : 
     178            0 :     output logic [3:0] dec_tlu_meicurpl,  // to PIC, Current priv level
     179            0 :     output logic [3:0] dec_tlu_meipt,     // to PIC
     180              : 
     181            0 :     input logic [70:0] ifu_ic_debug_rd_data,  // diagnostic icache read data
     182           20 :     input logic ifu_ic_debug_rd_data_valid,  // diagnostic icache read data valid
     183            0 :     output el2_cache_debug_pkt_t dec_tlu_ic_diag_pkt, // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
     184              : 
     185              : 
     186              :     // Debug start
     187            8 :     input logic dbg_halt_req,        // DM requests a halt
     188           10 :     input logic dbg_resume_req,      // DM requests a resume
     189      5887400 :     input logic ifu_miss_state_idle, // I-side miss buffer empty
     190              : 
     191          120 :     output logic        dec_tlu_dbg_halted,        // Core is halted and ready for debug command
     192          118 :     output logic        dec_tlu_debug_mode,        // Core is in debug mode
     193           10 :     output logic        dec_tlu_resume_ack,        // Resume acknowledge
     194          232 :     output logic        dec_tlu_flush_noredir_r,   // Tell fetch to idle on this flush
     195          108 :     output logic        dec_tlu_mpc_halted_only,   // Core is halted only due to MPC
     196            2 :     output logic        dec_tlu_flush_leak_one_r,  // single step
     197            8 :     output logic        dec_tlu_flush_err_r,       // iside perr/ecc rfpc
     198            0 :     output logic [31:2] dec_tlu_meihap,            // Fast ext int base
     199              : 
     200          168 :     output logic dec_debug_wdata_rs1_d,  // insert debug write data into rs1 at decode
     201              : 
     202       314101 :     output logic [31:0] dec_dbg_rddata,  // debug command read data
     203              : 
     204         2558 :     output logic dec_dbg_cmd_done,  // abstract command is done
     205            0 :     output logic dec_dbg_cmd_fail,  // abstract command failed (illegal reg address)
     206              : 
     207            0 :     output el2_trigger_pkt_t [3:0] trigger_pkt_any,  // info needed by debug trigger blocks
     208              : 
     209            0 :     output logic       dec_tlu_force_halt,       // halt has been forced
     210              :     // Debug end
     211              :     // branch info from pipe0 for errors or counter updates
     212      2721663 :     input  logic [1:0] exu_i0_br_hist_r,         // history
     213        26468 :     input  logic       exu_i0_br_error_r,        // error
     214         9608 :     input  logic       exu_i0_br_start_error_r,  // start error
     215      3012693 :     input  logic       exu_i0_br_valid_r,        // valid
     216       410552 :     input  logic       exu_i0_br_mp_r,           // mispredict
     217      2380332 :     input  logic       exu_i0_br_middle_r,       // middle of bank
     218              : 
     219              :     // branch info from pipe1 for errors or counter updates
     220              : 
     221      2110720 :     input logic exu_i0_br_way_r,  // way hit or repl
     222              : 
     223      5134863 :     output logic        dec_i0_rs1_en_d,  // Qualify GPR RS1 data
     224      3569581 :     output logic        dec_i0_rs2_en_d,  // Qualify GPR RS2 data
     225       407934 :     output logic [31:0] gpr_i0_rs1_d,     // gpr rs1 data
     226       598866 :     output logic [31:0] gpr_i0_rs2_d,     // gpr rs2 data
     227              : 
     228      2170592 :     output logic [31:0] dec_i0_immed_d,    // immediate data
     229       123462 :     output logic [12:1] dec_i0_br_immed_d, // br immediate data
     230              : 
     231         1460 :     output el2_alu_pkt_t i0_ap,  // alu packet
     232              : 
     233      5407994 :     output logic dec_i0_alu_decode_d,  // schedule on D-stage alu
     234      3883757 :     output logic dec_i0_branch_d,      // Branch in D-stage
     235              : 
     236       555609 :     output logic dec_i0_select_pc_d,  // select pc onto rs1 for jal's
     237              : 
     238         1321 :     output logic [31:1] dec_i0_pc_d,             // pc's at decode
     239        80402 :     output logic [ 3:0] dec_i0_rs1_bypass_en_d,  // rs1 bypass enable
     240         8620 :     output logic [ 3:0] dec_i0_rs2_bypass_en_d,  // rs2 bypass enable
     241              : 
     242       314101 :     output logic [31:0] dec_i0_result_r,  // Result R-stage
     243              : 
     244       623587 :     output el2_lsu_pkt_t lsu_p,           // lsu packet
     245      5490327 :     output logic         dec_qual_lsu_d,  // LSU instruction at D.  Use to quiet LSU operands
     246            0 :     output el2_mul_pkt_t mul_p,           // mul packet
     247        78130 :     output el2_div_pkt_t div_p,           // div packet
     248         2628 :     output logic         dec_div_cancel,  // cancel divide operation
     249              : 
     250       270374 :     output logic [11:0] dec_lsu_offset_d,  // 12b offset for load/store addresses
     251              : 
     252        77278 :     output logic        dec_csr_ren_d,    // CSR read enable
     253         7157 :     output logic [31:0] dec_csr_rddata_d, // CSR read data
     254              : 
     255        59220 :     output logic dec_tlu_flush_lower_r,  // tlu flush due to late mp, exception, rfpc, or int
     256        59220 :     output logic dec_tlu_flush_lower_wb,
     257        24762 :     output logic [31:1] dec_tlu_flush_path_r,  // tlu flush target
     258        29688 :     output logic        dec_tlu_i0_kill_writeb_r,    // I0 is flushed, don't writeback any results to arch state
     259        18868 :     output logic dec_tlu_fence_i_r,  // flush is a fence_i rfnpc, flush icache
     260              : 
     261       138906 :     output logic [31:1] pred_correct_npc_x,  // npc if prediction is correct at e2 stage
     262              : 
     263       782023 :     output el2_br_tlu_pkt_t dec_tlu_br0_r_pkt,  // slot 0 branch predictor update packet
     264              : 
     265       340148 :     output logic dec_tlu_perfcnt0,  // toggles when slot0 perf counter 0 has an event inc
     266       514626 :     output logic dec_tlu_perfcnt1,  // toggles when slot0 perf counter 1 has an event inc
     267       312914 :     output logic dec_tlu_perfcnt2,  // toggles when slot0 perf counter 2 has an event inc
     268        48468 :     output logic dec_tlu_perfcnt3,  // toggles when slot0 perf counter 3 has an event inc
     269              : 
     270       506166 :     output el2_predict_pkt_t dec_i0_predict_p_d,  // prediction packet to alus
     271       628591 :     output logic [pt.BHT_GHR_SIZE-1:0] i0_predict_fghr_d,  // DEC predict fghr
     272       651059 :     output logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] i0_predict_index_d,  // DEC predict index
     273        21223 :     output logic [pt.BTB_BTAG_SIZE-1:0] i0_predict_btag_d,  // DEC predict branch tag
     274              : 
     275            0 :     output logic [$clog2(pt.BTB_SIZE)-1:0] dec_fa_error_index,  // Fully associt btb error index
     276              : 
     277      2282093 :     output logic dec_lsu_valid_raw_d,
     278              : 
     279            0 :     output logic [31:0] dec_tlu_mrac_ff,  // CSR for memory region control
     280              : 
     281      6195062 :     output logic [1:0] dec_data_en,  // clock-gate control logic
     282      5989940 :     output logic [1:0] dec_ctl_en,
     283              : 
     284      1427480 :     input logic [15:0] ifu_i0_cinst,  // 16b compressed instruction
     285              : 
     286      5518341 :     output el2_trace_pkt_t trace_rv_trace_pkt,  // trace packet
     287              : 
     288              :     // PMP signals
     289            0 :     output el2_pmp_cfg_pkt_t        pmp_pmpcfg [pt.PMP_ENTRIES],
     290              :     output logic             [31:0] pmp_pmpaddr[pt.PMP_ENTRIES],
     291              : 
     292              : `ifdef RV_USER_MODE
     293              : 
     294              :     // Privilege mode
     295          857 :     output logic priv_mode,
     296          953 :     output logic priv_mode_eff,
     297          857 :     output logic priv_mode_ns,
     298              : 
     299              :     // mseccfg CSR content for PMP
     300            2 :     output el2_mseccfg_pkt_t mseccfg,
     301              : 
     302              : `endif
     303              : 
     304              :     // feature disable from mfdc
     305            0 :     output logic dec_tlu_external_ldfwd_disable,  // disable external load forwarding
     306          322 :     output logic dec_tlu_sideeffect_posted_disable,  // disable posted stores to side-effect address
     307            8 :     output logic dec_tlu_core_ecc_disable,  // disable core ECC
     308            0 :     output logic dec_tlu_bpred_disable,  // disable branch prediction
     309            6 :     output logic dec_tlu_wb_coalescing_disable,  // disable writebuffer coalescing
     310          345 :     output logic [2:0] dec_tlu_dma_qos_prty,  // DMA QoS priority coming from MFDC [18:16]
     311              : 
     312              :     // clock gating overrides from mcgc
     313            2 :     output logic dec_tlu_misc_clk_override,   // override misc clock domain gating
     314            2 :     output logic dec_tlu_ifu_clk_override,    // override fetch clock domain gating
     315            2 :     output logic dec_tlu_lsu_clk_override,    // override load/store clock domain gating
     316            2 :     output logic dec_tlu_bus_clk_override,    // override bus clock domain gating
     317            2 :     output logic dec_tlu_pic_clk_override,    // override PIC clock domain gating
     318          341 :     output logic dec_tlu_picio_clk_override,  // override PICIO clock domain gating
     319            2 :     output logic dec_tlu_dccm_clk_override,   // override DCCM clock domain gating
     320            2 :     output logic dec_tlu_icm_clk_override,    // override ICCM clock domain gating
     321              : 
     322      6165278 :     output logic dec_tlu_i0_commit_cmt,  // committed i0 instruction
     323              :     // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core.
     324              :     /*verilator coverage_off*/
     325              :     input  logic scan_mode               // Flop scan mode control
     326              :     /*verilator coverage_on*/
     327              : 
     328              : );
     329              : 
     330              : 
     331            2 :   logic dec_tlu_dec_clk_override;  // to and from dec blocks
     332            2 :   logic clk_override;
     333              : 
     334      6012959 :   logic dec_ib0_valid_d;
     335              : 
     336      6195679 :   logic dec_pmu_instr_decoded;
     337       237726 :   logic dec_pmu_decode_stall;
     338          266 :   logic dec_pmu_presync_stall;
     339        14664 :   logic dec_pmu_postsync_stall;
     340              : 
     341            2 :   logic dec_tlu_wr_pause_r;  // CSR write to pause reg is at R.
     342              : 
     343      2495649 :   logic [4:0] dec_i0_rs1_d;
     344      4215929 :   logic [4:0] dec_i0_rs2_d;
     345              : 
     346       468702 :   logic [31:0] dec_i0_instr_d;
     347              : 
     348            0 :   logic dec_tlu_trace_disable;
     349            0 :   logic dec_tlu_pipelining_disable;
     350              : 
     351              : 
     352      2808313 :   logic [4:0] dec_i0_waddr_r;
     353      5726991 :   logic dec_i0_wen_r;
     354       314101 :   logic [31:0] dec_i0_wdata_r;
     355        42288 :   logic dec_csr_wen_r;  // csr write enable at wb
     356      1566066 :   logic [11:0] dec_csr_rdaddr_r;  // read address for csrs
     357          542 :   logic [11:0] dec_csr_wraddr_r;  // write address for csryes
     358         1686 :   logic [31:0] dec_csr_wrdata_r;  // csr write data at wb
     359              : 
     360         1000 :   logic [11:0] dec_csr_rdaddr_d;  // read address for csr
     361        86351 :   logic dec_csr_legal_d;  // csr indicates legal operation
     362              : 
     363        42453 :   logic dec_csr_wen_unq_d;  // valid csr with write - for csr legal
     364        86473 :   logic dec_csr_any_unq_d;  // valid csr - for csr legal
     365         1430 :   logic dec_csr_stall_int_ff;  // csr is mie/mstatus
     366              : 
     367          280 :   el2_trap_pkt_t dec_tlu_packet_r;
     368              : 
     369      5770511 :   logic dec_i0_pc4_d;
     370          534 :   logic dec_tlu_presync_d;
     371        20529 :   logic dec_tlu_postsync_d;
     372          122 :   logic dec_tlu_debug_stall;
     373              : 
     374           18 :   logic [31:0] dec_illegal_inst;
     375              : 
     376          206 :   logic dec_i0_icaf_d;
     377              : 
     378            2 :   logic dec_i0_dbecc_d;
     379           86 :   logic dec_i0_icaf_second_d;
     380            0 :   logic [3:0] dec_i0_trigger_match_d;
     381            0 :   logic dec_debug_fence_d;
     382       919868 :   logic dec_nonblock_load_wen;
     383       368806 :   logic [4:0] dec_nonblock_load_waddr;
     384            2 :   logic dec_tlu_flush_pause_r;
     385       206055 :   el2_br_pkt_t dec_i0_brp;
     386       651059 :   logic [pt.BTB_ADDR_HI:pt.BTB_ADDR_LO] dec_i0_bp_index;
     387       628591 :   logic [pt.BHT_GHR_SIZE-1:0] dec_i0_bp_fghr;
     388        21223 :   logic [pt.BTB_BTAG_SIZE-1:0] dec_i0_bp_btag;
     389            0 :   logic [$clog2(pt.BTB_SIZE)-1:0] dec_i0_bp_fa_index;  // Fully associt btb index
     390              : 
     391          339 :   logic [31:1] dec_tlu_i0_pc_r;
     392        29688 :   logic dec_tlu_i0_kill_writeb_wb;
     393      6195034 :   logic dec_tlu_i0_valid_r;
     394              : 
     395            2 :   logic dec_pause_state;
     396              : 
     397          274 :   logic [1:0] dec_i0_icaf_type_d;  // i0 instruction access fault type
     398              : 
     399            0 :   logic dec_tlu_flush_extint;  // Fast ext int started
     400              : 
     401       578667 :   logic [31:0] dec_i0_inst_wb;
     402          339 :   logic [31:1] dec_i0_pc_wb;
     403      6138491 :   logic dec_tlu_i0_valid_wb1, dec_tlu_int_valid_wb1;
     404            4 :   logic [ 4:0] dec_tlu_exc_cause_wb1;
     405           62 :   logic [31:0] dec_tlu_mtval_wb1;
     406         5178 :   logic        dec_tlu_i0_exc_valid_wb1;
     407              : 
     408        21351 :   logic [ 4:0] div_waddr_wb;
     409       159480 :   logic        dec_div_active;
     410              : 
     411         2558 :   logic        dec_debug_valid_d;
     412              : 
     413              :   assign clk_override = dec_tlu_dec_clk_override;
     414              : 
     415              : 
     416              :   assign dec_dbg_rddata[31:0] = dec_i0_wdata_r[31:0];
     417              : 
     418              : 
     419              :   el2_dec_ib_ctl #(.pt(pt)) instbuff (.*);
     420              : 
     421              : 
     422              :   el2_dec_decode_ctl #(.pt(pt)) decode (.*);
     423              : 
     424              : 
     425              :   el2_dec_tlu_ctl #(.pt(pt)) tlu (.*);
     426              : 
     427              : 
     428              :   el2_dec_gpr_ctl #(
     429              :       .pt(pt)
     430              :   ) arf (
     431              :       .*,
     432              :       // inputs
     433              :       .raddr0(dec_i0_rs1_d[4:0]),
     434              :       .raddr1(dec_i0_rs2_d[4:0]),
     435              : 
     436              :       .wen0(dec_i0_wen_r),
     437              :       .waddr0(dec_i0_waddr_r[4:0]),
     438              :       .wd0(dec_i0_wdata_r[31:0]),
     439              :       .wen1(dec_nonblock_load_wen),
     440              :       .waddr1(dec_nonblock_load_waddr[4:0]),
     441              :       .wd1(lsu_nonblock_load_data[31:0]),
     442              :       .wen2(exu_div_wren),
     443              :       .waddr2(div_waddr_wb),
     444              :       .wd2(exu_div_result[31:0]),
     445              : 
     446              :       // outputs
     447              :       .rd0(gpr_i0_rs1_d[31:0]),
     448              :       .rd1(gpr_i0_rs2_d[31:0])
     449              :   );
     450              : 
     451              : 
     452              :   // Trigger
     453              : 
     454              :   el2_dec_trigger #(.pt(pt)) dec_trigger (.*);
     455              : 
     456              : 
     457              : 
     458              : 
     459              :   // trace
     460              :   assign trace_rv_trace_pkt.trace_rv_i_insn_ip = dec_i0_inst_wb[31:0];
     461              :   assign trace_rv_trace_pkt.trace_rv_i_address_ip = {dec_i0_pc_wb[31:1], 1'b0};
     462              : 
     463              :   assign trace_rv_trace_pkt.trace_rv_i_valid_ip     = dec_tlu_int_valid_wb1 | dec_tlu_i0_valid_wb1 | dec_tlu_i0_exc_valid_wb1;
     464              :   assign trace_rv_trace_pkt.trace_rv_i_exception_ip = dec_tlu_int_valid_wb1 |  dec_tlu_i0_exc_valid_wb1;
     465              :   assign trace_rv_trace_pkt.trace_rv_i_ecause_ip    = dec_tlu_exc_cause_wb1[4:0];     // replicate across ports
     466              :   assign trace_rv_trace_pkt.trace_rv_i_interrupt_ip = dec_tlu_int_valid_wb1;
     467              :   assign trace_rv_trace_pkt.trace_rv_i_tval_ip = dec_tlu_mtval_wb1[31:0];  // replicate across ports
     468              : 
     469              : 
     470              : 
     471              :   // end trace
     472              : 
     473              : 
     474              : endmodule  // el2_dec
     475              :