Line data Source code
1 : // SPDX-License-Identifier: Apache-2.0
2 : // Copyright 2020 Western Digital Corporation or its affiliates.
3 : //
4 : // Licensed under the Apache License, Version 2.0 (the "License");
5 : // you may not use this file except in compliance with the License.
6 : // You may obtain a copy of the License at
7 : //
8 : // http://www.apache.org/licenses/LICENSE-2.0
9 : //
10 : // Unless required by applicable law or agreed to in writing, software
11 : // distributed under the License is distributed on an "AS IS" BASIS,
12 : // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 : // See the License for the specific language governing permissions and
14 : // limitations under the License.
15 : //********************************************************************************
16 : // $Id$
17 : //
18 : // Function: Top level VeeR core file to control the debug mode
19 : // Comments: Responsible to put the rest of the core in quiesce mode,
20 : // Send the commands/address. sends WrData and Recieve read Data.
21 : // And then Resume the core to do the normal mode
22 : // Author :
23 : //********************************************************************************
24 : module el2_dbg
25 : import el2_pkg::*;
26 : #(
27 : `include "el2_param.vh"
28 : )(
29 : // outputs to the core for command and data interface
30 0 : output logic [31:0] dbg_cmd_addr,
31 0 : output logic [31:0] dbg_cmd_wrdata,
32 0 : output logic dbg_cmd_valid,
33 0 : output logic dbg_cmd_write, // 1: write command, 0: read_command
34 0 : output logic [1:0] dbg_cmd_type, // 0:gpr 1:csr 2: memory
35 0 : output logic [1:0] dbg_cmd_size, // size of the abstract mem access debug command
36 317 : output logic dbg_core_rst_l, // core reset from dm
37 :
38 : // inputs back from the core/dec
39 314049 : input logic [31:0] core_dbg_rddata,
40 0 : input logic core_dbg_cmd_done, // This will be treated like a valid signal
41 0 : input logic core_dbg_cmd_fail, // Exception during command run
42 :
43 : // Signals to dma to get a bubble
44 0 : output logic dbg_dma_bubble, // Debug needs a bubble to send a valid
45 0 : input logic dma_dbg_ready, // DMA is ready to accept debug request
46 :
47 : // interface with the rest of the core to halt/resume handshaking
48 0 : output logic dbg_halt_req, // This is a pulse
49 0 : output logic dbg_resume_req, // Debug sends a resume requests. Pulse
50 0 : input logic dec_tlu_debug_mode, // Core is in debug mode
51 0 : input logic dec_tlu_dbg_halted, // The core has finished the queiscing sequence. Core is halted now
52 0 : input logic dec_tlu_mpc_halted_only, // Only halted due to MPC
53 0 : input logic dec_tlu_resume_ack, // core sends back an ack for the resume (pulse)
54 :
55 : // inputs from the JTAG
56 240 : input logic dmi_reg_en, // read or write
57 0 : input logic [6:0] dmi_reg_addr, // address of DM register
58 112 : input logic dmi_reg_wr_en, // write instruction
59 20 : input logic [31:0] dmi_reg_wdata, // write data
60 :
61 : // output
62 12 : output logic [31:0] dmi_reg_rdata, // read data
63 :
64 : // AXI Write Channels
65 20 : output logic sb_axi_awvalid,
66 46 : input logic sb_axi_awready,
67 0 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_awid,
68 4 : output logic [31:0] sb_axi_awaddr,
69 4 : output logic [3:0] sb_axi_awregion,
70 0 : output logic [7:0] sb_axi_awlen,
71 0 : output logic [2:0] sb_axi_awsize,
72 0 : output logic [1:0] sb_axi_awburst,
73 0 : output logic sb_axi_awlock,
74 317 : output logic [3:0] sb_axi_awcache,
75 0 : output logic [2:0] sb_axi_awprot,
76 0 : output logic [3:0] sb_axi_awqos,
77 :
78 20 : output logic sb_axi_wvalid,
79 46 : input logic sb_axi_wready,
80 6 : output logic [63:0] sb_axi_wdata,
81 24 : output logic [7:0] sb_axi_wstrb,
82 317 : output logic sb_axi_wlast,
83 :
84 20 : input logic sb_axi_bvalid,
85 317 : output logic sb_axi_bready,
86 0 : input logic [1:0] sb_axi_bresp,
87 :
88 : // AXI Read Channels
89 16 : output logic sb_axi_arvalid,
90 44 : input logic sb_axi_arready,
91 0 : output logic [pt.SB_BUS_TAG-1:0] sb_axi_arid,
92 4 : output logic [31:0] sb_axi_araddr,
93 4 : output logic [3:0] sb_axi_arregion,
94 0 : output logic [7:0] sb_axi_arlen,
95 0 : output logic [2:0] sb_axi_arsize,
96 0 : output logic [1:0] sb_axi_arburst,
97 0 : output logic sb_axi_arlock,
98 0 : output logic [3:0] sb_axi_arcache,
99 0 : output logic [2:0] sb_axi_arprot,
100 0 : output logic [3:0] sb_axi_arqos,
101 :
102 16 : input logic sb_axi_rvalid,
103 317 : output logic sb_axi_rready,
104 5 : input logic [63:0] sb_axi_rdata,
105 0 : input logic [1:0] sb_axi_rresp,
106 :
107 316 : input logic dbg_bus_clk_en,
108 :
109 : // general inputs
110 61843746 : input logic clk,
111 61843746 : input logic free_clk,
112 316 : input logic rst_l, // This includes both top rst and debug rst
113 316 : input logic dbg_rst_l,
114 0 : input logic clk_override,
115 0 : input logic scan_mode
116 : );
117 :
118 :
119 : typedef enum logic [3:0] {IDLE=4'h0, HALTING=4'h1, HALTED=4'h2, CORE_CMD_START=4'h3, CORE_CMD_WAIT=4'h4, SB_CMD_START=4'h5, SB_CMD_SEND=4'h6, SB_CMD_RESP=4'h7, CMD_DONE=4'h8, RESUMING=4'h9} state_t;
120 : typedef enum logic [3:0] {SBIDLE=4'h0, WAIT_RD=4'h1, WAIT_WR=4'h2, CMD_RD=4'h3, CMD_WR=4'h4, CMD_WR_ADDR=4'h5, CMD_WR_DATA=4'h6, RSP_RD=4'h7, RSP_WR=4'h8, DONE=4'h9} sb_state_t;
121 :
122 0 : state_t dbg_state;
123 0 : state_t dbg_nxtstate;
124 0 : logic dbg_state_en;
125 : // these are the registers that the debug module implements
126 0 : logic [31:0] dmstatus_reg; // [26:24]-dmerr, [17:16]-resume ack, [9:8]-halted, [3:0]-version
127 0 : logic [31:0] dmcontrol_reg; // dmcontrol register has only 6 bits implemented. 31: haltreq, 30: resumereq, 29: haltreset, 28: ackhavereset, 1: ndmreset, 0: dmactive.
128 0 : logic [31:0] command_reg;
129 0 : logic [31:0] abstractcs_reg; // bits implemted are [12] - busy and [10:8]= command error
130 0 : logic [31:0] haltsum0_reg;
131 0 : logic [31:0] data0_reg;
132 0 : logic [31:0] data1_reg;
133 :
134 : // data 0
135 0 : logic [31:0] data0_din;
136 0 : logic data0_reg_wren, data0_reg_wren0, data0_reg_wren1, data0_reg_wren2;
137 : // data 1
138 0 : logic [31:0] data1_din;
139 0 : logic data1_reg_wren, data1_reg_wren0, data1_reg_wren1;
140 : // abstractcs
141 0 : logic abstractcs_busy_wren;
142 0 : logic abstractcs_busy_din;
143 0 : logic [2:0] abstractcs_error_din;
144 0 : logic abstractcs_error_sel0, abstractcs_error_sel1, abstractcs_error_sel2, abstractcs_error_sel3, abstractcs_error_sel4, abstractcs_error_sel5, abstractcs_error_sel6;
145 0 : logic dbg_sb_bus_error;
146 : // abstractauto
147 0 : logic abstractauto_reg_wren;
148 0 : logic [1:0] abstractauto_reg;
149 :
150 : // dmstatus
151 0 : logic dmstatus_resumeack_wren;
152 0 : logic dmstatus_resumeack_din;
153 4 : logic dmstatus_haveresetn_wren;
154 0 : logic dmstatus_resumeack;
155 633 : logic dmstatus_unavail;
156 316 : logic dmstatus_running;
157 0 : logic dmstatus_halted;
158 2 : logic dmstatus_havereset, dmstatus_haveresetn;
159 :
160 : // dmcontrol
161 0 : logic resumereq;
162 12 : logic dmcontrol_wren, dmcontrol_wren_Q;
163 : // command
164 0 : logic execute_command_ns, execute_command;
165 0 : logic command_wren, command_regno_wren;
166 0 : logic command_transfer_din;
167 24 : logic command_postexec_din;
168 0 : logic [31:0] command_din;
169 0 : logic [3:0] dbg_cmd_addr_incr;
170 0 : logic [31:0] dbg_cmd_curr_addr;
171 0 : logic [31:0] dbg_cmd_next_addr;
172 :
173 : // needed to send the read data back for dmi reads
174 28 : logic [31:0] dmi_reg_rdata_din;
175 :
176 36 : sb_state_t sb_state;
177 36 : sb_state_t sb_nxtstate;
178 90 : logic sb_state_en;
179 :
180 : //System bus section
181 36 : logic sbcs_wren;
182 72 : logic sbcs_sbbusy_wren;
183 353 : logic sbcs_sbbusy_din;
184 0 : logic sbcs_sbbusyerror_wren;
185 317 : logic sbcs_sbbusyerror_din;
186 :
187 0 : logic sbcs_sberror_wren;
188 36 : logic [2:0] sbcs_sberror_din;
189 0 : logic sbcs_unaligned;
190 0 : logic sbcs_illegal_size;
191 0 : logic [19:15] sbcs_reg_int;
192 :
193 : // data
194 20 : logic sbdata0_reg_wren0;
195 16 : logic sbdata0_reg_wren1;
196 36 : logic sbdata0_reg_wren;
197 12 : logic [31:0] sbdata0_din;
198 :
199 0 : logic sbdata1_reg_wren0;
200 16 : logic sbdata1_reg_wren1;
201 16 : logic sbdata1_reg_wren;
202 0 : logic [31:0] sbdata1_din;
203 :
204 36 : logic sbaddress0_reg_wren0;
205 36 : logic sbaddress0_reg_wren1;
206 72 : logic sbaddress0_reg_wren;
207 8 : logic [31:0] sbaddress0_reg_din;
208 0 : logic [3:0] sbaddress0_incr;
209 16 : logic sbreadonaddr_access;
210 0 : logic sbreadondata_access;
211 20 : logic sbdata0wr_access;
212 :
213 0 : logic sb_abmem_cmd_done_in, sb_abmem_data_done_in;
214 0 : logic sb_abmem_cmd_done_en, sb_abmem_data_done_en;
215 0 : logic sb_abmem_cmd_done, sb_abmem_data_done;
216 0 : logic [31:0] abmem_addr;
217 0 : logic abmem_addr_in_dccm_region, abmem_addr_in_iccm_region, abmem_addr_in_pic_region;
218 0 : logic abmem_addr_core_local;
219 317 : logic abmem_addr_external;
220 :
221 0 : logic sb_cmd_pending, sb_abmem_cmd_pending;
222 0 : logic sb_abmem_cmd_write;
223 0 : logic [2:0] sb_abmem_cmd_size;
224 0 : logic [31:0] sb_abmem_cmd_addr;
225 0 : logic [31:0] sb_abmem_cmd_wdata;
226 :
227 0 : logic [2:0] sb_cmd_size;
228 4 : logic [31:0] sb_cmd_addr;
229 4 : logic [63:0] sb_cmd_wdata;
230 :
231 16 : logic sb_bus_cmd_read, sb_bus_cmd_write_addr, sb_bus_cmd_write_data;
232 16 : logic sb_bus_rsp_read, sb_bus_rsp_write;
233 0 : logic sb_bus_rsp_error;
234 4 : logic [63:0] sb_bus_rdata;
235 :
236 : //registers
237 0 : logic [31:0] sbcs_reg;
238 4 : logic [31:0] sbaddress0_reg;
239 4 : logic [31:0] sbdata0_reg;
240 0 : logic [31:0] sbdata1_reg;
241 :
242 0 : logic sb_abmem_cmd_arvalid, sb_abmem_cmd_awvalid, sb_abmem_cmd_wvalid;
243 0 : logic sb_abmem_read_pend;
244 16 : logic sb_cmd_awvalid, sb_cmd_wvalid, sb_cmd_arvalid;
245 16 : logic sb_read_pend;
246 4 : logic [31:0] sb_axi_addr;
247 4 : logic [63:0] sb_axi_wrdata;
248 0 : logic [2:0] sb_axi_size;
249 :
250 2 : logic dbg_dm_rst_l;
251 316 : logic rst_l_sync;
252 :
253 : //clken
254 240 : logic dbg_free_clken;
255 61843746 : logic dbg_free_clk;
256 :
257 240 : logic sb_free_clken;
258 61843746 : logic sb_free_clk;
259 :
260 : // clocking
261 : // used for the abstract commands.
262 : assign dbg_free_clken = dmi_reg_en | execute_command | (dbg_state != IDLE) | dbg_state_en | dec_tlu_dbg_halted | dec_tlu_mpc_halted_only | dec_tlu_debug_mode | dbg_halt_req | clk_override;
263 :
264 : // used for the system bus
265 : assign sb_free_clken = dmi_reg_en | execute_command | sb_state_en | (sb_state != SBIDLE) | clk_override;
266 :
267 : rvoclkhdr dbg_free_cgc (.en(dbg_free_clken), .l1clk(dbg_free_clk), .*);
268 : rvoclkhdr sb_free_cgc (.en(sb_free_clken), .l1clk(sb_free_clk), .*);
269 :
270 : // end clocking section
271 :
272 : // Reset logic
273 : assign dbg_dm_rst_l = dbg_rst_l & (dmcontrol_reg[0] | scan_mode);
274 : assign dbg_core_rst_l = ~dmcontrol_reg[1] | scan_mode;
275 :
276 : // synchronize the rst
277 : rvsyncss #(1) rstl_syncff (.din(rst_l), .dout(rst_l_sync), .clk(free_clk), .rst_l(dbg_rst_l));
278 :
279 : // system bus register
280 : // sbcs[31:29], sbcs - [22]:sbbusyerror, [21]: sbbusy, [20]:sbreadonaddr, [19:17]:sbaccess, [16]:sbautoincrement, [15]:sbreadondata, [14:12]:sberror, sbsize=32, 128=0, 64/32/16/8 are legal
281 : assign sbcs_reg[31:29] = 3'b1;
282 : assign sbcs_reg[28:23] = '0;
283 : assign sbcs_reg[19:15] = {sbcs_reg_int[19], ~sbcs_reg_int[18], sbcs_reg_int[17:15]};
284 : assign sbcs_reg[11:5] = 7'h20;
285 : assign sbcs_reg[4:0] = 5'b01111;
286 : assign sbcs_wren = (dmi_reg_addr == 7'h38) & dmi_reg_en & dmi_reg_wr_en & (sb_state == SBIDLE);
287 : assign sbcs_sbbusyerror_wren = (sbcs_wren & dmi_reg_wdata[22]) |
288 : (sbcs_reg[21] & dmi_reg_en & ((dmi_reg_wr_en & (dmi_reg_addr == 7'h39)) | (dmi_reg_addr == 7'h3c) | (dmi_reg_addr == 7'h3d)));
289 : assign sbcs_sbbusyerror_din = ~(sbcs_wren & dmi_reg_wdata[22]); // Clear when writing one
290 :
291 : rvdffs #(1) sbcs_sbbusyerror_reg (.din(sbcs_sbbusyerror_din), .dout(sbcs_reg[22]), .en(sbcs_sbbusyerror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
292 : rvdffs #(1) sbcs_sbbusy_reg (.din(sbcs_sbbusy_din), .dout(sbcs_reg[21]), .en(sbcs_sbbusy_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
293 : rvdffs #(1) sbcs_sbreadonaddr_reg (.din(dmi_reg_wdata[20]), .dout(sbcs_reg[20]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
294 : rvdffs #(5) sbcs_misc_reg (.din({dmi_reg_wdata[19],~dmi_reg_wdata[18],dmi_reg_wdata[17:15]}),
295 : .dout(sbcs_reg_int[19:15]), .en(sbcs_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
296 : rvdffs #(3) sbcs_error_reg (.din(sbcs_sberror_din[2:0]), .dout(sbcs_reg[14:12]), .en(sbcs_sberror_wren), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
297 :
298 : assign sbcs_unaligned = ((sbcs_reg[19:17] == 3'b001) & sbaddress0_reg[0]) |
299 : ((sbcs_reg[19:17] == 3'b010) & (|sbaddress0_reg[1:0])) |
300 : ((sbcs_reg[19:17] == 3'b011) & (|sbaddress0_reg[2:0]));
301 :
302 : assign sbcs_illegal_size = sbcs_reg[19]; // Anything bigger than 64 bits is illegal
303 :
304 : assign sbaddress0_incr[3:0] = ({4{(sbcs_reg[19:17] == 3'h0)}} & 4'b0001) |
305 : ({4{(sbcs_reg[19:17] == 3'h1)}} & 4'b0010) |
306 : ({4{(sbcs_reg[19:17] == 3'h2)}} & 4'b0100) |
307 : ({4{(sbcs_reg[19:17] == 3'h3)}} & 4'b1000);
308 :
309 : // sbdata
310 : assign sbdata0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h3c); // write data only when single read is 0
311 : assign sbdata0_reg_wren1 = (sb_state == RSP_RD) & sb_state_en & ~sbcs_sberror_wren;
312 : assign sbdata0_reg_wren = sbdata0_reg_wren0 | sbdata0_reg_wren1;
313 :
314 : assign sbdata1_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h3d); // write data only when single read is 0;
315 : assign sbdata1_reg_wren1 = (sb_state == RSP_RD) & sb_state_en & ~sbcs_sberror_wren;
316 : assign sbdata1_reg_wren = sbdata1_reg_wren0 | sbdata1_reg_wren1;
317 :
318 : assign sbdata0_din[31:0] = ({32{sbdata0_reg_wren0}} & dmi_reg_wdata[31:0]) |
319 : ({32{sbdata0_reg_wren1}} & sb_bus_rdata[31:0]);
320 : assign sbdata1_din[31:0] = ({32{sbdata1_reg_wren0}} & dmi_reg_wdata[31:0]) |
321 : ({32{sbdata1_reg_wren1}} & sb_bus_rdata[63:32]);
322 :
323 : rvdffe #(32) dbg_sbdata0_reg (.*, .din(sbdata0_din[31:0]), .dout(sbdata0_reg[31:0]), .en(sbdata0_reg_wren), .rst_l(dbg_dm_rst_l));
324 : rvdffe #(32) dbg_sbdata1_reg (.*, .din(sbdata1_din[31:0]), .dout(sbdata1_reg[31:0]), .en(sbdata1_reg_wren), .rst_l(dbg_dm_rst_l));
325 :
326 : // sbaddress
327 : assign sbaddress0_reg_wren0 = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39);
328 : assign sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1;
329 : assign sbaddress0_reg_din[31:0]= ({32{sbaddress0_reg_wren0}} & dmi_reg_wdata[31:0]) |
330 : ({32{sbaddress0_reg_wren1}} & (32'(sbaddress0_reg[31:0] + {28'b0,sbaddress0_incr[3:0]})));
331 : rvdffe #(32) dbg_sbaddress0_reg (.*, .din(sbaddress0_reg_din[31:0]), .dout(sbaddress0_reg[31:0]), .en(sbaddress0_reg_wren), .rst_l(dbg_dm_rst_l));
332 :
333 : assign sbreadonaddr_access = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h39) & sbcs_reg[20]; // if readonaddr is set the next command will start upon writing of addr0
334 : assign sbreadondata_access = dmi_reg_en & ~dmi_reg_wr_en & (dmi_reg_addr == 7'h3c) & sbcs_reg[15]; // if readondata is set the next command will start upon reading of data0
335 : assign sbdata0wr_access = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h3c); // write to sbdata0 will start write command to system bus
336 :
337 : // memory mapped registers
338 : // dmcontrol register has only 5 bits implemented. 31: haltreq, 30: resumereq, 28: ackhavereset, 1: ndmreset, 0: dmactive.
339 : // rest all the bits are zeroed out
340 : // dmactive flop is reset based on core rst_l, all other flops use dm_rst_l
341 : assign dmcontrol_wren = (dmi_reg_addr == 7'h10) & dmi_reg_en & dmi_reg_wr_en;
342 : assign dmcontrol_reg[29] = '0;
343 : assign dmcontrol_reg[27:2] = '0;
344 : assign resumereq = dmcontrol_reg[30] & ~dmcontrol_reg[31] & dmcontrol_wren_Q;
345 : rvdffs #(4) dmcontrolff (.din({dmi_reg_wdata[31:30],dmi_reg_wdata[28],dmi_reg_wdata[1]}), .dout({dmcontrol_reg[31:30], dmcontrol_reg[28], dmcontrol_reg[1]}), .en(dmcontrol_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
346 : rvdffs #(1) dmcontrol_dmactive_ff (.din(dmi_reg_wdata[0]), .dout(dmcontrol_reg[0]), .en(dmcontrol_wren), .rst_l(dbg_rst_l), .clk(dbg_free_clk));
347 : rvdff #(1) dmcontrol_wrenff(.din(dmcontrol_wren), .dout(dmcontrol_wren_Q), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
348 :
349 : // dmstatus register bits that are implemented
350 : // [19:18]-havereset,[17:16]-resume ack, [9:8]-halted, [3:0]-version
351 : // rest all the bits are zeroed out
352 : //assign dmstatus_wren = (dmi_reg_addr[31:0] == 32'h11) & dmi_reg_en;
353 : assign dmstatus_reg[31:20] = '0;
354 : assign dmstatus_reg[19:18] = {2{dmstatus_havereset}};
355 : assign dmstatus_reg[15:14] = '0;
356 : assign dmstatus_reg[7] = '1;
357 : assign dmstatus_reg[6:4] = '0;
358 : assign dmstatus_reg[17:16] = {2{dmstatus_resumeack}};
359 : assign dmstatus_reg[13:12] = {2{dmstatus_unavail}};
360 : assign dmstatus_reg[11:10] = {2{dmstatus_running}};
361 : assign dmstatus_reg[9:8] = {2{dmstatus_halted}};
362 : assign dmstatus_reg[3:0] = 4'h2;
363 :
364 : assign dmstatus_resumeack_wren = ((dbg_state == RESUMING) & dec_tlu_resume_ack) | (dmstatus_resumeack & resumereq & dmstatus_halted);
365 : assign dmstatus_resumeack_din = (dbg_state == RESUMING) & dec_tlu_resume_ack;
366 :
367 : assign dmstatus_haveresetn_wren = (dmi_reg_addr == 7'h10) & dmi_reg_wdata[28] & dmi_reg_en & dmi_reg_wr_en & dmcontrol_reg[0]; // clear the havereset
368 : assign dmstatus_havereset = ~dmstatus_haveresetn;
369 :
370 : assign dmstatus_unavail = dmcontrol_reg[1] | ~rst_l_sync;
371 : assign dmstatus_running = ~(dmstatus_unavail | dmstatus_halted);
372 :
373 : rvdffs #(1) dmstatus_resumeack_reg (.din(dmstatus_resumeack_din), .dout(dmstatus_resumeack), .en(dmstatus_resumeack_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
374 : rvdff #(1) dmstatus_halted_reg (.din(dec_tlu_dbg_halted & ~dec_tlu_mpc_halted_only), .dout(dmstatus_halted), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
375 : rvdffs #(1) dmstatus_haveresetn_reg (.din(1'b1), .dout(dmstatus_haveresetn), .en(dmstatus_haveresetn_wren), .rst_l(rst_l), .clk(dbg_free_clk));
376 :
377 : // haltsum0 register
378 : assign haltsum0_reg[31:1] = '0;
379 : assign haltsum0_reg[0] = dmstatus_halted;
380 :
381 : // abstractcs register
382 : // bits implemted are [12] - busy and [10:8]= command error
383 : assign abstractcs_reg[31:13] = '0;
384 : assign abstractcs_reg[11] = '0;
385 : assign abstractcs_reg[7:4] = '0;
386 : assign abstractcs_reg[3:0] = 4'h2; // One data register
387 :
388 : assign abstractcs_error_sel0 = abstractcs_reg[12] & ~(|abstractcs_reg[10:8]) & dmi_reg_en & ((dmi_reg_wr_en & ((dmi_reg_addr == 7'h16) | (dmi_reg_addr == 7'h17)) | (dmi_reg_addr == 7'h18)) |
389 : (dmi_reg_addr == 7'h4) | (dmi_reg_addr == 7'h5));
390 : assign abstractcs_error_sel1 = execute_command & ~(|abstractcs_reg[10:8]) &
391 : ((~((command_reg[31:24] == 8'b0) | (command_reg[31:24] == 8'h2))) | // Illegal command
392 : (((command_reg[22:20] == 3'b011) | (command_reg[22])) & (command_reg[31:24] == 8'h2)) | // Illegal abstract memory size (can't be DW or higher)
393 : ((command_reg[22:20] != 3'b010) & ((command_reg[31:24] == 8'h0) & command_reg[17])) | // Illegal abstract reg size
394 : ((command_reg[31:24] == 8'h0) & command_reg[18])); //postexec for abstract register access
395 : assign abstractcs_error_sel2 = ((core_dbg_cmd_done & core_dbg_cmd_fail) | // exception from core
396 : (execute_command & (command_reg[31:24] == 8'h0) & // unimplemented regs
397 : (((command_reg[15:12] == 4'h1) & (command_reg[11:5] != 0)) | (command_reg[15:13] != 0)))) & ~(|abstractcs_reg[10:8]);
398 : assign abstractcs_error_sel3 = execute_command & (dbg_state != HALTED) & ~(|abstractcs_reg[10:8]);
399 : assign abstractcs_error_sel4 = dbg_sb_bus_error & dbg_bus_clk_en & ~(|abstractcs_reg[10:8]);// sb bus error for abstract memory command
400 : assign abstractcs_error_sel5 = execute_command & (command_reg[31:24] == 8'h2) & ~(|abstractcs_reg[10:8]) &
401 : (((command_reg[22:20] == 3'b001) & data1_reg[0]) | ((command_reg[22:20] == 3'b010) & (|data1_reg[1:0]))); //Unaligned address for abstract memory
402 : assign abstractcs_error_sel6 = (dmi_reg_addr == 7'h16) & dmi_reg_en & dmi_reg_wr_en;
403 :
404 : assign abstractcs_error_din[2:0] = abstractcs_error_sel0 ? 3'b001 : // writing command or abstractcs while a command was executing. Or accessing data0
405 : abstractcs_error_sel1 ? 3'b010 : // writing a illegal command type to cmd field of command
406 : abstractcs_error_sel2 ? 3'b011 : // exception while running command
407 : abstractcs_error_sel3 ? 3'b100 : // writing a comnand when not in the halted state
408 : abstractcs_error_sel4 ? 3'b101 : // Bus error
409 : abstractcs_error_sel5 ? 3'b111 : // unaligned or illegal size abstract memory command
410 : abstractcs_error_sel6 ? (~dmi_reg_wdata[10:8] & abstractcs_reg[10:8]) : //W1C
411 : abstractcs_reg[10:8]; //hold
412 :
413 : rvdffs #(1) dmabstractcs_busy_reg (.din(abstractcs_busy_din), .dout(abstractcs_reg[12]), .en(abstractcs_busy_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
414 : rvdff #(3) dmabstractcs_error_reg (.din(abstractcs_error_din[2:0]), .dout(abstractcs_reg[10:8]), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
415 :
416 : // abstract auto reg
417 : assign abstractauto_reg_wren = dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h18) & ~abstractcs_reg[12];
418 : rvdffs #(2) dbg_abstractauto_reg (.*, .din(dmi_reg_wdata[1:0]), .dout(abstractauto_reg[1:0]), .en(abstractauto_reg_wren), .rst_l(dbg_dm_rst_l), .clk(dbg_free_clk));
419 :
420 : // command register - implemented all the bits in this register
421 : // command[16] = 1: write, 0: read
422 : assign execute_command_ns = command_wren |
423 : (dmi_reg_en & ~abstractcs_reg[12] & (((dmi_reg_addr == 7'h4) & abstractauto_reg[0]) | ((dmi_reg_addr == 7'h5) & abstractauto_reg[1])));
424 : assign command_wren = (dmi_reg_addr == 7'h17) & dmi_reg_en & dmi_reg_wr_en;
425 : assign command_regno_wren = command_wren | ((command_reg[31:24] == 8'h0) & command_reg[19] & (dbg_state == CMD_DONE) & ~(|abstractcs_reg[10:8])); // aarpostincrement
426 : assign command_postexec_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[18];
427 : assign command_transfer_din = (dmi_reg_wdata[31:24] == 8'h0) & dmi_reg_wdata[17];
428 : assign command_din[31:16] = {dmi_reg_wdata[31:24],1'b0,dmi_reg_wdata[22:19],command_postexec_din,command_transfer_din, dmi_reg_wdata[16]};
429 : assign command_din[15:0] = command_wren ? dmi_reg_wdata[15:0] : dbg_cmd_next_addr[15:0];
430 : rvdff #(1) execute_commandff (.*, .din(execute_command_ns), .dout(execute_command), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l));
431 : rvdffe #(16) dmcommand_reg (.*, .din(command_din[31:16]), .dout(command_reg[31:16]), .en(command_wren), .rst_l(dbg_dm_rst_l));
432 : rvdffe #(16) dmcommand_regno_reg (.*, .din(command_din[15:0]), .dout(command_reg[15:0]), .en(command_regno_wren), .rst_l(dbg_dm_rst_l));
433 :
434 : // data0 reg
435 : assign data0_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h4) & (dbg_state == HALTED) & ~abstractcs_reg[12]);
436 : assign data0_reg_wren1 = core_dbg_cmd_done & (dbg_state == CORE_CMD_WAIT) & ~command_reg[16];
437 : assign data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 | data0_reg_wren2;
438 :
439 : assign data0_din[31:0] = ({32{data0_reg_wren0}} & dmi_reg_wdata[31:0]) |
440 : ({32{data0_reg_wren1}} & core_dbg_rddata[31:0]) |
441 : ({32{data0_reg_wren2}} & sb_bus_rdata[31:0]);
442 :
443 : rvdffe #(32) dbg_data0_reg (.*, .din(data0_din[31:0]), .dout(data0_reg[31:0]), .en(data0_reg_wren), .rst_l(dbg_dm_rst_l));
444 :
445 : // data 1
446 : assign data1_reg_wren0 = (dmi_reg_en & dmi_reg_wr_en & (dmi_reg_addr == 7'h5) & (dbg_state == HALTED) & ~abstractcs_reg[12]);
447 : assign data1_reg_wren1 = (dbg_state == CMD_DONE) & (command_reg[31:24] == 8'h2) & command_reg[19] & ~(|abstractcs_reg[10:8]); // aampostincrement
448 : assign data1_reg_wren = data1_reg_wren0 | data1_reg_wren1;
449 :
450 : assign data1_din[31:0] = ({32{data1_reg_wren0}} & dmi_reg_wdata[31:0]) |
451 : ({32{data1_reg_wren1}} & dbg_cmd_next_addr[31:0]);
452 :
453 : rvdffe #(32) dbg_data1_reg (.*, .din(data1_din[31:0]), .dout(data1_reg[31:0]), .en(data1_reg_wren), .rst_l(dbg_dm_rst_l));
454 :
455 : rvdffs #(1) sb_abmem_cmd_doneff (.din(sb_abmem_cmd_done_in), .dout(sb_abmem_cmd_done), .en(sb_abmem_cmd_done_en), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l), .*);
456 : rvdffs #(1) sb_abmem_data_doneff (.din(sb_abmem_data_done_in), .dout(sb_abmem_data_done), .en(sb_abmem_data_done_en), .clk(dbg_free_clk), .rst_l(dbg_dm_rst_l), .*);
457 :
458 : // FSM to control the debug mode entry, command send/recieve, and Resume flow.
459 317 : always_comb begin
460 317 : dbg_nxtstate = IDLE;
461 317 : dbg_state_en = 1'b0;
462 317 : abstractcs_busy_wren = 1'b0;
463 317 : abstractcs_busy_din = 1'b0;
464 317 : dbg_halt_req = dmcontrol_wren_Q & dmcontrol_reg[31]; // single pulse output to the core. Need to drive every time this register is written since core might be halted due to MPC
465 317 : dbg_resume_req = 1'b0; // single pulse output to the core
466 317 : dbg_sb_bus_error = 1'b0;
467 317 : data0_reg_wren2 = 1'b0;
468 317 : sb_abmem_cmd_done_in = 1'b0;
469 317 : sb_abmem_data_done_in = 1'b0;
470 317 : sb_abmem_cmd_done_en = 1'b0;
471 317 : sb_abmem_data_done_en = 1'b0;
472 :
473 317 : case (dbg_state)
474 24263282 : IDLE: begin
475 24263282 : dbg_nxtstate = (dmstatus_reg[9] | dec_tlu_mpc_halted_only) ? HALTED : HALTING; // initiate the halt command to the core
476 24263282 : dbg_state_en = dmcontrol_reg[31] | dmstatus_reg[9] | dec_tlu_mpc_halted_only; // when the jtag writes the halt bit in the DM register, OR when the status indicates H
477 24263282 : dbg_halt_req = dmcontrol_reg[31]; // only when jtag has written the halt_req bit in the control. Removed debug mode qualification during MPC changes
478 : end
479 0 : HALTING : begin
480 0 : dbg_nxtstate = HALTED; // Goto HALTED once the core sends an ACK
481 0 : dbg_state_en = dmstatus_reg[9] | dec_tlu_mpc_halted_only; // core indicates halted
482 : end
483 0 : HALTED: begin
484 : // wait for halted to go away before send to resume. Else start of new command
485 0 : dbg_nxtstate = dmstatus_reg[9] ? (resumereq ? RESUMING : (((command_reg[31:24] == 8'h2) & abmem_addr_external) ? SB_CMD_START : CORE_CMD_START)) :
486 0 : (dmcontrol_reg[31] ? HALTING : IDLE); // This is MPC halted case
487 0 : dbg_state_en = (dmstatus_reg[9] & resumereq) | execute_command | ~(dmstatus_reg[9] | dec_tlu_mpc_halted_only);
488 0 : abstractcs_busy_wren = dbg_state_en & ((dbg_nxtstate == CORE_CMD_START) | (dbg_nxtstate == SB_CMD_START)); // write busy when a new command was written by jtag
489 0 : abstractcs_busy_din = 1'b1;
490 0 : dbg_resume_req = dbg_state_en & (dbg_nxtstate == RESUMING); // single cycle pulse to core if resuming
491 : end
492 0 : CORE_CMD_START: begin
493 : // Don't execute the command if cmderror or transfer=0 for abstract register access
494 0 : dbg_nxtstate = ((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17])) ? CMD_DONE : CORE_CMD_WAIT; // new command sent to the core
495 0 : dbg_state_en = dbg_cmd_valid | (|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17]);
496 : end
497 0 : CORE_CMD_WAIT: begin
498 0 : dbg_nxtstate = CMD_DONE;
499 0 : dbg_state_en = core_dbg_cmd_done; // go to done state for one cycle after completing current command
500 : end
501 0 : SB_CMD_START: begin
502 0 : dbg_nxtstate = (|abstractcs_reg[10:8]) ? CMD_DONE : SB_CMD_SEND;
503 0 : dbg_state_en = (dbg_bus_clk_en & ~sb_cmd_pending) | (|abstractcs_reg[10:8]);
504 : end
505 0 : SB_CMD_SEND: begin
506 0 : sb_abmem_cmd_done_in = 1'b1;
507 0 : sb_abmem_data_done_in= 1'b1;
508 0 : sb_abmem_cmd_done_en = (sb_bus_cmd_read | sb_bus_cmd_write_addr) & dbg_bus_clk_en;
509 0 : sb_abmem_data_done_en= (sb_bus_cmd_read | sb_bus_cmd_write_data) & dbg_bus_clk_en;
510 0 : dbg_nxtstate = SB_CMD_RESP;
511 0 : dbg_state_en = (sb_abmem_cmd_done | sb_abmem_cmd_done_en) & (sb_abmem_data_done | sb_abmem_data_done_en) & dbg_bus_clk_en;
512 : end
513 0 : SB_CMD_RESP: begin
514 0 : dbg_nxtstate = CMD_DONE;
515 0 : dbg_state_en = (sb_bus_rsp_read | sb_bus_rsp_write) & dbg_bus_clk_en;
516 0 : dbg_sb_bus_error = (sb_bus_rsp_read | sb_bus_rsp_write) & sb_bus_rsp_error & dbg_bus_clk_en;
517 0 : data0_reg_wren2 = dbg_state_en & ~sb_abmem_cmd_write & ~dbg_sb_bus_error;
518 : end
519 0 : CMD_DONE: begin
520 0 : dbg_nxtstate = HALTED;
521 0 : dbg_state_en = 1'b1;
522 0 : abstractcs_busy_wren = dbg_state_en; // remove the busy bit from the abstracts ( bit 12 )
523 0 : abstractcs_busy_din = 1'b0;
524 0 : sb_abmem_cmd_done_in = 1'b0;
525 0 : sb_abmem_data_done_in= 1'b0;
526 0 : sb_abmem_cmd_done_en = 1'b1;
527 0 : sb_abmem_data_done_en= 1'b1;
528 : end
529 0 : RESUMING : begin
530 0 : dbg_nxtstate = IDLE;
531 0 : dbg_state_en = dmstatus_reg[17]; // resume ack has been updated in the dmstatus register
532 : end
533 0 : default : begin
534 0 : dbg_nxtstate = IDLE;
535 0 : dbg_state_en = 1'b0;
536 0 : abstractcs_busy_wren = 1'b0;
537 0 : abstractcs_busy_din = 1'b0;
538 0 : dbg_halt_req = 1'b0; // single pulse output to the core
539 0 : dbg_resume_req = 1'b0; // single pulse output to the core
540 0 : dbg_sb_bus_error = 1'b0;
541 0 : data0_reg_wren2 = 1'b0;
542 0 : sb_abmem_cmd_done_in = 1'b0;
543 0 : sb_abmem_data_done_in = 1'b0;
544 0 : sb_abmem_cmd_done_en = 1'b0;
545 0 : sb_abmem_data_done_en = 1'b0;
546 : end
547 : endcase
548 : end // always_comb begin
549 :
550 : assign dmi_reg_rdata_din[31:0] = ({32{dmi_reg_addr == 7'h4}} & data0_reg[31:0]) |
551 : ({32{dmi_reg_addr == 7'h5}} & data1_reg[31:0]) |
552 : ({32{dmi_reg_addr == 7'h10}} & {2'b0,dmcontrol_reg[29],1'b0,dmcontrol_reg[27:0]}) | // Read0 to Write only bits
553 : ({32{dmi_reg_addr == 7'h11}} & dmstatus_reg[31:0]) |
554 : ({32{dmi_reg_addr == 7'h16}} & abstractcs_reg[31:0]) |
555 : ({32{dmi_reg_addr == 7'h17}} & command_reg[31:0]) |
556 : ({32{dmi_reg_addr == 7'h18}} & {30'h0,abstractauto_reg[1:0]}) |
557 : ({32{dmi_reg_addr == 7'h40}} & haltsum0_reg[31:0]) |
558 : ({32{dmi_reg_addr == 7'h38}} & sbcs_reg[31:0]) |
559 : ({32{dmi_reg_addr == 7'h39}} & sbaddress0_reg[31:0]) |
560 : ({32{dmi_reg_addr == 7'h3c}} & sbdata0_reg[31:0]) |
561 : ({32{dmi_reg_addr == 7'h3d}} & sbdata1_reg[31:0]);
562 :
563 :
564 : rvdffs #($bits(state_t)) dbg_state_reg (.din(dbg_nxtstate), .dout({dbg_state}), .en(dbg_state_en), .rst_l(dbg_dm_rst_l & rst_l), .clk(dbg_free_clk));
565 : rvdffe #(32) dmi_rddata_reg (.din(dmi_reg_rdata_din[31:0]), .dout(dmi_reg_rdata[31:0]), .en(dmi_reg_en), .rst_l(dbg_dm_rst_l), .clk(clk), .*);
566 :
567 : assign abmem_addr[31:0] = data1_reg[31:0];
568 : assign abmem_addr_core_local = (abmem_addr_in_dccm_region | abmem_addr_in_iccm_region | abmem_addr_in_pic_region);
569 : assign abmem_addr_external = ~abmem_addr_core_local;
570 :
571 : assign abmem_addr_in_dccm_region = (abmem_addr[31:28] == pt.DCCM_REGION) & pt.DCCM_ENABLE;
572 : assign abmem_addr_in_iccm_region = (abmem_addr[31:28] == pt.ICCM_REGION) & pt.ICCM_ENABLE;
573 : assign abmem_addr_in_pic_region = (abmem_addr[31:28] == pt.PIC_REGION);
574 :
575 : // interface for the core
576 : assign dbg_cmd_addr[31:0] = (command_reg[31:24] == 8'h2) ? data1_reg[31:0] : {20'b0, command_reg[11:0]};
577 : assign dbg_cmd_wrdata[31:0] = data0_reg[31:0];
578 : assign dbg_cmd_valid = (dbg_state == CORE_CMD_START) & ~((|abstractcs_reg[10:8]) | ((command_reg[31:24] == 8'h0) & ~command_reg[17]) | ((command_reg[31:24] == 8'h2) & abmem_addr_external)) & dma_dbg_ready;
579 : assign dbg_cmd_write = command_reg[16];
580 : assign dbg_cmd_type[1:0] = (command_reg[31:24] == 8'h2) ? 2'b10 : {1'b0, (command_reg[15:12] == 4'b0)};
581 : assign dbg_cmd_size[1:0] = command_reg[21:20];
582 :
583 : assign dbg_cmd_addr_incr[3:0] = (command_reg[31:24] == 8'h2) ? (4'h1 << sb_abmem_cmd_size[1:0]) : 4'h1;
584 : assign dbg_cmd_curr_addr[31:0] = (command_reg[31:24] == 8'h2) ? data1_reg[31:0] : {16'b0, command_reg[15:0]};
585 : assign dbg_cmd_next_addr[31:0] = dbg_cmd_curr_addr[31:0] + {28'h0,dbg_cmd_addr_incr[3:0]};
586 :
587 : // Ask DMA to stop taking bus trxns since debug request is done
588 : assign dbg_dma_bubble = ((dbg_state == CORE_CMD_START) & ~(|abstractcs_reg[10:8])) | (dbg_state == CORE_CMD_WAIT);
589 :
590 : assign sb_cmd_pending = (sb_state == CMD_RD) | (sb_state == CMD_WR) | (sb_state == CMD_WR_ADDR) | (sb_state == CMD_WR_DATA) | (sb_state == RSP_RD) | (sb_state == RSP_WR);
591 : assign sb_abmem_cmd_pending = (dbg_state == SB_CMD_START) | (dbg_state == SB_CMD_SEND) | (dbg_state== SB_CMD_RESP);
592 :
593 :
594 : // system bus FSM
595 317 : always_comb begin
596 317 : sb_nxtstate = SBIDLE;
597 317 : sb_state_en = 1'b0;
598 317 : sbcs_sbbusy_wren = 1'b0;
599 317 : sbcs_sbbusy_din = 1'b0;
600 317 : sbcs_sberror_wren = 1'b0;
601 317 : sbcs_sberror_din[2:0] = 3'b0;
602 317 : sbaddress0_reg_wren1 = 1'b0;
603 317 : case (sb_state)
604 24263142 : SBIDLE: begin
605 24263142 : sb_nxtstate = sbdata0wr_access ? WAIT_WR : WAIT_RD;
606 24263142 : sb_state_en = (sbdata0wr_access | sbreadondata_access | sbreadonaddr_access) & ~(|sbcs_reg[14:12]) & ~sbcs_reg[22];
607 24263142 : sbcs_sbbusy_wren = sb_state_en; // set the single read bit if it is a singlread command
608 24263142 : sbcs_sbbusy_din = 1'b1;
609 24263142 : sbcs_sberror_wren = sbcs_wren & (|dmi_reg_wdata[14:12]); // write to clear the error bits
610 24263142 : sbcs_sberror_din[2:0] = ~dmi_reg_wdata[14:12] & sbcs_reg[14:12];
611 : end
612 8 : WAIT_RD: begin
613 8 : sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_RD;
614 8 : sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size;
615 8 : sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;
616 8 : sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;
617 : end
618 10 : WAIT_WR: begin
619 10 : sb_nxtstate = (sbcs_unaligned | sbcs_illegal_size) ? DONE : CMD_WR;
620 10 : sb_state_en = (dbg_bus_clk_en & ~sb_abmem_cmd_pending) | sbcs_unaligned | sbcs_illegal_size;
621 10 : sbcs_sberror_wren = sbcs_unaligned | sbcs_illegal_size;
622 10 : sbcs_sberror_din[2:0] = sbcs_unaligned ? 3'b011 : 3'b100;
623 : end
624 20 : CMD_RD : begin
625 20 : sb_nxtstate = RSP_RD;
626 20 : sb_state_en = sb_bus_cmd_read & dbg_bus_clk_en;
627 : end
628 25 : CMD_WR : begin
629 25 : sb_nxtstate = (sb_bus_cmd_write_addr & sb_bus_cmd_write_data) ? RSP_WR : (sb_bus_cmd_write_data ? CMD_WR_ADDR : CMD_WR_DATA);
630 25 : sb_state_en = (sb_bus_cmd_write_addr | sb_bus_cmd_write_data) & dbg_bus_clk_en;
631 : end
632 0 : CMD_WR_ADDR : begin
633 0 : sb_nxtstate = RSP_WR;
634 0 : sb_state_en = sb_bus_cmd_write_addr & dbg_bus_clk_en;
635 : end
636 0 : CMD_WR_DATA : begin
637 0 : sb_nxtstate = RSP_WR;
638 0 : sb_state_en = sb_bus_cmd_write_data & dbg_bus_clk_en;
639 : end
640 24 : RSP_RD: begin
641 24 : sb_nxtstate = DONE;
642 24 : sb_state_en = sb_bus_rsp_read & dbg_bus_clk_en;
643 24 : sbcs_sberror_wren = sb_state_en & sb_bus_rsp_error;
644 24 : sbcs_sberror_din[2:0] = 3'b010;
645 : end
646 35 : RSP_WR: begin
647 35 : sb_nxtstate = DONE;
648 35 : sb_state_en = sb_bus_rsp_write & dbg_bus_clk_en;
649 35 : sbcs_sberror_wren = sb_state_en & sb_bus_rsp_error;
650 35 : sbcs_sberror_din[2:0] = 3'b010;
651 : end
652 18 : DONE: begin
653 18 : sb_nxtstate = SBIDLE;
654 18 : sb_state_en = 1'b1;
655 18 : sbcs_sbbusy_wren = 1'b1; // reset the single read
656 18 : sbcs_sbbusy_din = 1'b0;
657 18 : sbaddress0_reg_wren1 = sbcs_reg[16] & (sbcs_reg[14:12] == 3'b0); // auto increment was set and no error. Update to new address after completing the current command
658 : end
659 0 : default : begin
660 0 : sb_nxtstate = SBIDLE;
661 0 : sb_state_en = 1'b0;
662 0 : sbcs_sbbusy_wren = 1'b0;
663 0 : sbcs_sbbusy_din = 1'b0;
664 0 : sbcs_sberror_wren = 1'b0;
665 0 : sbcs_sberror_din[2:0] = 3'b0;
666 0 : sbaddress0_reg_wren1 = 1'b0;
667 : end
668 : endcase
669 : end // always_comb begin
670 :
671 : rvdffs #($bits(sb_state_t)) sb_state_reg (.din(sb_nxtstate), .dout({sb_state}), .en(sb_state_en), .rst_l(dbg_dm_rst_l), .clk(sb_free_clk));
672 :
673 : assign sb_abmem_cmd_write = command_reg[16];
674 : assign sb_abmem_cmd_size[2:0] = {1'b0, command_reg[21:20]};
675 : assign sb_abmem_cmd_addr[31:0] = abmem_addr[31:0];
676 : assign sb_abmem_cmd_wdata[31:0] = data0_reg[31:0];
677 :
678 : assign sb_cmd_size[2:0] = sbcs_reg[19:17];
679 : assign sb_cmd_wdata[63:0] = {sbdata1_reg[31:0], sbdata0_reg[31:0]};
680 : assign sb_cmd_addr[31:0] = sbaddress0_reg[31:0];
681 :
682 : assign sb_abmem_cmd_awvalid = (dbg_state == SB_CMD_SEND) & sb_abmem_cmd_write & ~sb_abmem_cmd_done;
683 : assign sb_abmem_cmd_wvalid = (dbg_state == SB_CMD_SEND) & sb_abmem_cmd_write & ~sb_abmem_data_done;
684 : assign sb_abmem_cmd_arvalid = (dbg_state == SB_CMD_SEND) & ~sb_abmem_cmd_write & ~sb_abmem_cmd_done & ~sb_abmem_data_done;
685 : assign sb_abmem_read_pend = (dbg_state == SB_CMD_RESP) & ~sb_abmem_cmd_write;
686 :
687 : assign sb_cmd_awvalid = ((sb_state == CMD_WR) | (sb_state == CMD_WR_ADDR));
688 : assign sb_cmd_wvalid = ((sb_state == CMD_WR) | (sb_state == CMD_WR_DATA));
689 : assign sb_cmd_arvalid = (sb_state == CMD_RD);
690 : assign sb_read_pend = (sb_state == RSP_RD);
691 :
692 : assign sb_axi_size[2:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid | sb_abmem_cmd_arvalid | sb_abmem_read_pend) ? sb_abmem_cmd_size[2:0] : sb_cmd_size[2:0];
693 : assign sb_axi_addr[31:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid | sb_abmem_cmd_arvalid | sb_abmem_read_pend) ? sb_abmem_cmd_addr[31:0] : sb_cmd_addr[31:0];
694 : assign sb_axi_wrdata[63:0] = (sb_abmem_cmd_awvalid | sb_abmem_cmd_wvalid) ? {2{sb_abmem_cmd_wdata[31:0]}} : sb_cmd_wdata[63:0];
695 :
696 : // Generic bus response signals
697 : assign sb_bus_cmd_read = sb_axi_arvalid & sb_axi_arready;
698 : assign sb_bus_cmd_write_addr = sb_axi_awvalid & sb_axi_awready;
699 : assign sb_bus_cmd_write_data = sb_axi_wvalid & sb_axi_wready;
700 :
701 : assign sb_bus_rsp_read = sb_axi_rvalid & sb_axi_rready;
702 : assign sb_bus_rsp_write = sb_axi_bvalid & sb_axi_bready;
703 : assign sb_bus_rsp_error = (sb_bus_rsp_read & (|(sb_axi_rresp[1:0]))) | (sb_bus_rsp_write & (|(sb_axi_bresp[1:0])));
704 :
705 : // AXI Request signals
706 : assign sb_axi_awvalid = sb_abmem_cmd_awvalid | sb_cmd_awvalid;
707 : assign sb_axi_awaddr[31:0] = sb_axi_addr[31:0];
708 : assign sb_axi_awid[pt.SB_BUS_TAG-1:0] = '0;
709 : assign sb_axi_awsize[2:0] = sb_axi_size[2:0];
710 : assign sb_axi_awprot[2:0] = 3'b001;
711 : assign sb_axi_awcache[3:0] = 4'b1111;
712 : assign sb_axi_awregion[3:0] = sb_axi_addr[31:28];
713 : assign sb_axi_awlen[7:0] = '0;
714 : assign sb_axi_awburst[1:0] = 2'b01;
715 : assign sb_axi_awqos[3:0] = '0;
716 : assign sb_axi_awlock = '0;
717 :
718 : assign sb_axi_wvalid = sb_abmem_cmd_wvalid | sb_cmd_wvalid;
719 : assign sb_axi_wdata[63:0] = ({64{(sb_axi_size[2:0] == 3'h0)}} & {8{sb_axi_wrdata[7:0]}}) |
720 : ({64{(sb_axi_size[2:0] == 3'h1)}} & {4{sb_axi_wrdata[15:0]}}) |
721 : ({64{(sb_axi_size[2:0] == 3'h2)}} & {2{sb_axi_wrdata[31:0]}}) |
722 : ({64{(sb_axi_size[2:0] == 3'h3)}} & {sb_axi_wrdata[63:0]});
723 : assign sb_axi_wstrb[7:0] = ({8{(sb_axi_size[2:0] == 3'h0)}} & (8'h1 << sb_axi_addr[2:0])) |
724 : ({8{(sb_axi_size[2:0] == 3'h1)}} & (8'h3 << {sb_axi_addr[2:1],1'b0})) |
725 : ({8{(sb_axi_size[2:0] == 3'h2)}} & (8'hf << {sb_axi_addr[2],2'b0})) |
726 : ({8{(sb_axi_size[2:0] == 3'h3)}} & 8'hff);
727 : assign sb_axi_wlast = '1;
728 :
729 : assign sb_axi_arvalid = sb_abmem_cmd_arvalid | sb_cmd_arvalid;
730 : assign sb_axi_araddr[31:0] = sb_axi_addr[31:0];
731 : assign sb_axi_arid[pt.SB_BUS_TAG-1:0] = '0;
732 : assign sb_axi_arsize[2:0] = sb_axi_size[2:0];
733 : assign sb_axi_arprot[2:0] = 3'b001;
734 : assign sb_axi_arcache[3:0] = 4'b0;
735 : assign sb_axi_arregion[3:0] = sb_axi_addr[31:28];
736 : assign sb_axi_arlen[7:0] = '0;
737 : assign sb_axi_arburst[1:0] = 2'b01;
738 : assign sb_axi_arqos[3:0] = '0;
739 : assign sb_axi_arlock = '0;
740 :
741 : // AXI Response signals
742 : assign sb_axi_bready = 1'b1;
743 :
744 : assign sb_axi_rready = 1'b1;
745 : assign sb_bus_rdata[63:0] = ({64{sb_axi_size == 3'h0}} & ((sb_axi_rdata[63:0] >> 8*sb_axi_addr[2:0]) & 64'hff)) |
746 : ({64{sb_axi_size == 3'h1}} & ((sb_axi_rdata[63:0] >> 16*sb_axi_addr[2:1]) & 64'hffff)) |
747 : ({64{sb_axi_size == 3'h2}} & ((sb_axi_rdata[63:0] >> 32*sb_axi_addr[2]) & 64'hffff_ffff)) |
748 : ({64{sb_axi_size == 3'h3}} & sb_axi_rdata[63:0]);
749 :
750 : `ifdef RV_ASSERT_ON
751 : // assertion.
752 : // when the resume_ack is asserted then the dec_tlu_dbg_halted should be 0
753 : dm_check_resume_and_halted: assert property (@(posedge clk) disable iff(~rst_l) (~dec_tlu_resume_ack | ~dec_tlu_dbg_halted));
754 :
755 : assert_b2b_haltreq: assert property (@(posedge clk) disable iff (~(rst_l)) (##1 dbg_halt_req |=> ~dbg_halt_req)); // One cycle delay to fix weird issue around reset
756 : assert_halt_resume_onehot: assert #0 ($onehot0({dbg_halt_req, dbg_resume_req}));
757 : `endif
758 : endmodule
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